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From: James Clark <james.clark@linaro.org>
To: Leo Yan <leo.yan@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>, Jiri Olsa <jolsa@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Mike Leach <mike.leach@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Subject: Re: [PATCH v2 09/14] perf cs-etm: Classify exception calls using the exception packet
Date: Tue, 29 Sep 2026 15:08:42 +0100	[thread overview]
Message-ID: <7bed4275-0b97-46d7-b250-5039aa95eccf@linaro.org> (raw)
In-Reply-To: <20260923-perf_cs_etm_fix_non_taken-v2-9-6ab8c07a5455@arm.com>



On 23/09/2026 16:21, Leo Yan wrote:
> ETMv4 and ETE use the same exception number for SVC, HVC and SMC.
> Identify SVC by inspecting the instruction before the preferred return
> address in the exception packet.
> 
> Preserve the exception level and preferred return address from OpenCSD,
> and use them with the packet's ISA in cs_etm__is_syscall() and
> cs_etm__is_sync_exception(). This makes exception call classification
> independent of the preceding instruction range.
> 
> Assisted-by: Codex:gpt-6
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
>   tools/perf/util/cs-etm-decoder/cs-etm-decoder.c |  7 ++++++-
>   tools/perf/util/cs-etm.c                        | 10 +++-------
>   tools/perf/util/cs-etm.h                        |  1 +
>   3 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
> index 469aba5e596a791289c5bcece132aba7b0baf6c3..48e8c355a3e495cc30dcb4056c04a034d10ce860 100644
> --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
> +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
> @@ -511,7 +511,8 @@ cs_etm_decoder__buffer_exception(struct cs_etm_queue *etmq,
>   				 struct cs_etm_packet_queue *queue,
>   				 const ocsd_generic_trace_elem *elem,
>   				 const uint8_t trace_chan_id)
> -{	int ret = 0;
> +{
> +	int ret = 0;
>   	struct cs_etm_packet *packet;
>   
>   	ret = cs_etm_decoder__buffer_packet(etmq, queue, elem, trace_chan_id,
> @@ -521,6 +522,10 @@ cs_etm_decoder__buffer_exception(struct cs_etm_queue *etmq,
>   
>   	packet = &queue->packet_buffer[queue->tail];
>   	packet->exception_number = elem->exception_number;
> +	if (elem->context.el_valid)
> +		packet->el = elem->context.exception_level;
> +	if (elem->excep_ret_addr)
> +		packet->end_addr = elem->en_addr;
>   
>   	return ret;
>   }
> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> index c8a92b5dba6001329d68766d540b9b7ead90e9e6..a40b3b2fe2e6318154111d9b7ebd05bee53934f1 100644
> --- a/tools/perf/util/cs-etm.c
> +++ b/tools/perf/util/cs-etm.c
> @@ -2019,7 +2019,7 @@ static int cs_etm__exception(struct cs_etm_traceid_queue *tidq)
>   	 * to generate branch sample for the instruction range before the
>   	 * exception is trapped to kernel or before the exception returning.
>   	 *
> -	 * The exception packet includes the dummy address values, so don't
> +	 * The exception packet does not describe an instruction range, so don't
>   	 * swap PACKET with PREV_PACKET.  This keeps PREV_PACKET to be useful
>   	 * for generating instruction and branch samples.
>   	 */
> @@ -2225,7 +2225,6 @@ static bool cs_etm__is_syscall(struct cs_etm_queue *etmq,
>   			       struct cs_etm_traceid_queue *tidq, u64 magic)
>   {
>   	struct cs_etm_packet *packet = tidq->packet;
> -	struct cs_etm_packet *prev_packet = tidq->prev_packet;
>   
>   	if (magic == __perf_cs_etmv3_magic)
>   		if (packet->exception_number == CS_ETMV3_EXC_SVC)
> @@ -2238,8 +2237,7 @@ static bool cs_etm__is_syscall(struct cs_etm_queue *etmq,
>   	 */
>   	if (magic == __perf_cs_etmv4_magic || magic == __perf_cs_ete_magic) {
>   		if (packet->exception_number == CS_ETMV4_EXC_CALL &&
> -		    cs_etm__is_svc_instr(etmq, tidq, prev_packet,
> -					 prev_packet->end_addr))
> +		    cs_etm__is_svc_instr(etmq, tidq, packet, packet->end_addr))
>   			return true;
>   	}
>   
> @@ -2277,7 +2275,6 @@ static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq,
>   				      u64 magic)
>   {
>   	struct cs_etm_packet *packet = tidq->packet;
> -	struct cs_etm_packet *prev_packet = tidq->prev_packet;
>   
>   	if (magic == __perf_cs_etmv3_magic)
>   		if (packet->exception_number == CS_ETMV3_EXC_SMC ||
> @@ -2301,8 +2298,7 @@ static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq,
>   		 * (SMC, HVC) are taken as sync exceptions.
>   		 */
>   		if (packet->exception_number == CS_ETMV4_EXC_CALL &&
> -		    !cs_etm__is_svc_instr(etmq, tidq, prev_packet,
> -					  prev_packet->end_addr))
> +		    !cs_etm__is_svc_instr(etmq, tidq, packet, packet->end_addr))
>   			return true;
>   
>   		/*
> diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h
> index b81099c2b301c25f894cc9a50edfde87aceff49d..4d03f2a680b58aacd91c9f6c957fb2d38e7ac2ad 100644
> --- a/tools/perf/util/cs-etm.h
> +++ b/tools/perf/util/cs-etm.h
> @@ -174,6 +174,7 @@ struct cs_etm_packet {
>   	enum cs_etm_sample_type sample_type;
>   	enum cs_etm_isa isa;
>   	u64 start_addr;
> +	/* For exceptions: preferred return address, or CS_ETM_INVAL_ADDR. */
>   	u64 end_addr;

Minor nit, but you could use a union. I don't know how clear re-using 
"end_addr" id for exception packets is when reading the code.

        union {
            u64 end_addr; // Range packets
            u64 pref_ret_addr; // Exception packets
        };


>   	u32 instr_count;
>   	u32 last_instr_type;
> 


  reply	other threads:[~2026-09-29 14:08 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-23 15:21 [PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions Leo Yan
2026-09-23 15:21 ` [PATCH v2 01/14] perf sample: Allow decoders to supply branch return addresses Leo Yan
2026-09-24 13:00   ` Adrian Hunter
2026-09-23 15:21 ` [PATCH v2 02/14] perf intel-pt: Preserve return addresses for asynchronous branches Leo Yan
2026-09-24 13:00   ` Adrian Hunter
2026-09-23 15:21 ` [PATCH v2 03/14] perf cs-etm: Break branch history when instruction memory is unavailable Leo Yan
2026-09-23 15:21 ` [PATCH v2 04/14] perf cs-etm: Centralize packet ISA initialization Leo Yan
2026-09-23 15:21 ` [PATCH v2 05/14] perf cs-etm: Use the recorded instruction size for A32 and A64 Leo Yan
2026-09-29 13:55   ` James Clark
2026-09-23 15:21 ` [PATCH v2 06/14] perf cs-etm: Mark branches that were not taken Leo Yan
2026-09-23 15:21 ` [PATCH v2 07/14] perf cs-etm: Factor out final instruction sample synthesis Leo Yan
2026-09-23 15:21 ` [PATCH v2 08/14] perf cs-etm: Centralize branch sample synthesis checks Leo Yan
2026-09-23 15:21 ` [PATCH v2 09/14] perf cs-etm: Classify exception calls using the exception packet Leo Yan
2026-09-29 14:08   ` James Clark [this message]
2026-09-23 15:21 ` [PATCH v2 10/14] perf cs-etm: Synthesize exception entries separately from branches Leo Yan
2026-09-23 15:21 ` [PATCH v2 11/14] perf tests: Check CoreSight IRQ entry and exit Leo Yan
2026-09-29 12:22   ` James Clark
2026-09-23 15:21 ` [PATCH v2 12/14] perf tests: Check CoreSight syscall " Leo Yan
2026-09-23 15:21 ` [PATCH v2 13/14] perf tests: Check CoreSight abort " Leo Yan
2026-09-23 15:21 ` [PATCH v2 14/14] perf tests: Check CoreSight emulated instruction " Leo Yan
2026-09-29 14:41 ` [PATCH v2 00/14] perf cs-etm: Fix bogus branch samples on exceptions James Clark

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