From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Chris Wilson" <chris.p.wilson@intel.com>,
"Fei Yang" <fei.yang@intel.com>,
"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Dave Airlie" <airlied@redhat.com>,
"David Airlie" <airlied@linux.ie>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com,
"Andi Shyti" <andi.shyti@linux.intel.com>,
stable@vger.kernel.org,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: Re: [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation
Date: Thu, 16 Jun 2022 08:33:24 +0100 [thread overview]
Message-ID: <7c29c710-64ee-6e87-afb4-6d6b51e26315@linux.intel.com> (raw)
In-Reply-To: <387b9a8d3e719ad2db4fce56c0bfc0f909fd6df6.1655306128.git.mchehab@kernel.org>
On 15/06/2022 16:27, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@intel.com>
>
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of of concurrent access
> and stale access from prefetch.
>
> We only need to invalidate the TLB if they are accessible by the user.
>
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Same question as against the other patch - fix or optimisation?
Regards,
Tvrtko
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Fei Yang <fei.yang@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
> ---
>
> See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/
>
> drivers/gpu/drm/i915/i915_vma.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 0bffb70b3c5f..7989986161e8 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -537,7 +537,8 @@ int i915_vma_bind(struct i915_vma *vma,
> bind_flags);
> }
>
> - set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags);
> + if (bind_flags & I915_VMA_LOCAL_BIND)
> + set_bit(I915_BO_WAS_BOUND_BIT, &vma->obj->flags);
>
> atomic_or(bind_flags, &vma->flags);
> return 0;
next prev parent reply other threads:[~2022-06-16 7:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-15 15:27 [PATCH 0/6] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-06-16 7:21 ` Tvrtko Ursulin
2022-06-23 11:04 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 2/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-06-15 17:03 ` [Intel-gfx] " Umesh Nerlige Ramappa
2022-06-23 11:07 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-06-16 7:25 ` Tvrtko Ursulin
2022-06-23 11:08 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-06-16 7:33 ` Tvrtko Ursulin [this message]
2022-06-23 11:13 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab
2022-06-16 7:35 ` Tvrtko Ursulin
2022-06-23 11:17 ` Andi Shyti
2022-06-24 8:34 ` Tvrtko Ursulin
2022-06-27 9:00 ` Mauro Carvalho Chehab
2022-06-28 15:49 ` Tvrtko Ursulin
2022-06-29 15:30 ` Mauro Carvalho Chehab
2022-06-29 16:02 ` Tvrtko Ursulin
2022-06-30 7:32 ` Mauro Carvalho Chehab
2022-06-30 8:12 ` Tvrtko Ursulin
2022-06-30 16:01 ` Mauro Carvalho Chehab
2022-07-01 7:56 ` Tvrtko Ursulin
2022-07-04 8:42 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Mauro Carvalho Chehab
2022-06-23 11:18 ` Andi Shyti
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7c29c710-64ee-6e87-afb4-6d6b51e26315@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=airlied@linux.ie \
--cc=airlied@redhat.com \
--cc=andi.shyti@linux.intel.com \
--cc=chris.p.wilson@intel.com \
--cc=daniel@ffwll.ch \
--cc=dri-devel@lists.freedesktop.org \
--cc=fei.yang@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@linux.intel.com \
--cc=joonas.lahtinen@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mauro.chehab@linux.intel.com \
--cc=mchehab@kernel.org \
--cc=rodrigo.vivi@intel.com \
--cc=stable@vger.kernel.org \
--cc=thomas.hellstrom@intel.com \
--cc=thomas.hellstrom@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome