From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: "Chris Wilson" <chris.p.wilson@intel.com>,
"Fei Yang" <fei.yang@intel.com>,
"Michał Winiarski" <michal.winiarski@intel.com>,
"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Andi Shyti" <andi.shyti@linux.intel.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
"Dave Airlie" <airlied@redhat.com>,
"David Airlie" <airlied@linux.ie>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Matt Roper" <matthew.d.roper@intel.com>,
"Matthew Auld" <matthew.auld@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
stable@vger.kernel.org
Subject: [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets
Date: Wed, 15 Jun 2022 16:27:40 +0100 [thread overview]
Message-ID: <cd5696e3800fd29114ddf0cebc950b57a17bc1b8.1655306128.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1655306128.git.mchehab@kernel.org>
From: Chris Wilson <chris.p.wilson@intel.com>
Avoid trying to invalidate the TLB in the middle of performing an
engine reset, as this may result in the reset timing out. Currently,
the TLB invalidate is only serialised by its own mutex, forgoing the
uncore lock, but we can take the uncore->lock as well to serialise
the mmio access, thereby serialising with the GDRST.
Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with
i915 selftest/hangcheck.
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Reported-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Tested-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: stable@vger.kernel.org
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---
See [PATCH 0/6] at: https://lore.kernel.org/all/cover.1655306128.git.mchehab@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index fb4fd5273ca4..33eb93586858 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1248,6 +1248,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
mutex_lock(>->tlb_invalidate_lock);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
+ spin_lock_irq(&uncore->lock); /* seralise invalidate with GT reset */
+
awake = 0;
for_each_engine(engine, gt, id) {
struct reg_and_bit rb;
@@ -1272,6 +1274,8 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
IS_ALDERLAKE_P(i915)))
intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
+ spin_unlock_irq(&uncore->lock);
+
for_each_engine_masked(engine, gt, awake, tmp) {
struct reg_and_bit rb;
--
2.36.1
next prev parent reply other threads:[~2022-06-15 15:29 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-15 15:27 [PATCH 0/6] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab
2022-06-15 15:27 ` [PATCH 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-06-16 7:21 ` Tvrtko Ursulin
2022-06-23 11:04 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 2/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-06-15 17:03 ` [Intel-gfx] " Umesh Nerlige Ramappa
2022-06-23 11:07 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-06-16 7:25 ` Tvrtko Ursulin
2022-06-23 11:08 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-06-16 7:33 ` Tvrtko Ursulin
2022-06-23 11:13 ` Andi Shyti
2022-06-15 15:27 ` [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab
2022-06-16 7:35 ` Tvrtko Ursulin
2022-06-23 11:17 ` Andi Shyti
2022-06-24 8:34 ` Tvrtko Ursulin
2022-06-27 9:00 ` Mauro Carvalho Chehab
2022-06-28 15:49 ` Tvrtko Ursulin
2022-06-29 15:30 ` Mauro Carvalho Chehab
2022-06-29 16:02 ` Tvrtko Ursulin
2022-06-30 7:32 ` Mauro Carvalho Chehab
2022-06-30 8:12 ` Tvrtko Ursulin
2022-06-30 16:01 ` Mauro Carvalho Chehab
2022-07-01 7:56 ` Tvrtko Ursulin
2022-07-04 8:42 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` Mauro Carvalho Chehab [this message]
2022-06-23 11:18 ` [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Andi Shyti
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