* [GIT PULL] RISC-V updates for v7.4
@ 2026-10-29 3:32 Paul Walmsley
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From: Paul Walmsley @ 2026-10-29 3:32 UTC (permalink / raw)
To: torvalds; +Cc: linux-kernel, linux-riscv
[-- Attachment #1: Type: text/plain, Size: 12941 bytes --]
Linus,
Please pull these RISC-V updates for v7.4. These are mostly
optimizations, fixes, and preparation for work that we're planning for
v7.5 - there's not much in terms of new features this time.
thanks,
- Paul
The following changes since commit 282f4a8aa95c5a01b96e55eb5da297560e5f2986:
riscv: lib: Fix ZBB strnlen wrap-around regression on huge counts (2026-10-05 19:02:38 -0600)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-7.4-mw1
for you to fetch changes up to a5ae1bf65cee84bcc121d659e7e22a767853f5f5:
riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled (2026-10-08 15:40:07 -0600)
----------------------------------------------------------------
RISC-V updates for v7.4
- Add support for crash hotplug
- Improve user copy performance on cores with fast misaligned
accesses
- Optimize code paths involving pgtable_l{4,5}_enabled() by patching
in the return values during early boot (since these don't change
during runtime), or by specifying the return values directly in
Kconfig files (for purpose-built kernels)
- Change the PCIe bus reassignment behavior to depend on the
PCI_REASSIGN_ALL_BUS PCI flag (as ARM64 does)
- Avoid an unnecessary sstatus CSR read during context switch
- Make the sbi_ecall() macro variadic, improving code clarity
- Refactor __switch_to_vector() to prepare for upcoming vector context
switch optimizations
- Add a kselftest for vectorized user copy
- Add bounds checking on the shadow stack restore token address to
avoid it being used as an attack vector
- Fix the shadow stack and indirect branch landing pad control functions to
only update the CPU's envcfg CSR when operating on the current task
- For MIPS RISC-V systems, add support for early boot-applied errata;
and for P8700 RISC-V systems, avoid WFI usage in the kernel (since
it is buggy)
- Add the "B" RISC-V ISA extension to hwcap and hwprobe reporting
- Add support for specifying and reporting the "Zic64b" RISC-V ISA
extension, and add it to the SpacemiT K1, K3, and Sophgo SG2044 DT
files
- Require the block size of cache management operations to be
specified in DT schema validation for the RISC-V ISA extensions
Zicbom, Zicbop, and Zicboz
- Some miscellaneous fixes: fix an incorrect bitfield width in the
RVG_SYSTEM_CSR_MASK bitmask macro; make RISCV_ALTERNATIVE mandatory,
now that XIP kernel support has been removed; and remove some
unnecessary includes in kernel/smp.c
----------------------------------------------------------------
Aleksa Paunovic (1):
riscv: Add support for early boot errata application on MIPS chips
Andrew Jones (2):
riscv: Add B to hwcap and hwprobe
riscv: Add a getter for user PMLEN support
Andy Chiu (5):
riscv: introduce assembly version of jump table
riscv: optmize ucopy for has_fast_unaligned_accesses
riscv: do not read csr in vector context switch
riscv: vector: refactor context switch for kernel-mode vector
selftest: riscv: test vectorized user copy
Anthony Iliopoulos (1):
riscv: remove unused profile.h includes
Aurelien Jarno (1):
riscv: fix RVG_SYSTEM_CSR_MASK width mask
Djordje Todorovic (1):
riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause
Guodong Xu (5):
dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz
dt-bindings: riscv: Add Zic64b extension description
riscv: dts: spacemit: k3: Add Zic64b ISA extension
riscv: dts: spacemit: k1: Add Zic64b ISA extension
riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
Jisheng Zhang (5):
riscv: remove RISCV_ALTERNATIVE Kconfig option
riscv: convert pgtable_l4|l5_enabled to inline function
riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled
riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57
riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled
Qingwei Hu (1):
riscv: Add Zic64b to cpufeature and hwprobe
Radim Krčmář (2):
RISC-V: sbi: turn sbi_ecall into variadic macro
RISC-V: make use of variadic sbi_ecall
Rui Qi (1):
riscv: crash: Add crash hotplug support
Samuel Holland (2):
riscv: cfi: Bounds check restore token before swap
riscv: cfi: Only write envcfg CSR when task is current
sun wenhan (1):
riscv: align pcie bus assign logic with ARM64
Documentation/arch/riscv/hwprobe.rst | 8 +
.../devicetree/bindings/riscv/extensions.yaml | 54 +++++
arch/riscv/Kconfig | 51 ++---
arch/riscv/Kconfig.errata | 18 +-
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 128 ++++++------
arch/riscv/boot/dts/spacemit/k1.dtsi | 80 ++++----
arch/riscv/boot/dts/spacemit/k3.dtsi | 48 ++---
arch/riscv/errata/mips/Makefile | 6 +
arch/riscv/errata/mips/errata.c | 55 +++--
arch/riscv/include/asm/alternative-macros.h | 24 ---
arch/riscv/include/asm/alternative.h | 12 +-
arch/riscv/include/asm/cpufeature-macros.h | 10 +-
arch/riscv/include/asm/cpufeature.h | 8 +-
arch/riscv/include/asm/errata_list.h | 37 ++++
arch/riscv/include/asm/errata_list_vendors.h | 5 +-
arch/riscv/include/asm/hwcap.h | 4 +
arch/riscv/include/asm/insn.h | 2 +-
arch/riscv/include/asm/jump_label.h | 26 +++
arch/riscv/include/asm/kexec.h | 13 ++
arch/riscv/include/asm/kvm_nacl.h | 4 +-
arch/riscv/include/asm/pci.h | 5 +
arch/riscv/include/asm/pgalloc.h | 14 +-
arch/riscv/include/asm/pgtable-32.h | 4 +-
arch/riscv/include/asm/pgtable-64.h | 74 +++++--
arch/riscv/include/asm/pgtable.h | 4 +-
arch/riscv/include/asm/processor.h | 7 +-
arch/riscv/include/asm/sbi.h | 81 +++++++-
arch/riscv/include/asm/vector.h | 8 +-
arch/riscv/include/asm/vendor_extensions.h | 18 +-
arch/riscv/include/asm/vmalloc.h | 5 +-
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 2 +
arch/riscv/kernel/Makefile | 3 +-
arch/riscv/kernel/alternative.c | 24 ++-
arch/riscv/kernel/cpu.c | 4 +-
arch/riscv/kernel/cpu_ops_sbi.c | 6 +-
arch/riscv/kernel/cpufeature.c | 91 ++++++++-
arch/riscv/kernel/crash.c | 113 +++++++++++
arch/riscv/kernel/head.S | 4 +-
arch/riscv/kernel/kernel_mode_vector.c | 9 +-
arch/riscv/kernel/paravirt.c | 2 +-
arch/riscv/kernel/process.c | 12 ++
arch/riscv/kernel/sbi.c | 57 +++---
arch/riscv/kernel/sbi_ecall.c | 38 ++--
arch/riscv/kernel/smp.c | 1 -
arch/riscv/kernel/suspend.c | 4 +-
arch/riscv/kernel/sys_hwprobe.c | 2 +
arch/riscv/kernel/usercfi.c | 20 +-
arch/riscv/kvm/nacl.c | 7 +-
arch/riscv/lib/uaccess.S | 61 +++---
arch/riscv/mm/init.c | 79 +++++---
arch/riscv/mm/kasan_init.c | 20 +-
arch/riscv/mm/pgtable.c | 4 +-
arch/riscv/mm/ptdump.c | 4 +-
drivers/acpi/riscv/cppc.c | 4 +-
drivers/perf/riscv_pmu_sbi.c | 43 ++--
tools/testing/selftests/riscv/vector/Makefile | 6 +-
.../selftests/riscv/vector/v_uaccess_stress.c | 221 +++++++++++++++++++++
58 files changed, 1170 insertions(+), 485 deletions(-)
create mode 100644 arch/riscv/kernel/crash.c
create mode 100644 tools/testing/selftests/riscv/vector/v_uaccess_stress.c
vmlinux size differences in bytes (from 282f4a8aa95c):
text data bss dec hex filename
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+19525 +5164 . +24689 +6071 vmlinux.nosmp_defconfig.gcc-16
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+2969 +1544 . +4513 +11a1 vmlinux.rv32_defconfig.clang-17
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+950 -976 . -26 -1a vmlinux.nommu_virt_defconfig.clang-17
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+2865 +1352 . +4217 +1079 vmlinux.rv32_defconfig.gcc-11
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-24610 +8068 -16384 -32926 -809e vmlinux.allnoconfig.clang-19
-611151 -146228 -32 -757411 -b8ea3 vmlinux.allmodconfig.clang-19
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