From: Gavin Shan <gshan@redhat.com>
To: Ben Horgan <ben.horgan@arm.com>, james.morse@arm.com
Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com,
baolin.wang@linux.alibaba.com, bobo.shaobowang@huawei.com,
carl@os.amperecomputing.com, catalin.marinas@arm.com,
dakr@kernel.org, dave.martin@arm.com, david@redhat.com,
dfustini@baylibre.com, fenghuay@nvidia.com,
gregkh@linuxfoundation.org, guohanjun@huawei.com,
jeremy.linton@arm.com, jonathan.cameron@huawei.com,
kobak@nvidia.com, lcherian@marvell.com, lenb@kernel.org,
linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, lpieralisi@kernel.org,
peternewman@google.com, quic_jiles@quicinc.com,
rafael@kernel.org, robh@kernel.org, rohit.mathew@arm.com,
scott@os.amperecomputing.com, sdonthineni@nvidia.com,
sudeep.holla@arm.com, tan.shaopeng@fujitsu.com, will@kernel.org,
xhao@linux.alibaba.com,
Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Subject: Re: [PATCH 14/33] arm_mpam: Probe hardware to find the supported partid/pmg values
Date: Sun, 9 Nov 2025 10:43:27 +1000 [thread overview]
Message-ID: <7d0c73d3-1943-469f-813a-eba1dac38d4a@redhat.com> (raw)
In-Reply-To: <20251107123450.664001-15-ben.horgan@arm.com>
Hi Ben,
On 11/7/25 10:34 PM, Ben Horgan wrote:
> From: James Morse <james.morse@arm.com>
>
> CPUs can generate traffic with a range of PARTID and PMG values,
> but each MSC may also have its own maximum size for these fields.
> Before MPAM can be used, the driver needs to probe each RIS on
> each MSC, to find the system-wide smallest value that can be used.
> The limits from requestors (e.g. CPUs) also need taking into account.
>
> While doing this, RIS entries that firmware didn't describe are created
> under MPAM_CLASS_UNKNOWN.
>
> This adds the low level MSC write accessors.
>
> While we're here, implement the mpam_register_requestor() call
> for the arch code to register the CPU limits. Future callers of this
> will tell us about the SMMU and ITS.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Ben Horgan <ben.horgan@arm.com>
> Tested-by: Fenghua Yu <fenghuay@nvidia.com>
> Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
> Tested-by: Peter Newman <peternewman@google.com>
> Signed-off-by: Ben Horgan <ben.horgan@arm.com>
> ---
> Changes since v3:
> From Jonathan:
> Stray comma in printk
> Unnecessary braces
> ---
> drivers/resctrl/mpam_devices.c | 148 +++++++++++++++++++++++++++++++-
> drivers/resctrl/mpam_internal.h | 6 ++
> include/linux/arm_mpam.h | 14 +++
> 3 files changed, 167 insertions(+), 1 deletion(-)
>
One comment related to 'partid_max_init', but this looks good to me in
either way:
Reviewed-by: Gavin Shan <gshan@redhat.com>
> diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
> index 4162a7a57626..e1e26cb350f7 100644
> --- a/drivers/resctrl/mpam_devices.c
> +++ b/drivers/resctrl/mpam_devices.c
> @@ -6,6 +6,7 @@
> #include <linux/acpi.h>
> #include <linux/atomic.h>
> #include <linux/arm_mpam.h>
> +#include <linux/bitfield.h>
> #include <linux/cacheinfo.h>
> #include <linux/cpu.h>
> #include <linux/cpumask.h>
> @@ -42,6 +43,15 @@ static atomic_t mpam_num_msc;
> static int mpam_cpuhp_state;
> static DEFINE_MUTEX(mpam_cpuhp_state_lock);
>
> +/*
> + * The smallest common values for any CPU or MSC in the system.
> + * Generating traffic outside this range will result in screaming interrupts.
> + */
> +u16 mpam_partid_max;
> +u8 mpam_pmg_max;
> +static bool partid_max_init, partid_max_published;
> +static DEFINE_SPINLOCK(partid_max_lock);
> +
If mpam_partid_max and mpam_pmg_max are initialized to USHRT_MAX and 255 here,
the state related to partid_max_init can be removed...
> /*
> * mpam is enabled once all devices have been probed from CPU online callbacks,
> * scheduled via this work_struct. If access to an MSC depends on a CPU that
> @@ -142,6 +152,70 @@ static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg)
>
> #define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc, MPAMF_##reg)
>
> +static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
> +{
> + WARN_ON_ONCE(reg + sizeof(u32) >= msc->mapped_hwpage_sz);
> + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
> +
> + writel_relaxed(val, msc->mapped_hwpage + reg);
> +}
> +
> +static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
> +{
> + lockdep_assert_held_once(&msc->part_sel_lock);
> + __mpam_write_reg(msc, reg, val);
> +}
> +
> +#define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc, MPAMCFG_##reg, val)
> +
> +static u64 mpam_msc_read_idr(struct mpam_msc *msc)
> +{
> + u64 idr_high = 0, idr_low;
> +
> + lockdep_assert_held(&msc->part_sel_lock);
> +
> + idr_low = mpam_read_partsel_reg(msc, IDR);
> + if (FIELD_GET(MPAMF_IDR_EXT, idr_low))
> + idr_high = mpam_read_partsel_reg(msc, IDR + 4);
> +
> + return (idr_high << 32) | idr_low;
> +}
> +
> +static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
> +{
> + lockdep_assert_held(&msc->part_sel_lock);
> +
> + mpam_write_partsel_reg(msc, PART_SEL, partsel);
> +}
> +
> +static void __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc)
> +{
> + u32 partsel = FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) |
> + FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, partid);
> +
> + __mpam_part_sel_raw(partsel, msc);
> +}
> +
> +int mpam_register_requestor(u16 partid_max, u8 pmg_max)
> +{
> + guard(spinlock)(&partid_max_lock);
> + if (!partid_max_init) {
> + mpam_partid_max = partid_max;
> + mpam_pmg_max = pmg_max;
> + partid_max_init = true;
> + } else if (!partid_max_published) {
> + mpam_partid_max = min(mpam_partid_max, partid_max);
> + mpam_pmg_max = min(mpam_pmg_max, pmg_max);
> + } else {
> + /* New requestors can't lower the values */
> + if (partid_max < mpam_partid_max || pmg_max < mpam_pmg_max)
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(mpam_register_requestor);
> +
With mpam_partid_max and mpam_pmg_max initialized to USHRT_MAX and 255, this
can be:
if (!partid_max_published) {
...
} else {
...
}
> static struct mpam_vmsc *
> mpam_vmsc_alloc(struct mpam_component *comp, struct mpam_msc *msc)
> {
> @@ -451,9 +525,35 @@ int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
> return err;
> }
>
> +static struct mpam_msc_ris *mpam_get_or_create_ris(struct mpam_msc *msc,
> + u8 ris_idx)
> +{
> + int err;
> + struct mpam_msc_ris *ris;
> +
> + lockdep_assert_held(&mpam_list_lock);
> +
> + if (!test_bit(ris_idx, &msc->ris_idxs)) {
> + err = mpam_ris_create_locked(msc, ris_idx, MPAM_CLASS_UNKNOWN,
> + 0, 0);
> + if (err)
> + return ERR_PTR(err);
> + }
> +
> + list_for_each_entry(ris, &msc->ris, msc_list) {
> + if (ris->ris_idx == ris_idx)
> + return ris;
> + }
> +
> + return ERR_PTR(-ENOENT);
> +}
> +
> static int mpam_msc_hw_probe(struct mpam_msc *msc)
> {
> u64 idr;
> + u16 partid_max;
> + u8 ris_idx, pmg_max;
> + struct mpam_msc_ris *ris;
> struct device *dev = &msc->pdev->dev;
>
> lockdep_assert_held(&msc->probe_lock);
> @@ -464,6 +564,40 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
> return -EIO;
> }
>
> + /* Grab an IDR value to find out how many RIS there are */
> + mutex_lock(&msc->part_sel_lock);
> + idr = mpam_msc_read_idr(msc);
> + mutex_unlock(&msc->part_sel_lock);
> +
> + msc->ris_max = FIELD_GET(MPAMF_IDR_RIS_MAX, idr);
> +
> + /* Use these values so partid/pmg always starts with a valid value */
> + msc->partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
> + msc->pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
> +
> + for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
> + mutex_lock(&msc->part_sel_lock);
> + __mpam_part_sel(ris_idx, 0, msc);
> + idr = mpam_msc_read_idr(msc);
> + mutex_unlock(&msc->part_sel_lock);
> +
> + partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
> + pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
> + msc->partid_max = min(msc->partid_max, partid_max);
> + msc->pmg_max = min(msc->pmg_max, pmg_max);
> +
> + mutex_lock(&mpam_list_lock);
> + ris = mpam_get_or_create_ris(msc, ris_idx);
> + mutex_unlock(&mpam_list_lock);
> + if (IS_ERR(ris))
> + return PTR_ERR(ris);
> + }
> +
> + spin_lock(&partid_max_lock);
> + mpam_partid_max = min(mpam_partid_max, msc->partid_max);
> + mpam_pmg_max = min(mpam_pmg_max, msc->pmg_max);
> + spin_unlock(&partid_max_lock);
> +
> msc->probed = true;
>
> return 0;
> @@ -686,10 +820,20 @@ static struct platform_driver mpam_msc_driver = {
>
> static void mpam_enable_once(void)
> {
> + /*
> + * Once the cpuhp callbacks have been changed, mpam_partid_max can no
> + * longer change.
> + */
> + spin_lock(&partid_max_lock);
> + partid_max_published = true;
> + spin_unlock(&partid_max_lock);
> +
> mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline,
> "mpam:online");
>
> - pr_info("MPAM enabled\n");
> + /* Use printk() to avoid the pr_fmt adding the function name. */
> + printk(KERN_INFO "MPAM enabled with %u PARTIDs and %u PMGs\n",
> + mpam_partid_max + 1, mpam_pmg_max + 1);
> }
>
> void mpam_disable(struct work_struct *ignored)
> @@ -756,4 +900,6 @@ static int __init mpam_msc_driver_init(void)
>
> return platform_driver_register(&mpam_msc_driver);
> }
> +
> +/* Must occur after arm64_mpam_register_cpus() from arch_initcall() */
> subsys_initcall(mpam_msc_driver_init);
> diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
> index 4e1538d29783..768a58a3ab27 100644
> --- a/drivers/resctrl/mpam_internal.h
> +++ b/drivers/resctrl/mpam_internal.h
> @@ -49,6 +49,8 @@ struct mpam_msc {
> */
> struct mutex probe_lock;
> bool probed;
> + u16 partid_max;
> + u8 pmg_max;
> unsigned long ris_idxs;
> u32 ris_max;
>
> @@ -138,6 +140,10 @@ struct mpam_msc_ris {
> extern struct srcu_struct mpam_srcu;
> extern struct list_head mpam_classes;
>
> +/* System wide partid/pmg values */
> +extern u16 mpam_partid_max;
> +extern u8 mpam_pmg_max;
> +
> /* Scheduled work callback to enable mpam once all MSC have been probed */
> void mpam_enable(struct work_struct *work);
> void mpam_disable(struct work_struct *work);
> diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h
> index 5a3aab6bb1d4..c7246cfeb091 100644
> --- a/include/linux/arm_mpam.h
> +++ b/include/linux/arm_mpam.h
> @@ -49,4 +49,18 @@ static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
> }
> #endif
>
> +/**
> + * mpam_register_requestor() - Register a requestor with the MPAM driver
> + * @partid_max: The maximum PARTID value the requestor can generate.
> + * @pmg_max: The maximum PMG value the requestor can generate.
> + *
> + * Registers a requestor with the MPAM driver to ensure the chosen system-wide
> + * minimum PARTID and PMG values will allow the requestors features to be used.
> + *
> + * Returns an error if the registration is too late, and a larger PARTID/PMG
> + * value has been advertised to user-space. In this case the requestor should
> + * not use its MPAM features. Returns 0 on success.
> + */
> +int mpam_register_requestor(u16 partid_max, u8 pmg_max);
> +
> #endif /* __LINUX_ARM_MPAM_H */
Thanks,
Gavin
next prev parent reply other threads:[~2025-11-09 0:43 UTC|newest]
Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-07 12:34 [PATCH 00/33] arm_mpam: Add basic mpam driver Ben Horgan
2025-11-07 12:34 ` [PATCH 01/33] ACPI / PPTT: Add a helper to fill a cpumask from a processor container Ben Horgan
2025-11-08 4:31 ` Gavin Shan
2025-11-12 10:14 ` Ben Horgan
2025-11-12 5:45 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 02/33] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels Ben Horgan
2025-11-11 7:34 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 03/33] ACPI / PPTT: Add acpi_pptt_cache_v1_full to use pptt cache as one structure Ben Horgan
2025-11-08 4:54 ` Gavin Shan
2025-11-10 15:51 ` Ben Horgan
2025-11-10 15:46 ` Jonathan Cameron
2025-11-10 16:28 ` Ben Horgan
2025-11-10 17:00 ` Jeremy Linton
2025-11-11 16:48 ` Ben Horgan
2025-11-12 20:22 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 04/33] ACPI / PPTT: Find cache level by cache-id Ben Horgan
2025-11-08 5:11 ` Gavin Shan
2025-11-10 16:02 ` Jonathan Cameron
2025-11-11 17:02 ` Ben Horgan
2025-11-12 20:23 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 05/33] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id Ben Horgan
2025-11-08 5:10 ` Gavin Shan
2025-11-10 16:04 ` Jonathan Cameron
2025-11-12 20:26 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 06/33] arm64: kconfig: Add Kconfig entry for MPAM Ben Horgan
2025-11-07 12:34 ` [PATCH 07/33] platform: Define platform_device_put cleanup handler Ben Horgan
2025-11-10 1:03 ` Gavin Shan
2025-11-10 16:07 ` Jonathan Cameron
2025-11-12 20:32 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 08/33] ACPI: Define acpi_put_table cleanup handler and acpi_get_table_ret() helper Ben Horgan
2025-11-10 1:03 ` Gavin Shan
2025-11-10 16:11 ` Jonathan Cameron
2025-11-12 7:02 ` Shaopeng Tan (Fujitsu)
2025-11-12 20:39 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 09/33] ACPI / MPAM: Parse the MPAM table Ben Horgan
2025-11-08 8:54 ` Gavin Shan
2025-11-10 16:27 ` Jonathan Cameron
2025-11-12 14:45 ` Ben Horgan
2025-11-10 16:23 ` Jonathan Cameron
2025-11-12 7:01 ` Shaopeng Tan (Fujitsu)
2025-11-12 14:55 ` Ben Horgan
2025-11-13 2:16 ` Fenghua Yu
2025-11-13 12:09 ` Ben Horgan
2025-11-13 2:33 ` Fenghua Yu
2025-11-13 14:24 ` Ben Horgan
2025-11-07 12:34 ` [PATCH 10/33] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate Ben Horgan
2025-11-08 9:28 ` Gavin Shan
2025-11-10 16:44 ` Jonathan Cameron
2025-11-12 15:32 ` Ben Horgan
2025-11-10 16:58 ` Jonathan Cameron
2025-11-12 16:05 ` Ben Horgan
2025-11-12 7:22 ` Shaopeng Tan (Fujitsu)
2025-11-12 15:37 ` Ben Horgan
2025-11-13 2:46 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 11/33] arm_mpam: Add the class and component structures for firmware described ris Ben Horgan
2025-11-09 0:07 ` Gavin Shan
2025-11-12 16:39 ` Ben Horgan
2025-11-12 16:48 ` Ben Horgan
2025-11-10 17:10 ` Jonathan Cameron
2025-11-12 17:21 ` Ben Horgan
2025-11-12 7:29 ` Shaopeng Tan (Fujitsu)
2025-11-13 3:23 ` Fenghua Yu
2025-11-13 16:39 ` Ben Horgan
2025-11-07 12:34 ` [PATCH 12/33] arm_mpam: Add MPAM MSC register layout definitions Ben Horgan
2025-11-09 0:25 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 13/33] arm_mpam: Add cpuhp callbacks to probe MSC hardware Ben Horgan
2025-11-07 12:34 ` [PATCH 14/33] arm_mpam: Probe hardware to find the supported partid/pmg values Ben Horgan
2025-11-09 0:43 ` Gavin Shan [this message]
2025-11-10 23:26 ` Gavin Shan
2025-11-11 9:30 ` Ben Horgan
2025-11-12 7:57 ` Shaopeng Tan (Fujitsu)
2025-11-13 3:50 ` Fenghua Yu
2025-11-13 16:43 ` Ben Horgan
2025-11-07 12:34 ` [PATCH 15/33] arm_mpam: Add helpers for managing the locking around the mon_sel registers Ben Horgan
2025-11-09 0:49 ` Gavin Shan
2025-11-12 8:03 ` Shaopeng Tan (Fujitsu)
2025-11-13 3:52 ` Fenghua Yu
2025-11-07 12:34 ` [PATCH 16/33] arm_mpam: Probe the hardware features resctrl supports Ben Horgan
2025-11-09 21:55 ` Gavin Shan
2025-11-12 8:17 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 17/33] arm_mpam: Merge supported features during mpam_enable() into mpam_class Ben Horgan
2025-11-09 21:59 ` Gavin Shan
2025-11-12 8:24 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 18/33] arm_mpam: Reset MSC controls from cpuhp callbacks Ben Horgan
2025-11-09 22:11 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 19/33] arm_mpam: Add a helper to touch an MSC from any CPU Ben Horgan
2025-11-09 22:13 ` Gavin Shan
2025-11-14 2:47 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 20/33] arm_mpam: Extend reset logic to allow devices to be reset any time Ben Horgan
2025-11-09 22:16 ` Gavin Shan
2025-11-13 20:24 ` Fenghua Yu
2025-11-14 2:52 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 21/33] arm_mpam: Register and enable IRQs Ben Horgan
2025-11-09 22:18 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 22/33] arm_mpam: Use a static key to indicate when mpam is enabled Ben Horgan
2025-11-09 22:20 ` Gavin Shan
2025-11-14 4:37 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 23/33] arm_mpam: Allow configuration to be applied and restored during cpu online Ben Horgan
2025-11-09 22:59 ` Gavin Shan
2025-11-13 17:14 ` Ben Horgan
2025-11-10 17:27 ` Jonathan Cameron
2025-11-11 17:45 ` Ben Horgan
2025-11-14 10:33 ` Ben Horgan
2025-11-14 14:34 ` Ben Horgan
2025-11-07 12:34 ` [PATCH 24/33] arm_mpam: Probe and reset the rest of the features Ben Horgan
2025-11-09 23:01 ` Gavin Shan
2025-11-14 7:04 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 25/33] arm_mpam: Add helpers to allocate monitors Ben Horgan
2025-11-09 23:02 ` Gavin Shan
2025-11-14 7:14 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 26/33] arm_mpam: Add mpam_msmon_read() to read monitor value Ben Horgan
2025-11-09 23:13 ` Gavin Shan
2025-11-14 10:07 ` Ben Horgan
2025-11-12 5:33 ` Shaopeng Tan (Fujitsu)
2025-11-07 12:34 ` [PATCH 27/33] arm_mpam: Track bandwidth counter state for power management Ben Horgan
2025-11-09 23:15 ` Gavin Shan
2025-11-10 13:49 ` Zeng Heng
2025-11-10 17:31 ` Jonathan Cameron
2025-11-07 12:34 ` [PATCH 28/33] arm_mpam: Consider overflow in bandwidth counter state Ben Horgan
2025-11-09 23:16 ` Gavin Shan
2025-11-10 13:50 ` Zeng Heng
2025-11-10 17:32 ` Jonathan Cameron
2025-11-07 12:34 ` [PATCH 29/33] arm_mpam: Probe for long/lwd mbwu counters Ben Horgan
2025-11-09 23:16 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 30/33] arm_mpam: Use long MBWU counters if supported Ben Horgan
2025-11-09 23:17 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 31/33] arm_mpam: Add helper to reset saved mbwu state Ben Horgan
2025-11-09 23:18 ` Gavin Shan
2025-11-10 17:34 ` Jonathan Cameron
2025-11-07 12:34 ` [PATCH 32/33] arm_mpam: Add kunit test for bitmap reset Ben Horgan
2025-11-09 23:19 ` Gavin Shan
2025-11-07 12:34 ` [PATCH 33/33] arm_mpam: Add kunit tests for props_mismatch() Ben Horgan
2025-11-09 23:19 ` Gavin Shan
2025-11-07 12:47 ` [PATCH 00/33] arm_mpam: Add basic mpam driver Ben Horgan
2025-11-07 21:22 ` Fenghua Yu
2025-11-07 23:22 ` Carl Worth
2025-11-10 16:15 ` Ben Horgan
2025-11-11 0:45 ` Carl Worth
2025-11-10 1:05 ` Gavin Shan
2025-11-10 13:56 ` Zeng Heng
2025-11-10 16:03 ` Ben Horgan
2025-11-11 7:09 ` Shaopeng Tan (Fujitsu)
2025-11-16 17:16 ` Drew Fustini
2025-11-18 14:11 ` Ben Horgan
2025-11-18 22:55 ` Drew Fustini
2025-11-19 10:00 ` Jonathan Cameron
2025-11-19 20:09 ` Drew Fustini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7d0c73d3-1943-469f-813a-eba1dac38d4a@redhat.com \
--to=gshan@redhat.com \
--cc=amitsinght@marvell.com \
--cc=baisheng.gao@unisoc.com \
--cc=baolin.wang@linux.alibaba.com \
--cc=ben.horgan@arm.com \
--cc=bobo.shaobowang@huawei.com \
--cc=carl@os.amperecomputing.com \
--cc=catalin.marinas@arm.com \
--cc=dakr@kernel.org \
--cc=dave.martin@arm.com \
--cc=david@redhat.com \
--cc=dfustini@baylibre.com \
--cc=fenghuay@nvidia.com \
--cc=gregkh@linuxfoundation.org \
--cc=guohanjun@huawei.com \
--cc=james.morse@arm.com \
--cc=jeremy.linton@arm.com \
--cc=jonathan.cameron@huawei.com \
--cc=kobak@nvidia.com \
--cc=lcherian@marvell.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=peternewman@google.com \
--cc=quic_jiles@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=rohit.mathew@arm.com \
--cc=scott@os.amperecomputing.com \
--cc=sdonthineni@nvidia.com \
--cc=sudeep.holla@arm.com \
--cc=tan.shaopeng@fujitsu.com \
--cc=tan.shaopeng@jp.fujitsu.com \
--cc=will@kernel.org \
--cc=xhao@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®