From: James Clark <james.clark@linaro.org>
To: Chu Guangqing <chuguangqing@inspur.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
john.g.garry@oracle.com, will@kernel.org, mike.leach@linaro.org,
leo.yan@linux.dev, peterz@infradead.org, mingo@redhat.com,
acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, jolsa@kernel.org,
irogers@google.com, adrian.hunter@intel.com
Subject: Re: [PATCH] tools/perf: Fix spelling typo in tools/perf
Date: Fri, 31 Oct 2025 10:01:23 +0000 [thread overview]
Message-ID: <7fbec952-dfbc-4d6d-a6af-819ec9c81dd5@linaro.org> (raw)
In-Reply-To: <20251031025810.1939-1-chuguangqing@inspur.com>
On 31/10/2025 2:58 am, Chu Guangqing wrote:
> The json file incorrectly used "acceses" instead of "accesses".
>
> Signed-off-by: Chu Guangqing <chuguangqing@inspur.com>
Reviewed-by: James Clark <james.clark@linaro.org>
> ---
> .../arch/arm64/ampere/ampereonex/metrics.json | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> index 6817cac149e0..a29aadc9b2e3 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> @@ -388,55 +388,55 @@
> "MetricExpr": "L1D_CACHE_RW / L1D_CACHE",
> "BriefDescription": "L1D cache access - demand",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "l1d_cache_access_prefetches",
> "MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE",
> "BriefDescription": "L1D cache access - prefetch",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "l1d_cache_demand_misses",
> "MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE",
> "BriefDescription": "L1D cache demand misses",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "l1d_cache_demand_misses_read",
> "MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE",
> "BriefDescription": "L1D cache demand misses - read",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "l1d_cache_demand_misses_write",
> "MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE",
> "BriefDescription": "L1D cache demand misses - write",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "l1d_cache_prefetch_misses",
> "MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE",
> "BriefDescription": "L1D cache prefetch misses",
> "MetricGroup": "Cache",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "ase_scalar_mix",
> "MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC",
> "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations",
> "MetricGroup": "Instructions",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> },
> {
> "MetricName": "ase_vector_mix",
> "MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC",
> "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations",
> "MetricGroup": "Instructions",
> - "ScaleUnit": "100percent of cache acceses"
> + "ScaleUnit": "100percent of cache accesses"
> }
> ]
next prev parent reply other threads:[~2025-10-31 10:01 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-31 2:58 Chu Guangqing
2025-10-31 10:01 ` James Clark [this message]
2025-10-31 19:17 ` Ilkka Koskinen
2025-11-03 17:53 ` Namhyung Kim
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