* [PATCH V2 1/3] scsi: ufs-qcom: Add support for dumping HW and SW hibern8 count
2025-03-05 12:03 [PATCH V2 0/3] scsi: ufs-qcom: Enable Dumping of Hibern8, MCQ, and Testbus Registers Manish Pandey
@ 2025-03-05 12:03 ` Manish Pandey
2025-03-05 12:03 ` [PATCH V2 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers Manish Pandey
2025-03-05 12:03 ` [PATCH V2 3/3] scsi: ufs-qcom: Add support for testbus registers Manish Pandey
2 siblings, 0 replies; 6+ messages in thread
From: Manish Pandey @ 2025-03-05 12:03 UTC (permalink / raw)
To: Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, quic_nitirawa,
quic_cang, quic_nguyenb
This patch adds functionality to dump both hardware and software
hibern8 enter counts. This enhancement will aid in monitoring and
debugging hibern8 state transitions by providing detailed count
information.
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 9 +++++++++
drivers/ufs/host/ufs-qcom.h | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 1b37449fbffc..f5181773c0e5 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1573,6 +1573,15 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
host = ufshcd_get_variant(hba);
+ dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT));
+ dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT));
+
+ dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT));
+ dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT));
+
+ dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n",
+ ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT));
+
ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
"HCI Vendor Specific Registers ");
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index d0e6ec9128e7..a41db017009f 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -75,6 +75,15 @@ enum {
UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
};
+/* Vendor-specific Hibern8 count registers for the QCOM UFS host controller. */
+enum {
+ REG_UFS_HW_H8_ENTER_CNT = 0x2700,
+ REG_UFS_SW_H8_ENTER_CNT = 0x2704,
+ REG_UFS_SW_AFTER_HW_H8_ENTER_CNT = 0x2708,
+ REG_UFS_HW_H8_EXIT_CNT = 0x270C,
+ REG_UFS_SW_H8_EXIT_CNT = 0x2710,
+};
+
enum {
UFS_MEM_CQIS_VS = 0x8,
};
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH V2 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers
2025-03-05 12:03 [PATCH V2 0/3] scsi: ufs-qcom: Enable Dumping of Hibern8, MCQ, and Testbus Registers Manish Pandey
2025-03-05 12:03 ` [PATCH V2 1/3] scsi: ufs-qcom: Add support for dumping HW and SW hibern8 count Manish Pandey
@ 2025-03-05 12:03 ` Manish Pandey
2025-03-06 17:01 ` Bart Van Assche
2025-03-05 12:03 ` [PATCH V2 3/3] scsi: ufs-qcom: Add support for testbus registers Manish Pandey
2 siblings, 1 reply; 6+ messages in thread
From: Manish Pandey @ 2025-03-05 12:03 UTC (permalink / raw)
To: Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, quic_nitirawa,
quic_cang, quic_nguyenb
This patch adds functionality to dump MCQ registers.
This will help in diagnosing issues related to MCQ
operations by providing detailed register dumps.
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 59 +++++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 61 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index f5181773c0e5..7daee416eb8b 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1566,6 +1566,52 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
return 0;
}
+static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
+{
+ /* RES_MCQ_1 */
+ ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ HCI 1da0000-1da03f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_2 */
+ ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ HCI 1da0400-1da07f0 ");
+ usleep_range(1000, 1100);
+
+ /*RES_MCQ_VS */
+ ufshcd_dump_regs(hba, 0x0, 5 * 4, "MCQ VS 1da4000-1da4010 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_1 */
+ ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ SQD 1da5000-1da53f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_2 */
+ ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ SQD 1da5400-1da57f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_3 */
+ ufshcd_dump_regs(hba, 0x800, 256 * 4, "MCQ SQD 1da5800-1da5bf0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_4 */
+ ufshcd_dump_regs(hba, 0xc00, 256 * 4, "MCQ SQD 1da5c00-1da5ff0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_5 */
+ ufshcd_dump_regs(hba, 0x1000, 256 * 4, "MCQ SQD 1da6000-1da63f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_6 */
+ ufshcd_dump_regs(hba, 0x1400, 256 * 4, "MCQ SQD 1da6400-1da67f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_7 */
+ ufshcd_dump_regs(hba, 0x1800, 256 * 4, "MCQ SQD 1da6800-1da6bf0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_8 */
+ ufshcd_dump_regs(hba, 0x1c00, 256 * 4, "MCQ SQD 1da6c00-1da6ff0 ");
+}
+
static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
{
u32 reg;
@@ -1624,6 +1670,19 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
+
+ if (hba->mcq_enabled) {
+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ);
+ ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers ");
+ }
+
+ if (in_task()) {
+ /* Dump MCQ Host Vendor Specific Registers */
+ if (hba->mcq_enabled) {
+ ufs_qcom_dump_mcq_hci_regs(hba);
+ usleep_range(1000, 1100);
+ }
+ }
}
/**
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index a41db017009f..03a3fee56041 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -50,6 +50,8 @@ enum {
*/
UFS_AH8_CFG = 0xFC,
+ UFS_RD_REG_MCQ = 0xD00,
+
REG_UFS_MEM_ICE_CONFIG = 0x260C,
REG_UFS_MEM_ICE_NUM_CORE = 0x2664,
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH V2 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers
2025-03-05 12:03 ` [PATCH V2 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers Manish Pandey
@ 2025-03-06 17:01 ` Bart Van Assche
0 siblings, 0 replies; 6+ messages in thread
From: Bart Van Assche @ 2025-03-06 17:01 UTC (permalink / raw)
To: Manish Pandey, Manivannan Sadhasivam, James E.J. Bottomley,
Martin K. Petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, quic_nitirawa,
quic_cang, quic_nguyenb
On 3/5/25 4:03 AM, Manish Pandey wrote:
> +static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
> +{
> + /* RES_MCQ_1 */
> + ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ HCI 1da0000-1da03f0 ");
> + usleep_range(1000, 1100);
Please add a comment that explains why the usleep_range() calls are
present.
> @@ -1624,6 +1670,19 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
>
> reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
> ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
> +
> + if (hba->mcq_enabled) {
> + reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ);
> + ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers ");
> + }
> +
> + if (in_task()) {
> + /* Dump MCQ Host Vendor Specific Registers */
> + if (hba->mcq_enabled) {
> + ufs_qcom_dump_mcq_hci_regs(hba);
> + usleep_range(1000, 1100);
> + }
> + }
> }
Please either combine the two "if (hba->mcq_enabled)" tests or combine
the "in_task()" and "hba->mcq_enabled" tests.
Please also add a comment that explains why the in_task() call is
present and a comment that explains why the usleep_range() call is
present.
Thanks,
Bart.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V2 3/3] scsi: ufs-qcom: Add support for testbus registers
2025-03-05 12:03 [PATCH V2 0/3] scsi: ufs-qcom: Enable Dumping of Hibern8, MCQ, and Testbus Registers Manish Pandey
2025-03-05 12:03 ` [PATCH V2 1/3] scsi: ufs-qcom: Add support for dumping HW and SW hibern8 count Manish Pandey
2025-03-05 12:03 ` [PATCH V2 2/3] scsi: ufs-qcom: Add support for dumping MCQ registers Manish Pandey
@ 2025-03-05 12:03 ` Manish Pandey
2025-03-06 17:05 ` Bart Van Assche
2 siblings, 1 reply; 6+ messages in thread
From: Manish Pandey @ 2025-03-05 12:03 UTC (permalink / raw)
To: Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, quic_nitirawa,
quic_cang, quic_nguyenb
This patch introduces support for dumping testbus registers,
enhancing the debugging capabilities for UFS-QCOM drivers.
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 73 +++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 7daee416eb8b..c8f95519b580 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1566,6 +1566,75 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
return 0;
}
+static void ufs_qcom_dump_testbus(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ u32 *testbus = NULL;
+ int i, j, nminor = 0, testbus_len = 0;
+ char *prefix;
+
+ testbus = kmalloc(256 * sizeof(u32), GFP_KERNEL);
+ if (!testbus)
+ return;
+
+ for (j = 0; j < TSTBUS_MAX; j++) {
+ nminor = 32;
+
+ switch (j) {
+ case TSTBUS_UAWM:
+ prefix = "TSTBUS_UAWM ";
+ break;
+ case TSTBUS_UARM:
+ prefix = "TSTBUS_UARM ";
+ break;
+ case TSTBUS_TXUC:
+ prefix = "TSTBUS_TXUC ";
+ break;
+ case TSTBUS_RXUC:
+ prefix = "TSTBUS_RXUC ";
+ break;
+ case TSTBUS_DFC:
+ prefix = "TSTBUS_DFC ";
+ break;
+ case TSTBUS_TRLUT:
+ prefix = "TSTBUS_TRLUT ";
+ break;
+ case TSTBUS_TMRLUT:
+ prefix = "TSTBUS_TMRLUT ";
+ break;
+ case TSTBUS_OCSC:
+ prefix = "TSTBUS_OCSC ";
+ break;
+ case TSTBUS_UTP_HCI:
+ prefix = "TSTBUS_UTP_HCI ";
+ break;
+ case TSTBUS_COMBINED:
+ prefix = "TSTBUS_COMBINED ";
+ break;
+ case TSTBUS_WRAPPER:
+ prefix = "TSTBUS_WRAPPER ";
+ break;
+ case TSTBUS_UNIPRO:
+ nminor = 256;
+ prefix = "TSTBUS_UNIPRO ";
+ break;
+ default:
+ break;
+ }
+
+ host->testbus.select_major = j;
+ testbus_len = nminor * sizeof(u32);
+ for (i = 0; i < nminor; i++) {
+ host->testbus.select_minor = i;
+ ufs_qcom_testbus_config(host);
+ testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
+ }
+ print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
+ 16, 4, testbus, testbus_len, false);
+ }
+ kfree(testbus);
+}
+
static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
{
/* RES_MCQ_1 */
@@ -1682,6 +1751,10 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
ufs_qcom_dump_mcq_hci_regs(hba);
usleep_range(1000, 1100);
}
+ ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
+ usleep_range(1000, 1100);
+ ufs_qcom_dump_testbus(hba);
+ usleep_range(1000, 1100);
}
}
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH V2 3/3] scsi: ufs-qcom: Add support for testbus registers
2025-03-05 12:03 ` [PATCH V2 3/3] scsi: ufs-qcom: Add support for testbus registers Manish Pandey
@ 2025-03-06 17:05 ` Bart Van Assche
0 siblings, 0 replies; 6+ messages in thread
From: Bart Van Assche @ 2025-03-06 17:05 UTC (permalink / raw)
To: Manish Pandey, Manivannan Sadhasivam, James E.J. Bottomley,
Martin K. Petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, quic_nitirawa,
quic_cang, quic_nguyenb
On 3/5/25 4:03 AM, Manish Pandey wrote:
> This patch introduces support for dumping testbus registers,
> enhancing the debugging capabilities for UFS-QCOM drivers.
>
> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 73 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 7daee416eb8b..c8f95519b580 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -1566,6 +1566,75 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
> return 0;
> }
>
> +static void ufs_qcom_dump_testbus(struct ufs_hba *hba)
> +{
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + u32 *testbus = NULL;
> + int i, j, nminor = 0, testbus_len = 0;
> + char *prefix;
Shouldn't the declarations be ordered from longest to shortest for new
code?
Has it been considered to annotate the 'testbus' declaration with __free
and to remove the kfree(testbus) call? See also <linux/cleanup.h>
> + switch (j) {
> + case TSTBUS_UAWM:
> + prefix = "TSTBUS_UAWM ";
> + break;
> + case TSTBUS_UARM:
> + prefix = "TSTBUS_UARM ";
> + break;
> + case TSTBUS_TXUC:
> + prefix = "TSTBUS_TXUC ";
> + break;
> + case TSTBUS_RXUC:
> + prefix = "TSTBUS_RXUC ";
> + break;
> + case TSTBUS_DFC:
> + prefix = "TSTBUS_DFC ";
> + break;
> + case TSTBUS_TRLUT:
> + prefix = "TSTBUS_TRLUT ";
> + break;
> + case TSTBUS_TMRLUT:
> + prefix = "TSTBUS_TMRLUT ";
> + break;
> + case TSTBUS_OCSC:
> + prefix = "TSTBUS_OCSC ";
> + break;
> + case TSTBUS_UTP_HCI:
> + prefix = "TSTBUS_UTP_HCI ";
> + break;
> + case TSTBUS_COMBINED:
> + prefix = "TSTBUS_COMBINED ";
> + break;
> + case TSTBUS_WRAPPER:
> + prefix = "TSTBUS_WRAPPER ";
> + break;
> + case TSTBUS_UNIPRO:
> + nminor = 256;
> + prefix = "TSTBUS_UNIPRO ";
> + break;
> + default:
> + break;
> + }
Has it been considered to convert the above switch-statement into an
array lookup?
> @@ -1682,6 +1751,10 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
> ufs_qcom_dump_mcq_hci_regs(hba);
> usleep_range(1000, 1100);
> }
> + ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
> + usleep_range(1000, 1100);
> + ufs_qcom_dump_testbus(hba);
> + usleep_range(1000, 1100);
> }
> }
Please add a comment that explains why the usleep_range() calls are
present.
Thanks,
Bart.
^ permalink raw reply [flat|nested] 6+ messages in thread