[PATCH v2 0/2] PCI: mediatek-gen3: Support limiting link speed and width

[PATCH v2 0/2] PCI: mediatek-gen3: Support limiting link speed and width

[AngeloGioacchino Del Regno]

Changes in v2:
 - Rebased on next-20240917

This series adds support for limiting the PCI-Express link speed
(or PCIe gen restriction) and link width (number of lanes) in the
pcie-mediatek-gen3 driver.

The maximum supported pcie gen is read from the controller itself,
so defining a max gen through platform data for each SoC is avoided.

Both are done by adding support for the standard devicetree properties
`max-link-speed` and `num-lanes`.

Please note that changing the bindings is not required, as those do
already allow specifying those properties for this controller.



AngeloGioacchino Del Regno (2):
  PCI: mediatek-gen3: Add support for setting max-link-speed limit
  PCI: mediatek-gen3: Add support for restricting link width

 drivers/pci/controller/pcie-mediatek-gen3.c | 75 ++++++++++++++++++++-
 1 file changed, 73 insertions(+), 2 deletions(-)

-- 
2.46.0

[PATCH v2 1/2] PCI: mediatek-gen3: Add support for setting max-link-speed limit

[AngeloGioacchino Del Regno]

Add support for respecting the max-link-speed devicetree property,
forcing a maximum speed (Gen) for a PCI-Express port.

Since the MediaTek PCIe Gen3 controllers also expose the maximum
supported link speed in the PCIE_BASE_CFG register, if property
max-link-speed is specified in devicetree, validate it against the
controller capabilities and proceed setting the limitations only
if the wanted Gen is lower than the maximum one that is supported
by the controller itself (otherwise it makes no sense!).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 55 ++++++++++++++++++++-
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 66ce4b5d309b..e1d1fb39d5c6 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -28,7 +28,11 @@
 
 #include "../pci.h"
 
+#define PCIE_BASE_CFG_REG		0x14
+#define PCIE_BASE_CFG_SPEED_MASK	GENMASK(15, 8)
+
 #define PCIE_SETTING_REG		0x80
+#define PCIE_SETTING_GEN_SUPPORT_MASK	GENMASK(14, 12)
 #define PCIE_PCI_IDS_1			0x9c
 #define PCI_CLASS(class)		(class << 8)
 #define PCIE_RC_MODE			BIT(0)
@@ -125,6 +129,9 @@
 
 struct mtk_gen3_pcie;
 
+#define PCIE_CONF_LINK2_CTL_STS		0x10b0
+#define PCIE_CONF_LINK2_LCR2_LINK_SPEED	GENMASK(3, 0)
+
 /**
  * struct mtk_gen3_pcie_pdata - differentiate between host generations
  * @power_up: pcie power_up callback
@@ -160,6 +167,7 @@ struct mtk_msi_set {
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
+ * @max_link_speed: Maximum link speed (PCIe Gen) for this port
  * @irq: PCIe controller interrupt number
  * @saved_irq_state: IRQ enable state saved at suspend time
  * @irq_lock: lock protecting IRQ register access
@@ -180,6 +188,7 @@ struct mtk_gen3_pcie {
 	struct phy *phy;
 	struct clk_bulk_data *clks;
 	int num_clks;
+	u8 max_link_speed;
 
 	int irq;
 	u32 saved_irq_state;
@@ -381,11 +390,27 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 	int err;
 	u32 val;
 
-	/* Set as RC mode */
+	/* Set as RC mode and set controller PCIe Gen speed restriction, if any*/
 	val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
 	val |= PCIE_RC_MODE;
+	if (pcie->max_link_speed) {
+		val &= ~PCIE_SETTING_GEN_SUPPORT_MASK;
+
+		/* Can enable link speed support only from Gen2 onwards */
+		if (pcie->max_link_speed >= 2)
+			val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK,
+					  GENMASK(pcie->max_link_speed - 2, 0));
+	}
 	writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
 
+	/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
+	if (pcie->max_link_speed) {
+		val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
+		val &= PCIE_CONF_LINK2_LCR2_LINK_SPEED;
+		val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
+		writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
+	}
+
 	/* Set class code */
 	val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
 	val &= ~GENMASK(31, 8);
@@ -1004,9 +1029,21 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 }
 
+static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
+{
+	u32 val;
+	int ret;
+
+	val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
+	val = FIELD_GET(PCIE_BASE_CFG_SPEED_MASK, val);
+	ret = fls(val);
+
+	return ret > 0 ? ret : -EINVAL;
+}
+
 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 {
-	int err;
+	int max_speed, err;
 
 	err = mtk_pcie_parse_port(pcie);
 	if (err)
@@ -1031,6 +1068,20 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	if (err)
 		return err;
 
+	err = of_pci_get_max_link_speed(pcie->dev->of_node);
+	if (err > 0) {
+		/* Get the maximum speed supported by the controller */
+		max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
+
+		/* Set max_link_speed only if the controller supports it */
+		if (max_speed >= 0 && max_speed <= err) {
+			pcie->max_link_speed = err;
+			dev_dbg(pcie->dev,
+				"Max controller link speed Gen%u, override to Gen%u",
+				max_speed, pcie->max_link_speed);
+		}
+	}
+
 	/* Try link up */
 	err = mtk_pcie_startup_port(pcie);
 	if (err)
-- 
2.46.0

[PATCH v2 2/2] PCI: mediatek-gen3: Add support for restricting link width

[AngeloGioacchino Del Regno]

Add support for restricting the port's link width by specifying
the num-lanes devicetree property in the PCIe node.

The setting is done in the GEN_SETTINGS register (in the driver
named as PCIE_SETTING_REG), where each set bit in [11:8] activates
a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 22 ++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index e1d1fb39d5c6..e2c9802a230c 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -32,6 +32,7 @@
 #define PCIE_BASE_CFG_SPEED_MASK	GENMASK(15, 8)
 
 #define PCIE_SETTING_REG		0x80
+#define PCIE_SETTING_LINK_WIDTH		GENMASK(11, 8)
 #define PCIE_SETTING_GEN_SUPPORT_MASK	GENMASK(14, 12)
 #define PCIE_PCI_IDS_1			0x9c
 #define PCI_CLASS(class)		(class << 8)
@@ -168,6 +169,7 @@ struct mtk_msi_set {
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
  * @max_link_speed: Maximum link speed (PCIe Gen) for this port
+ * @num_lanes: Number of PCIe lanes for this port
  * @irq: PCIe controller interrupt number
  * @saved_irq_state: IRQ enable state saved at suspend time
  * @irq_lock: lock protecting IRQ register access
@@ -189,6 +191,7 @@ struct mtk_gen3_pcie {
 	struct clk_bulk_data *clks;
 	int num_clks;
 	u8 max_link_speed;
+	u8 num_lanes;
 
 	int irq;
 	u32 saved_irq_state;
@@ -390,7 +393,7 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 	int err;
 	u32 val;
 
-	/* Set as RC mode and set controller PCIe Gen speed restriction, if any*/
+	/* Set as RC mode and set controller PCIe Gen speed/lanes restriction, if any */
 	val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
 	val |= PCIE_RC_MODE;
 	if (pcie->max_link_speed) {
@@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
 			val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK,
 					  GENMASK(pcie->max_link_speed - 2, 0));
 	}
+	if (pcie->num_lanes) {
+		val &= ~PCIE_SETTING_LINK_WIDTH;
+
+		/* Zero means one lane, each bit activates x2/x4/x8/x16 */
+		if (pcie->num_lanes > 1)
+			val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
+					  GENMASK(pcie->num_lanes >> 1, 0));
+	};
 	writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
 
 	/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
@@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource *regs;
+	u32 num_lanes;
 
 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
 	if (!regs)
@@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 		return pcie->num_clks;
 	}
 
+	ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);
+	if (ret == 0) {
+		if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))
+			dev_warn(dev, "Invalid num-lanes, using controller defaults\n");
+		else
+			pcie->num_lanes = num_lanes;
+	}
+
 	return 0;
 }
 
-- 
2.46.0

Re: [PATCH v2 1/2] PCI: mediatek-gen3: Add support for setting max-link-speed limit

[Fei Shao]

On Tue, Sep 17, 2024 at 5:13 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Add support for respecting the max-link-speed devicetree property,
> forcing a maximum speed (Gen) for a PCI-Express port.
>
> Since the MediaTek PCIe Gen3 controllers also expose the maximum
> supported link speed in the PCIE_BASE_CFG register, if property
> max-link-speed is specified in devicetree, validate it against the
> controller capabilities and proceed setting the limitations only
> if the wanted Gen is lower than the maximum one that is supported
> by the controller itself (otherwise it makes no sense!).
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/pci/controller/pcie-mediatek-gen3.c | 55 ++++++++++++++++++++-
>  1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 66ce4b5d309b..e1d1fb39d5c6 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -28,7 +28,11 @@
>
>  #include "../pci.h"
>
> +#define PCIE_BASE_CFG_REG              0x14
> +#define PCIE_BASE_CFG_SPEED_MASK       GENMASK(15, 8)
> +
>  #define PCIE_SETTING_REG               0x80
> +#define PCIE_SETTING_GEN_SUPPORT_MASK  GENMASK(14, 12)
>  #define PCIE_PCI_IDS_1                 0x9c
>  #define PCI_CLASS(class)               (class << 8)
>  #define PCIE_RC_MODE                   BIT(0)
> @@ -125,6 +129,9 @@
>
>  struct mtk_gen3_pcie;
>
> +#define PCIE_CONF_LINK2_CTL_STS                0x10b0
> +#define PCIE_CONF_LINK2_LCR2_LINK_SPEED        GENMASK(3, 0)
> +
>  /**
>   * struct mtk_gen3_pcie_pdata - differentiate between host generations
>   * @power_up: pcie power_up callback
> @@ -160,6 +167,7 @@ struct mtk_msi_set {
>   * @phy: PHY controller block
>   * @clks: PCIe clocks
>   * @num_clks: PCIe clocks count for this port
> + * @max_link_speed: Maximum link speed (PCIe Gen) for this port
>   * @irq: PCIe controller interrupt number
>   * @saved_irq_state: IRQ enable state saved at suspend time
>   * @irq_lock: lock protecting IRQ register access
> @@ -180,6 +188,7 @@ struct mtk_gen3_pcie {
>         struct phy *phy;
>         struct clk_bulk_data *clks;
>         int num_clks;
> +       u8 max_link_speed;
>
>         int irq;
>         u32 saved_irq_state;
> @@ -381,11 +390,27 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
>         int err;
>         u32 val;
>
> -       /* Set as RC mode */
> +       /* Set as RC mode and set controller PCIe Gen speed restriction, if any*/

NIt: one space before ending the comment.

>         val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
>         val |= PCIE_RC_MODE;
> +       if (pcie->max_link_speed) {
> +               val &= ~PCIE_SETTING_GEN_SUPPORT_MASK;
> +
> +               /* Can enable link speed support only from Gen2 onwards */
> +               if (pcie->max_link_speed >= 2)
> +                       val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK,
> +                                         GENMASK(pcie->max_link_speed - 2, 0));
> +       }
>         writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
>
> +       /* Set Link Control 2 (LNKCTL2) speed restriction, if any */
> +       if (pcie->max_link_speed) {
> +               val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
> +               val &= PCIE_CONF_LINK2_LCR2_LINK_SPEED;

I guess it needs a bitwise NOT operator over the mask.
    val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;

Apart from that, I think appending _MASK to the name makes its usage
clearer and consistent with other masks.
(although the name gets even more lengthy...)

> +               val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
> +               writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
> +       }
> +
>         /* Set class code */
>         val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
>         val &= ~GENMASK(31, 8);
> @@ -1004,9 +1029,21 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
>         reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
>  }
>
> +static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
> +{
> +       u32 val;
> +       int ret;
> +
> +       val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
> +       val = FIELD_GET(PCIE_BASE_CFG_SPEED_MASK, val);
> +       ret = fls(val);
> +
> +       return ret > 0 ? ret : -EINVAL;
> +}
> +
>  static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>  {
> -       int err;
> +       int max_speed, err;
>
>         err = mtk_pcie_parse_port(pcie);
>         if (err)
> @@ -1031,6 +1068,20 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>         if (err)
>                 return err;
>
> +       err = of_pci_get_max_link_speed(pcie->dev->of_node);
> +       if (err > 0) {
> +               /* Get the maximum speed supported by the controller */
> +               max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
> +
> +               /* Set max_link_speed only if the controller supports it */
> +               if (max_speed >= 0 && max_speed <= err) {
> +                       pcie->max_link_speed = err;
> +                       dev_dbg(pcie->dev,
> +                               "Max controller link speed Gen%u, override to Gen%u",
> +                               max_speed, pcie->max_link_speed);

Convert max_speed to an unsigned type to avoid potential typecheck warnings?

Regards,
Fei


> +               }
> +       }
> +
>         /* Try link up */
>         err = mtk_pcie_startup_port(pcie);
>         if (err)
> --
> 2.46.0
>
>

Re: [PATCH v2 1/2] PCI: mediatek-gen3: Add support for setting max-link-speed limit

[AngeloGioacchino Del Regno]

Il 17/09/24 18:15, Fei Shao ha scritto:
> On Tue, Sep 17, 2024 at 5:13 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Add support for respecting the max-link-speed devicetree property,
>> forcing a maximum speed (Gen) for a PCI-Express port.
>>
>> Since the MediaTek PCIe Gen3 controllers also expose the maximum
>> supported link speed in the PCIE_BASE_CFG register, if property
>> max-link-speed is specified in devicetree, validate it against the
>> controller capabilities and proceed setting the limitations only
>> if the wanted Gen is lower than the maximum one that is supported
>> by the controller itself (otherwise it makes no sense!).
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/pci/controller/pcie-mediatek-gen3.c | 55 ++++++++++++++++++++-
>>   1 file changed, 53 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
>> index 66ce4b5d309b..e1d1fb39d5c6 100644
>> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
>> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
>> @@ -28,7 +28,11 @@
>>
>>   #include "../pci.h"
>>
>> +#define PCIE_BASE_CFG_REG              0x14
>> +#define PCIE_BASE_CFG_SPEED_MASK       GENMASK(15, 8)
>> +
>>   #define PCIE_SETTING_REG               0x80
>> +#define PCIE_SETTING_GEN_SUPPORT_MASK  GENMASK(14, 12)
>>   #define PCIE_PCI_IDS_1                 0x9c
>>   #define PCI_CLASS(class)               (class << 8)
>>   #define PCIE_RC_MODE                   BIT(0)
>> @@ -125,6 +129,9 @@
>>
>>   struct mtk_gen3_pcie;
>>
>> +#define PCIE_CONF_LINK2_CTL_STS                0x10b0
>> +#define PCIE_CONF_LINK2_LCR2_LINK_SPEED        GENMASK(3, 0)
>> +
>>   /**
>>    * struct mtk_gen3_pcie_pdata - differentiate between host generations
>>    * @power_up: pcie power_up callback
>> @@ -160,6 +167,7 @@ struct mtk_msi_set {
>>    * @phy: PHY controller block
>>    * @clks: PCIe clocks
>>    * @num_clks: PCIe clocks count for this port
>> + * @max_link_speed: Maximum link speed (PCIe Gen) for this port
>>    * @irq: PCIe controller interrupt number
>>    * @saved_irq_state: IRQ enable state saved at suspend time
>>    * @irq_lock: lock protecting IRQ register access
>> @@ -180,6 +188,7 @@ struct mtk_gen3_pcie {
>>          struct phy *phy;
>>          struct clk_bulk_data *clks;
>>          int num_clks;
>> +       u8 max_link_speed;
>>
>>          int irq;
>>          u32 saved_irq_state;
>> @@ -381,11 +390,27 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
>>          int err;
>>          u32 val;
>>
>> -       /* Set as RC mode */
>> +       /* Set as RC mode and set controller PCIe Gen speed restriction, if any*/
> 
> NIt: one space before ending the comment.
> 

Yep. :-)

>>          val = readl_relaxed(pcie->base + PCIE_SETTING_REG);
>>          val |= PCIE_RC_MODE;
>> +       if (pcie->max_link_speed) {
>> +               val &= ~PCIE_SETTING_GEN_SUPPORT_MASK;
>> +
>> +               /* Can enable link speed support only from Gen2 onwards */
>> +               if (pcie->max_link_speed >= 2)
>> +                       val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK,
>> +                                         GENMASK(pcie->max_link_speed - 2, 0));
>> +       }
>>          writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
>>
>> +       /* Set Link Control 2 (LNKCTL2) speed restriction, if any */
>> +       if (pcie->max_link_speed) {
>> +               val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
>> +               val &= PCIE_CONF_LINK2_LCR2_LINK_SPEED;
> 
> I guess it needs a bitwise NOT operator over the mask.
>      val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
> 

I have no idea how the NOT disappeared from this line :o
Nice catch.

> Apart from that, I think appending _MASK to the name makes its usage
> clearer and consistent with other masks.
> (although the name gets even more lengthy...)

Actually, the only other ones that say _MASK are the ones that I am introducing
in this commit, other than PCIE_LTSSM_STATE_MASK... all of the others do *not*
have the _MASK suffix.

At this point, for consistency, I should rather drop the _MASK suffix from the
PCIE_BASE_CFG_SPEED and PCIE_SETTING_GEN_SUPPORT definitions that I introduce
here, so I'll do exactly that for v3.

> 
>> +               val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
>> +               writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
>> +       }
>> +
>>          /* Set class code */
>>          val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
>>          val &= ~GENMASK(31, 8);
>> @@ -1004,9 +1029,21 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
>>          reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
>>   }
>>
>> +static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)
>> +{
>> +       u32 val;
>> +       int ret;
>> +
>> +       val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);
>> +       val = FIELD_GET(PCIE_BASE_CFG_SPEED_MASK, val);
>> +       ret = fls(val);
>> +
>> +       return ret > 0 ? ret : -EINVAL;
>> +}
>> +
>>   static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>>   {
>> -       int err;
>> +       int max_speed, err;

Self-review: reorder this, e comes before m. Oops!

>>
>>          err = mtk_pcie_parse_port(pcie);
>>          if (err)
>> @@ -1031,6 +1068,20 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>>          if (err)
>>                  return err;
>>
>> +       err = of_pci_get_max_link_speed(pcie->dev->of_node);
>> +       if (err > 0) {
>> +               /* Get the maximum speed supported by the controller */
>> +               max_speed = mtk_pcie_get_controller_max_link_speed(pcie);
>> +
>> +               /* Set max_link_speed only if the controller supports it */
>> +               if (max_speed >= 0 && max_speed <= err) {
>> +                       pcie->max_link_speed = err;
>> +                       dev_dbg(pcie->dev,
>> +                               "Max controller link speed Gen%u, override to Gen%u",
>> +                               max_speed, pcie->max_link_speed);
> 
> Convert max_speed to an unsigned type to avoid potential typecheck warnings?
> 

I'll just change that to "[...] Gen%d, override to Gen%u", looks simply
cleaner, in the end...

Thanks!
Angelo

> Regards,
> Fei
> 
> 
>> +               }
>> +       }
>> +
>>          /* Try link up */
>>          err = mtk_pcie_startup_port(pcie);
>>          if (err)
>> --
>> 2.46.0
>>
>>