* [PATCH 1/4] clk: versaclock3: Remove unused SE2 clock select macro
2025-10-21 17:53 [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
@ 2025-10-21 17:53 ` Ovidiu Panait
2025-10-21 17:53 ` [PATCH 2/4] clk: versaclock3: Use clk_parent_data arrays for clk_mux Ovidiu Panait
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Ovidiu Panait @ 2025-10-21 17:53 UTC (permalink / raw)
To: biju.das.jz, geert+renesas, magnus.damm, robh, krzk+dt, conor+dt,
mturquette, sboyd
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk
The VC3_SE2_CTRL_REG0_SE2_CLK_SEL macro is no longer used since
commit ae6040cd7c7f8 ("clk: versaclock3: Prepare for the addition of
5L35023 device"), which switched SE2 clock select handling to use
variant-specific OF data (se2_clk_sel_msk).
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/clk/clk-versaclock3.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index 1849863dbd67..f387cdb12f48 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -61,7 +61,6 @@
#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
#define VC3_SE2_CTRL_REG0 0x1f
-#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
#define VC3_SE3_DIFF1_CTRL_REG 0x21
#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/4] clk: versaclock3: Use clk_parent_data arrays for clk_mux
2025-10-21 17:53 [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
2025-10-21 17:53 ` [PATCH 1/4] clk: versaclock3: Remove unused SE2 clock select macro Ovidiu Panait
@ 2025-10-21 17:53 ` Ovidiu Panait
2025-10-21 17:53 ` [PATCH 3/4] clk: versaclock3: Add freerunning 32.768kHz clock support Ovidiu Panait
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Ovidiu Panait @ 2025-10-21 17:53 UTC (permalink / raw)
To: biju.das.jz, geert+renesas, magnus.damm, robh, krzk+dt, conor+dt,
mturquette, sboyd
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk
Replace the inline parent_hws initializers with static clk_parent_data
arrays for the clk muxes. This provides more flexibility in how
parents are described and will simplify extending the parent lists in
the next commit.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/clk/clk-versaclock3.c | 48 ++++++++++++++++++++---------------
1 file changed, 28 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index f387cdb12f48..ebd9d75d7f55 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -900,6 +900,29 @@ static struct vc3_hw_data clk_div[] = {
}
};
+static const struct clk_parent_data clk_mux_parent_data[][2] = {
+ [VC3_SE1_MUX] = {
+ { .hw = &clk_div[VC3_DIV5].hw },
+ { .hw = &clk_div[VC3_DIV4].hw }
+ },
+ [VC3_SE2_MUX] = {
+ { .hw = &clk_div[VC3_DIV5].hw },
+ { .hw = &clk_div[VC3_DIV4].hw }
+ },
+ [VC3_SE3_MUX] = {
+ { .hw = &clk_div[VC3_DIV2].hw },
+ { .hw = &clk_div[VC3_DIV4].hw }
+ },
+ [VC3_DIFF1_MUX] = {
+ { .hw = &clk_div[VC3_DIV1].hw },
+ { .hw = &clk_div[VC3_DIV3].hw }
+ },
+ [VC3_DIFF2_MUX] = {
+ { .hw = &clk_div[VC3_DIV1].hw },
+ { .hw = &clk_div[VC3_DIV3].hw }
+ },
+};
+
static struct vc3_hw_data clk_mux[] = {
[VC3_SE1_MUX] = {
.data = &(struct vc3_clk_data) {
@@ -909,10 +932,7 @@ static struct vc3_hw_data clk_mux[] = {
.hw.init = &(struct clk_init_data) {
.name = "se1_mux",
.ops = &vc3_clk_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &clk_div[VC3_DIV5].hw,
- &clk_div[VC3_DIV4].hw
- },
+ .parent_data = clk_mux_parent_data[VC3_SE1_MUX],
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
@@ -924,10 +944,7 @@ static struct vc3_hw_data clk_mux[] = {
.hw.init = &(struct clk_init_data) {
.name = "se2_mux",
.ops = &vc3_clk_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &clk_div[VC3_DIV5].hw,
- &clk_div[VC3_DIV4].hw
- },
+ .parent_data = clk_mux_parent_data[VC3_SE2_MUX],
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
@@ -940,10 +957,7 @@ static struct vc3_hw_data clk_mux[] = {
.hw.init = &(struct clk_init_data) {
.name = "se3_mux",
.ops = &vc3_clk_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &clk_div[VC3_DIV2].hw,
- &clk_div[VC3_DIV4].hw
- },
+ .parent_data = clk_mux_parent_data[VC3_SE3_MUX],
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
@@ -956,10 +970,7 @@ static struct vc3_hw_data clk_mux[] = {
.hw.init = &(struct clk_init_data) {
.name = "diff1_mux",
.ops = &vc3_clk_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &clk_div[VC3_DIV1].hw,
- &clk_div[VC3_DIV3].hw
- },
+ .parent_data = clk_mux_parent_data[VC3_DIFF1_MUX],
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
@@ -972,10 +983,7 @@ static struct vc3_hw_data clk_mux[] = {
.hw.init = &(struct clk_init_data) {
.name = "diff2_mux",
.ops = &vc3_clk_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &clk_div[VC3_DIV1].hw,
- &clk_div[VC3_DIV3].hw
- },
+ .parent_data = clk_mux_parent_data[VC3_DIFF2_MUX],
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT
}
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 3/4] clk: versaclock3: Add freerunning 32.768kHz clock support
2025-10-21 17:53 [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
2025-10-21 17:53 ` [PATCH 1/4] clk: versaclock3: Remove unused SE2 clock select macro Ovidiu Panait
2025-10-21 17:53 ` [PATCH 2/4] clk: versaclock3: Use clk_parent_data arrays for clk_mux Ovidiu Panait
@ 2025-10-21 17:53 ` Ovidiu Panait
2025-10-21 17:53 ` [PATCH 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node Ovidiu Panait
2025-12-02 13:07 ` [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
4 siblings, 0 replies; 6+ messages in thread
From: Ovidiu Panait @ 2025-10-21 17:53 UTC (permalink / raw)
To: biju.das.jz, geert+renesas, magnus.damm, robh, krzk+dt, conor+dt,
mturquette, sboyd
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk
The Versa 3 clock generator has an internal 32.768kHz oscillator that can
be routed to the SE1, SE2 and SE3 outputs. This patch exposes it as a
fixed-rate clock ("vc3-clk-32k") and makes it available as a parent for
the SE1/SE2/SE3 muxes.
The 32.768kHz clock is only intended to be used when explicitly requested
(i.e. when a rate of exactly 32768Hz is set). Selecting it as a fallback
for other rates can cause issues, for example in audio configurations.
To enforce this, introduce a new helper function,
_vc3_clk_mux_determine_rate() which rejects configurations where the
32.768kHz parent would otherwise be chosen implicitly.
Two new fields are added to struct vc3_clk_data:
- clk_32k_bitmsk: bit mask for selecting the 32.768kHz oscillator
- clk_32k_index: index of the 32.768kHz clock in the mux parent list
They are used by clk_mux callbacks to select the appropriate parent clock.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/clk/clk-versaclock3.c | 85 +++++++++++++++++++++++++++++------
1 file changed, 71 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index ebd9d75d7f55..b5df349f497d 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -61,8 +61,10 @@
#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
#define VC3_SE2_CTRL_REG0 0x1f
+#define VC3_SE2_CTRL_REG0_SE2_FREERUN_32K BIT(7)
#define VC3_SE3_DIFF1_CTRL_REG 0x21
+#define VC3_SE3_DIFF1_CTRL_REG_SE3_FREERUN_32K BIT(7)
#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
#define VC3_DIFF1_CTRL_REG 0x22
@@ -72,6 +74,7 @@
#define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7)
#define VC3_SE1_DIV4_CTRL 0x24
+#define VC3_SE1_DIV4_CTRL_SE1_FREERUN_32K BIT(4)
#define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3)
#define VC3_PLL1_VCO_MIN 300000000UL
@@ -83,6 +86,9 @@
#define VC3_2_POW_16 (U16_MAX + 1)
#define VC3_DIV_MASK(width) ((1 << (width)) - 1)
+#define VC3_CLK_32K_NAME "vc3-clk-32k"
+#define VC3_CLK_32K_FREQ 32768
+
enum vc3_pfd_mux {
VC3_PFD2_MUX,
VC3_PFD3_MUX,
@@ -134,6 +140,9 @@ enum vc3_clk_mux {
struct vc3_clk_data {
u8 offs;
u8 bitmsk;
+
+ u8 clk_32k_bitmsk;
+ u8 clk_32k_index;
};
struct vc3_pfd_data {
@@ -213,6 +222,7 @@ static const struct clk_div_table div3_divs[] = {
{}
};
+static struct clk_hw *clk_32k;
static struct clk_hw *clk_out[6];
static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw)
@@ -549,19 +559,40 @@ static const struct clk_ops vc3_div_ops = {
.set_rate = vc3_div_set_rate,
};
+static int _vc3_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ bool is_32k_req = (req->rate == VC3_CLK_32K_FREQ);
+ struct clk_rate_request tmp_req;
+ int ret;
+
+ clk_hw_init_rate_request(hw, &tmp_req, req->rate);
+
+ ret = clk_mux_determine_rate_flags(hw, &tmp_req, CLK_SET_RATE_PARENT);
+ if (ret)
+ return ret;
+
+ /* Select the 32.768 kHz parent only when explicitly requested. */
+ if ((tmp_req.best_parent_rate == VC3_CLK_32K_FREQ) && !is_32k_req)
+ return -EINVAL;
+
+ memcpy(req, &tmp_req, sizeof(*req));
+
+ return 0;
+}
+
static int vc3_clk_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
int frc;
- if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) {
+ if (_vc3_clk_mux_determine_rate(hw, req)) {
/* The below check is equivalent to (best_parent_rate/rate) */
if (req->best_parent_rate >= req->rate) {
frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate,
req->rate);
req->rate *= frc;
- return clk_mux_determine_rate_flags(hw, req,
- CLK_SET_RATE_PARENT);
+ return _vc3_clk_mux_determine_rate(hw, req);
}
}
@@ -576,6 +607,9 @@ static u8 vc3_clk_mux_get_parent(struct clk_hw *hw)
regmap_read(vc3->regmap, clk_mux->offs, &val);
+ if (clk_mux->clk_32k_bitmsk && !(val & clk_mux->clk_32k_bitmsk))
+ return clk_mux->clk_32k_index;
+
return !!(val & clk_mux->bitmsk);
}
@@ -583,9 +617,15 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
const struct vc3_clk_data *clk_mux = vc3->data;
+ unsigned int bitmsk = clk_mux->clk_32k_bitmsk;
+ unsigned int val = 0;
+
+ if (index != clk_mux->clk_32k_index) {
+ bitmsk |= clk_mux->bitmsk;
+ val = clk_mux->clk_32k_bitmsk | (index ? clk_mux->bitmsk : 0);
+ }
- return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk,
- index ? clk_mux->bitmsk : 0);
+ return regmap_update_bits(vc3->regmap, clk_mux->offs, bitmsk, val);
}
static const struct clk_ops vc3_clk_mux_ops = {
@@ -900,18 +940,21 @@ static struct vc3_hw_data clk_div[] = {
}
};
-static const struct clk_parent_data clk_mux_parent_data[][2] = {
+static const struct clk_parent_data clk_mux_parent_data[][3] = {
[VC3_SE1_MUX] = {
{ .hw = &clk_div[VC3_DIV5].hw },
- { .hw = &clk_div[VC3_DIV4].hw }
+ { .hw = &clk_div[VC3_DIV4].hw },
+ { .name = VC3_CLK_32K_NAME, .index = -1 }
},
[VC3_SE2_MUX] = {
{ .hw = &clk_div[VC3_DIV5].hw },
- { .hw = &clk_div[VC3_DIV4].hw }
+ { .hw = &clk_div[VC3_DIV4].hw },
+ { .name = VC3_CLK_32K_NAME, .index = -1 }
},
[VC3_SE3_MUX] = {
{ .hw = &clk_div[VC3_DIV2].hw },
- { .hw = &clk_div[VC3_DIV4].hw }
+ { .hw = &clk_div[VC3_DIV4].hw },
+ { .name = VC3_CLK_32K_NAME, .index = -1 }
},
[VC3_DIFF1_MUX] = {
{ .hw = &clk_div[VC3_DIV1].hw },
@@ -927,38 +970,44 @@ static struct vc3_hw_data clk_mux[] = {
[VC3_SE1_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE1_DIV4_CTRL,
- .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
+ .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL,
+ .clk_32k_bitmsk = VC3_SE1_DIV4_CTRL_SE1_FREERUN_32K,
+ .clk_32k_index = 2
},
.hw.init = &(struct clk_init_data) {
.name = "se1_mux",
.ops = &vc3_clk_mux_ops,
.parent_data = clk_mux_parent_data[VC3_SE1_MUX],
- .num_parents = 2,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE2_CTRL_REG0,
+ .clk_32k_bitmsk = VC3_SE2_CTRL_REG0_SE2_FREERUN_32K,
+ .clk_32k_index = 2
},
.hw.init = &(struct clk_init_data) {
.name = "se2_mux",
.ops = &vc3_clk_mux_ops,
.parent_data = clk_mux_parent_data[VC3_SE2_MUX],
- .num_parents = 2,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT
}
},
[VC3_SE3_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE3_DIFF1_CTRL_REG,
- .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
+ .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL,
+ .clk_32k_bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_FREERUN_32K,
+ .clk_32k_index = 2
},
.hw.init = &(struct clk_init_data) {
.name = "se3_mux",
.ops = &vc3_clk_mux_ops,
.parent_data = clk_mux_parent_data[VC3_SE3_MUX],
- .num_parents = 2,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT
}
},
@@ -1038,6 +1087,14 @@ static int vc3_probe(struct i2c_client *client)
return ret;
}
+ /* Register fixed 32.768kHz clock */
+ clk_32k = devm_clk_hw_register_fixed_rate(dev, VC3_CLK_32K_NAME, NULL,
+ 0, VC3_CLK_32K_FREQ);
+ if (IS_ERR(clk_32k))
+ return dev_err_probe(dev, PTR_ERR(clk_32k),
+ "Failed to register %dHz fixed clock\n",
+ VC3_CLK_32K_FREQ);
+
/* Register pfd muxes */
for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) {
clk_pfd_mux[i].regmap = regmap;
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node
2025-10-21 17:53 [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
` (2 preceding siblings ...)
2025-10-21 17:53 ` [PATCH 3/4] clk: versaclock3: Add freerunning 32.768kHz clock support Ovidiu Panait
@ 2025-10-21 17:53 ` Ovidiu Panait
2025-12-02 13:07 ` [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
4 siblings, 0 replies; 6+ messages in thread
From: Ovidiu Panait @ 2025-10-21 17:53 UTC (permalink / raw)
To: biju.das.jz, geert+renesas, magnus.damm, robh, krzk+dt, conor+dt,
mturquette, sboyd
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk
Add versa3 clock generator node. It provides clocks for the RTC, PCIe
and audio devices.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index f20b63acca00..3d2f926a3358 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -100,6 +100,12 @@ vqmmc_sdhi1: regulator-vccq-sdhi1 {
states = <3300000 0>, <1800000 1>;
};
+ x1: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
/* 32.768kHz crystal */
x6: x6-clock {
compatible = "fixed-clock";
@@ -209,6 +215,25 @@ raa215300: pmic@12 {
clocks = <&x6>;
clock-names = "xin";
};
+
+ versa3: clock-generator@69 {
+ compatible = "renesas,5l35023";
+ reg = <0x69>;
+ clocks = <&x1>;
+ #clock-cells = <1>;
+ assigned-clocks = <&versa3 0>,
+ <&versa3 1>,
+ <&versa3 2>,
+ <&versa3 3>,
+ <&versa3 4>,
+ <&versa3 5>;
+ assigned-clock-rates = <24000000>,
+ <24576000>,
+ <32768>,
+ <22579200>,
+ <100000000>,
+ <100000000>;
+ };
};
&mdio0 {
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK
2025-10-21 17:53 [PATCH 0/4] Add versaclock3 support for RZ/V2H EVK Ovidiu Panait
` (3 preceding siblings ...)
2025-10-21 17:53 ` [PATCH 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node Ovidiu Panait
@ 2025-12-02 13:07 ` Ovidiu Panait
4 siblings, 0 replies; 6+ messages in thread
From: Ovidiu Panait @ 2025-12-02 13:07 UTC (permalink / raw)
To: geert+renesas
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk,
biju.das.jz, magnus.damm, robh, krzk+dt, conor+dt, mturquette,
sboyd, Ovidiu Panait
Hi Geert,
On 10/21/25 8:53 PM, Ovidiu Panait wrote:
> Hi,
>
> This series extends the versaclock3 driver to support the internal
> freerunning 32.768 kHz clock, which is used on the RZ/V2H SoC as RTC
> counter clock. It also adds the dts node for the RZ/V2H EVK.
>
I wanted to check whether you had a chance to look at this patchset.
Please let me know if you have any comments/feedback. Thanks!
Ovidiu
> Best regards,
> Ovidiu
>
> Ovidiu Panait (4):
> clk: versaclock3: Remove unused SE2 clock select macro
> clk: versaclock3: Use clk_parent_data arrays for clk_mux
> clk: versaclock3: Add freerunning 32.768kHz clock support
> arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock
> generator node
>
> .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 25 ++++
> drivers/clk/clk-versaclock3.c | 126 +++++++++++++-----
> 2 files changed, 120 insertions(+), 31 deletions(-)
>
^ permalink raw reply [flat|nested] 6+ messages in thread