Re: [PATCH] coresight-etm4x: Conditionally access register TRCEXTINSELR

[yuanfang zhang <yuanfang.zhang@oss.qualcomm.com>]

On 8/11/2025 6:25 PM, James Clark wrote:
>
>
> On 11/08/2025 10:57 am, Yuanfang Zhang wrote:
>> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
>> To avoid invalid accesses, introduce a check on numextinsel
>> (derived from TRCIDR5[11:9]) before reading or writing to this register.
>>
>
> Looks like this should have a fixes: tag.
updated in next patch.
>
>> Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++---
>>   drivers/hwtracing/coresight/coresight-etm4x.h      |  2 ++
>>   2 files changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index 42e5d37403addc6ec81f2e3184522d67d1677c04..8a9c4caceff0165e4fce7ac4250f3e16ccc1d34e 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>>           etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
>>           etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
>>       }
>> -    etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
>> +    if (drvdata->numextinsel)
>> +        etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
>>       for (i = 0; i < drvdata->nr_cntr; i++) {
>>           etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
>>           etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
>> @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info)
>>       etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
>>       /* NUMEXTIN, bits[8:0] number of external inputs implemented */
>>       drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
>> +    drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
>>       /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
>>       drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
>>       /* ATBTRIG, bit[22] implementation can support ATB triggers? */
>> @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
>>           state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
>>           state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
>>       }
>> -    state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
>> +
>> +    if (drvdata->nrseqstate)
>
> Shouldn't this be "if (drvdata->numextinsel)"? Or it needs a comment saying why it's different to the others.
typo, will correct in next patch.
>
> Otherwise looks ok.
>
>> +        state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
>>         for (i = 0; i < drvdata->nr_cntr; i++) {
>>           state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
>> @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>>           etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
>>           etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
>>       }
>> -    etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
>> +    if (drvdata->numextinsel)
>> +        etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
>>         for (i = 0; i < drvdata->nr_cntr; i++) {
>>           etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
>> index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>> @@ -162,6 +162,7 @@
>>   #define TRCIDR4_NUMVMIDC_MASK            GENMASK(31, 28)
>>     #define TRCIDR5_NUMEXTIN_MASK            GENMASK(8, 0)
>> +#define TRCIDR5_NUMEXTINSEL_MASK               GENMASK(11, 9)
>>   #define TRCIDR5_TRACEIDSIZE_MASK        GENMASK(21, 16)
>>   #define TRCIDR5_ATBTRIG                BIT(22)
>>   #define TRCIDR5_LPOVERRIDE            BIT(23)
>> @@ -999,6 +1000,7 @@ struct etmv4_drvdata {
>>       u8                nr_cntr;
>>       u8                nr_ext_inp;
>>       u8                numcidc;
>> +    u8                numextinsel;
>>       u8                numvmidc;
>>       u8                nrseqstate;
>>       u8                nr_event;
>>
>> ---
>> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
>> change-id: 20250811-trcextinselr_issue-f267afa0e5ed
>>
>> Best regards,
>