* [PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
@ 2020-09-02 6:48 ` Elaine Zhang
2020-09-02 15:54 ` Robin Murphy
2020-09-02 6:48 ` [PATCH v1 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Elaine Zhang
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:48 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-half-divider.c | 12 +++++----
drivers/clk/rockchip/clk.c | 35 ++++++++++++++-----------
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..35db0651ea1d 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,6 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
@@ -212,12 +213,13 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
div_ops = &clk_half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- mux ? &mux->hw : NULL, mux_ops,
- div ? &div->hw : NULL, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags);
+ clk = hw->clk;
return clk;
err_div:
kfree(gate);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..2cfebfb61814 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,6 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
@@ -100,12 +101,12 @@ static struct clk *rockchip_clk_register_branch(const char *name,
: &clk_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- mux ? &mux->hw : NULL, mux_ops,
- div ? &div->hw : NULL, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags);
-
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags);
+ clk = hw->clk;
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto err_composite;
@@ -214,6 +215,7 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
struct clk *clk;
struct clk_gate *gate = NULL;
@@ -255,11 +257,12 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = &clk_fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- NULL, NULL,
- &div->hw, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags | CLK_SET_RATE_UNGATE);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ &div->hw, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags | CLK_SET_RATE_UNGATE);
+ clk = hw->clk;
if (IS_ERR(clk)) {
kfree(frac);
return clk;
@@ -320,6 +323,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, spinlock_t *lock)
{
+ struct clk_hw *hw;
struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fixed_factor *fix = NULL;
@@ -349,10 +353,11 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
fix->mult = mult;
fix->div = div;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- NULL, NULL,
- &fix->hw, &clk_fixed_factor_ops,
- &gate->hw, &clk_gate_ops, flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ &fix->hw, &clk_fixed_factor_ops,
+ &gate->hw, &clk_gate_ops, flags);
+ clk = hw->clk;
if (IS_ERR(clk)) {
kfree(fix);
kfree(gate);
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
2020-09-02 6:48 ` [PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
@ 2020-09-02 15:54 ` Robin Murphy
0 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2020-09-02 15:54 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, sboyd, mturquette, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
On 2020-09-02 07:48, Elaine Zhang wrote:
> clk_hw_register_composite it's already exported.
> Preparation for compilation of rK common clock drivers into modules.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> drivers/clk/rockchip/clk-half-divider.c | 12 +++++----
> drivers/clk/rockchip/clk.c | 35 ++++++++++++++-----------
> 2 files changed, 27 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
> index b333fc28c94b..35db0651ea1d 100644
> --- a/drivers/clk/rockchip/clk-half-divider.c
> +++ b/drivers/clk/rockchip/clk-half-divider.c
> @@ -166,6 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
> unsigned long flags,
> spinlock_t *lock)
> {
> + struct clk_hw *hw;
> struct clk *clk;
> struct clk_mux *mux = NULL;
> struct clk_gate *gate = NULL;
> @@ -212,12 +213,13 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
> div_ops = &clk_half_divider_ops;
> }
>
> - clk = clk_register_composite(NULL, name, parent_names, num_parents,
> - mux ? &mux->hw : NULL, mux_ops,
> - div ? &div->hw : NULL, div_ops,
> - gate ? &gate->hw : NULL, gate_ops,
> - flags);
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux ? &mux->hw : NULL, mux_ops,
> + div ? &div->hw : NULL, div_ops,
> + gate ? &gate->hw : NULL, gate_ops,
> + flags);
>
> + clk = hw->clk;
> return clk;
Nit: there's really no point keeping the "clk" variable here, you could
simply "return hw->clk" if registration succeeds - note that you also
need the rest of the logic from clk_register_composite() to check that
"hw" isn't an error value.
> err_div:
> kfree(gate);
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 546e810c3560..2cfebfb61814 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -43,6 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
> u8 gate_shift, u8 gate_flags, unsigned long flags,
> spinlock_t *lock)
> {
> + struct clk_hw *hw;
> struct clk *clk;
> struct clk_mux *mux = NULL;
> struct clk_gate *gate = NULL;
> @@ -100,12 +101,12 @@ static struct clk *rockchip_clk_register_branch(const char *name,
> : &clk_divider_ops;
> }
>
> - clk = clk_register_composite(NULL, name, parent_names, num_parents,
> - mux ? &mux->hw : NULL, mux_ops,
> - div ? &div->hw : NULL, div_ops,
> - gate ? &gate->hw : NULL, gate_ops,
> - flags);
> -
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + mux ? &mux->hw : NULL, mux_ops,
> + div ? &div->hw : NULL, div_ops,
> + gate ? &gate->hw : NULL, gate_ops,
> + flags);
> + clk = hw->clk;
> if (IS_ERR(clk)) {
Similar to above, this is totally broken - you need to rework all the
error handling in terms of "hw" rather than "clk" - dereferencing an
ERR_PTR value does not yield another ERR_PTR value, it yields a crash ;)
Robin.
> ret = PTR_ERR(clk);
> goto err_composite;
> @@ -214,6 +215,7 @@ static struct clk *rockchip_clk_register_frac_branch(
> unsigned long flags, struct rockchip_clk_branch *child,
> spinlock_t *lock)
> {
> + struct clk_hw *hw;
> struct rockchip_clk_frac *frac;
> struct clk *clk;
> struct clk_gate *gate = NULL;
> @@ -255,11 +257,12 @@ static struct clk *rockchip_clk_register_frac_branch(
> div->approximation = rockchip_fractional_approximation;
> div_ops = &clk_fractional_divider_ops;
>
> - clk = clk_register_composite(NULL, name, parent_names, num_parents,
> - NULL, NULL,
> - &div->hw, div_ops,
> - gate ? &gate->hw : NULL, gate_ops,
> - flags | CLK_SET_RATE_UNGATE);
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + NULL, NULL,
> + &div->hw, div_ops,
> + gate ? &gate->hw : NULL, gate_ops,
> + flags | CLK_SET_RATE_UNGATE);
> + clk = hw->clk;
> if (IS_ERR(clk)) {
> kfree(frac);
> return clk;
> @@ -320,6 +323,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
> int gate_offset, u8 gate_shift, u8 gate_flags,
> unsigned long flags, spinlock_t *lock)
> {
> + struct clk_hw *hw;
> struct clk *clk;
> struct clk_gate *gate = NULL;
> struct clk_fixed_factor *fix = NULL;
> @@ -349,10 +353,11 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
> fix->mult = mult;
> fix->div = div;
>
> - clk = clk_register_composite(NULL, name, parent_names, num_parents,
> - NULL, NULL,
> - &fix->hw, &clk_fixed_factor_ops,
> - &gate->hw, &clk_gate_ops, flags);
> + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> + NULL, NULL,
> + &fix->hw, &clk_fixed_factor_ops,
> + &gate->hw, &clk_gate_ops, flags);
> + clk = hw->clk;
> if (IS_ERR(clk)) {
> kfree(fix);
> kfree(gate);
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
2020-09-02 6:48 ` [PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
@ 2020-09-02 6:48 ` Elaine Zhang
2020-09-02 6:48 ` [PATCH v1 3/6] clk: rockchip: Export rockchip_register_softrst() Elaine Zhang
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:48 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-ddr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 9273bce4d7b6..282b6f22eb22 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
return clk;
}
+EXPORT_SYMBOL(rockchip_clk_register_ddrclk);
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 3/6] clk: rockchip: Export rockchip_register_softrst()
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
2020-09-02 6:48 ` [PATCH v1 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
2020-09-02 6:48 ` [PATCH v1 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Elaine Zhang
@ 2020-09-02 6:48 ` Elaine Zhang
2020-09-02 6:48 ` [PATCH v1 4/6] clk: rockchip: Export some clock common APIs for module drivers Elaine Zhang
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:48 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/softrst.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..caba9055090b 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
kfree(softrst);
}
};
+EXPORT_SYMBOL(rockchip_register_softrst);
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 4/6] clk: rockchip: Export some clock common APIs for module drivers
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
` (2 preceding siblings ...)
2020-09-02 6:48 ` [PATCH v1 3/6] clk: rockchip: Export rockchip_register_softrst() Elaine Zhang
@ 2020-09-02 6:48 ` Elaine Zhang
2020-09-02 6:49 ` [PATCH v1 5/6] clk: rockchip: fix the clk config to support module build Elaine Zhang
2020-09-02 6:50 ` [PATCH v1 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
5 siblings, 0 replies; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:48 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++----------------
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 2cfebfb61814..796338c3bd6f 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -366,8 +366,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
return clk;
}
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base,
+ unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
@@ -399,14 +400,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
+EXPORT_SYMBOL(rockchip_clk_init);
-void __init rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
&ctx->clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
+EXPORT_SYMBOL(rockchip_clk_of_add_provider);
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
@@ -414,8 +417,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
if (ctx->clk_data.clks && id)
ctx->clk_data.clks[id] = clk;
}
+EXPORT_SYMBOL(rockchip_clk_add_lookup);
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
@@ -438,11 +442,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
+EXPORT_SYMBOL(rockchip_clk_register_plls);
-void __init rockchip_clk_register_branches(
- struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
@@ -571,14 +575,15 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
- unsigned int lookup_id,
- const char *name, const char *const *parent_names,
- u8 num_parents,
- const struct rockchip_cpuclk_reg_data *reg_data,
- const struct rockchip_cpuclk_rate_table *rates,
- int nrates)
+EXPORT_SYMBOL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const *parent_names,
+ u8 num_parents,
+ const struct rockchip_cpuclk_reg_data *reg_data,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates)
{
struct clk *clk;
@@ -593,9 +598,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
+EXPORT_SYMBOL(rockchip_clk_register_armclk);
-void __init rockchip_clk_protect_critical(const char *const clocks[],
- int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+ int nclocks)
{
int i;
@@ -607,6 +613,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
clk_prepare_enable(clk);
}
}
+EXPORT_SYMBOL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
@@ -626,10 +633,10 @@ static struct notifier_block rockchip_restart_handler = {
.priority = 128,
};
-void __init
+void
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
- unsigned int reg,
- void (*cb)(void))
+ unsigned int reg,
+ void (*cb)(void))
{
int ret;
@@ -641,3 +648,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
pr_err("%s: cannot register restart handler, %d\n",
__func__, ret);
}
+EXPORT_SYMBOL(rockchip_register_restart_notifier);
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 5/6] clk: rockchip: fix the clk config to support module build
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
` (3 preceding siblings ...)
2020-09-02 6:48 ` [PATCH v1 4/6] clk: rockchip: Export some clock common APIs for module drivers Elaine Zhang
@ 2020-09-02 6:49 ` Elaine Zhang
2020-09-02 6:50 ` [PATCH v1 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
5 siblings, 0 replies; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:49 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark configuration to "tristate",
to support building Rk SoCs clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/Kconfig | 1 +
drivers/clk/rockchip/Kconfig | 78 +++++++++++++++++++++++++++++++++++
drivers/clk/rockchip/Makefile | 42 ++++++++++---------
3 files changed, 101 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/rockchip/Kconfig
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac9fac3..b41aaed9bd51 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/sprd/Kconfig"
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
new file mode 100644
index 000000000000..53a44396bc35
--- /dev/null
+++ b/drivers/clk/rockchip/Kconfig
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+# common clock support for ROCKCHIP SoC family.
+
+config COMMON_CLK_ROCKCHIP
+ tristate "Rockchip clock controller common support"
+ depends on ARCH_ROCKCHIP
+ default ARCH_ROCKCHIP
+ help
+ Say y here to enable common clock controller.
+
+if COMMON_CLK_ROCKCHIP
+config CLK_PX30
+ tristate "Rockchip Px30 clock controller support"
+ default y
+ help
+ Build the driver for Px30 Clock Driver.
+
+config CLK_RV110X
+ tristate "Rockchip Rv110x clock controller support"
+ default y
+ help
+ Build the driver for Rv110x Clock Driver.
+
+config CLK_RK3036
+ tristate "Rockchip Rk3036 clock controller support"
+ default y
+ help
+ Build the driver for Rk3036 Clock Driver.
+
+config CLK_RK312X
+ tristate "Rockchip Rk312x clock controller support"
+ default y
+ help
+ Build the driver for Rk312x Clock Driver.
+
+config CLK_RK3188
+ tristate "Rockchip Rk3188 clock controller support"
+ default y
+ help
+ Build the driver for Rk3188 Clock Driver.
+
+config CLK_RK322X
+ tristate "Rockchip Rk322x clock controller support"
+ default y
+ help
+ Build the driver for Rk322x Clock Driver.
+
+config CLK_RK3288
+ tristate "Rockchip Rk3288 clock controller support"
+ depends on ARM
+ default y
+ help
+ Build the driver for Rk3288 Clock Driver.
+
+config CLK_RK3308
+ tristate "Rockchip Rk3308 clock controller support"
+ default y
+ help
+ Build the driver for Rk3308 Clock Driver.
+
+config CLK_RK3328
+ tristate "Rockchip Rk3328 clock controller support"
+ default y
+ help
+ Build the driver for Rk3328 Clock Driver.
+
+config CLK_RK3368
+ tristate "Rockchip Rk3368 clock controller support"
+ default y
+ help
+ Build the driver for Rk3368 Clock Driver.
+
+config CLK_RK3399
+ tristate "Rockchip Rk3399 clock controller support"
+ default y
+ help
+ Build the driver for Rk3399 Clock Driver.
+endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 7c5b5813a87c..a99e4d9bbae1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,24 +3,26 @@
# Rockchip Clock specific Makefile
#
-obj-y += clk.o
-obj-y += clk-pll.o
-obj-y += clk-cpu.o
-obj-y += clk-half-divider.o
-obj-y += clk-inverter.o
-obj-y += clk-mmc-phase.o
-obj-y += clk-muxgrf.o
-obj-y += clk-ddr.o
-obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
-obj-y += clk-px30.o
-obj-y += clk-rv1108.o
-obj-y += clk-rk3036.o
-obj-y += clk-rk3128.o
-obj-y += clk-rk3188.o
-obj-y += clk-rk3228.o
-obj-y += clk-rk3288.o
-obj-y += clk-rk3308.o
-obj-y += clk-rk3328.o
-obj-y += clk-rk3368.o
-obj-y += clk-rk3399.o
+clk-rockchip-y += clk.o
+clk-rockchip-y += clk-pll.o
+clk-rockchip-y += clk-cpu.o
+clk-rockchip-y += clk-half-divider.o
+clk-rockchip-y += clk-inverter.o
+clk-rockchip-y += clk-mmc-phase.o
+clk-rockchip-y += clk-muxgrf.o
+clk-rockchip-y += clk-ddr.o
+clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
+
+obj-$(CONFIG_CLK_PX30) += clk-px30.o
+obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
+obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
+obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
+obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
+obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o
+obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o
+obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
+obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
+obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
+obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v1 6/6] clk: rockchip: rk3399: Support module build
2020-09-02 6:48 [PATCH v1 0/6] clk: rockchip: Support module build Elaine Zhang
` (4 preceding siblings ...)
2020-09-02 6:49 ` [PATCH v1 5/6] clk: rockchip: fix the clk config to support module build Elaine Zhang
@ 2020-09-02 6:50 ` Elaine Zhang
2020-09-02 16:03 ` Robin Murphy
5 siblings, 1 reply; 9+ messages in thread
From: Elaine Zhang @ 2020-09-02 6:50 UTC (permalink / raw)
To: heiko
Cc: mturquette, sboyd, linux-clk, linux-rockchip, linux-kernel, xxx,
xf, huangtao, kever.yang, Elaine Zhang
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 40 +++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..a1d5704b9ba2 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include <linux/clk-provider.h>
+#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/rk3399-cru.h>
@@ -1600,3 +1602,41 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ unsigned long data;
+
+ data = (unsigned long)of_device_get_match_data(&pdev->dev);
+ if (data)
+ rk3399_pmu_clk_init(np);
+ else
+ rk3399_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = (void *)0
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = (void *)1,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v1 6/6] clk: rockchip: rk3399: Support module build
2020-09-02 6:50 ` [PATCH v1 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
@ 2020-09-02 16:03 ` Robin Murphy
0 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2020-09-02 16:03 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, sboyd, mturquette, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
On 2020-09-02 07:50, Elaine Zhang wrote:
> support CLK_OF_DECLARE and builtin_platform_driver_probe
> double clk init method.
> add module author, description and license to support building
> Soc Rk3399 clock driver as module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> drivers/clk/rockchip/clk-rk3399.c | 40 +++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index ce1d2446f142..a1d5704b9ba2 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -5,9 +5,11 @@
> */
>
> #include <linux/clk-provider.h>
> +#include <linux/module.h>
> #include <linux/io.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <dt-bindings/clock/rk3399-cru.h>
> @@ -1600,3 +1602,41 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
> rockchip_clk_of_add_provider(np, ctx);
> }
> CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
> +
> +static int __init clk_rk3399_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + unsigned long data;
> +
> + data = (unsigned long)of_device_get_match_data(&pdev->dev);
> + if (data)
> + rk3399_pmu_clk_init(np);
> + else
> + rk3399_clk_init(np);
It might be clearer and simpler to just store a function pointer in the
match data directly - there's already precedent for that elsewhere.
Robin.
> +
> + return 0;
> +}
> +
> +static const struct of_device_id clk_rk3399_match_table[] = {
> + {
> + .compatible = "rockchip,rk3399-cru",
> + .data = (void *)0
> + }, {
> + .compatible = "rockchip,rk3399-pmucru",
> + .data = (void *)1,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
> +
> +static struct platform_driver clk_rk3399_driver = {
> + .driver = {
> + .name = "clk-rk3399",
> + .of_match_table = clk_rk3399_match_table,
> + },
> +};
> +builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
> +
> +MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:clk-rk3399");
>
^ permalink raw reply [flat|nested] 9+ messages in thread