Re: [PATCH v2] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 3/6/2026 8:45 PM, Dmitry Baryshkov wrote:
> On Sat, Feb 28, 2026 at 08:34:27PM +0200, Dmitry Baryshkov wrote:
>> Due to the way the DDR controller is organized on Glymur, hardware
>> engineers strongly recommended disabling UBWC bank swizzling on Glymur.
>> Follow that recommendation.
>>
>> Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>> ---
>> Changes in v2:
>> - Fix the syntax error...
>> - Link to v1: https://lore.kernel.org/r/20260228-fix-glymur-ubwc-v1-1-d80e3fe0dcc7@oss.qualcomm.com
>> ---
>>  drivers/soc/qcom/ubwc_config.c | 3 +--
>>  1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
>> index 1c25aaf55e52..8304463f238a 100644
>> --- a/drivers/soc/qcom/ubwc_config.c
>> +++ b/drivers/soc/qcom/ubwc_config.c
>> @@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
>>  static const struct qcom_ubwc_cfg_data glymur_data = {
>>  	.ubwc_enc_version = UBWC_5_0,
>>  	.ubwc_dec_version = UBWC_5_0,
>> -	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
>> -			UBWC_SWIZZLE_ENABLE_LVL3,
>> +	.ubwc_swizzle = 0,
>>  	.ubwc_bank_spread = true,
>>  	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
>>  	.highest_bank_bit = 16,
> 
> Carrying over from v1 discussion.
> 
> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>

Sorry, please use my oss email instead:

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

-Akhil.

> 
> It depends on the fix which is currently a part of msm-fixes for the
> device to function correctly. Raised the question on IRC regarding the
> immutable tag or any other proper way to merge it.
> 
>>
>> ---
>> base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
>> change-id: 20260228-fix-glymur-ubwc-f673d5ca0581
>>
>> Best regards,
>> -- 
>> With best wishes
>> Dmitry
>>
>