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* [PATCH] ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards
@ 2024-06-17  9:14 Etienne Carriere
  2024-06-27 10:37 ` Alexandre TORGUE
  0 siblings, 1 reply; 2+ messages in thread
From: Etienne Carriere @ 2024-06-17  9:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: devicetree, linux-arm-kernel, linux-stm32, Alexandre Torgue,
	Maxime Coquelin, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
	Etienne Carriere

Define the GIC interrupt (PPI 15) to be used on ST STM32MP15x boards
for OP-TEE async notif.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 5 +++++
 arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +++++
 arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 5 +++++
 arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +++++
 4 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
index 306e1bc2a514..847b360f02fc 100644
--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
@@ -62,6 +62,11 @@ &m4_rproc {
 	reset-names = "mcu_rst", "hold_boot";
 };
 
+&optee {
+	interrupt-parent = <&intc>;
+	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
index 956da5f26c1c..43280289759d 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
@@ -68,6 +68,11 @@ &m4_rproc {
 	reset-names = "mcu_rst", "hold_boot";
 };
 
+&optee {
+	interrupt-parent = <&intc>;
+	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
index 8e4b0db198c2..6f27d794d270 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
@@ -67,6 +67,11 @@ &m4_rproc {
 	reset-names = "mcu_rst", "hold_boot";
 };
 
+&optee {
+	interrupt-parent = <&intc>;
+	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
index 72b9cab2d990..6ae391bffee5 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
@@ -72,6 +72,11 @@ &m4_rproc {
 	reset-names = "mcu_rst", "hold_boot";
 };
 
+&optee {
+	interrupt-parent = <&intc>;
+	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
-- 
2.25.1


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2024-06-17  9:14 [PATCH] ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards Etienne Carriere
2024-06-27 10:37 ` Alexandre TORGUE

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