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From: Marc Zyngier <maz@kernel.org>
To: Fuad Tabba <fuad.tabba@linux.dev>
Cc: Oliver Upton <oupton@kernel.org>,
	kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	Joey Gouly <joey.gouly@arm.com>,
	Steffen Eiden <seiden@linux.ibm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Vincent Donnefort <vdonnefort@google.com>,
	kernel-team@android.com, linux-kernel@vger.kernel.org,
	Oculytic <oculytic@gmail.com>, Fuad Tabba <tabba@google.com>
Subject: Re: [PATCH 3/3] KVM: arm64: Disable host PMU counters for protected guests
Date: Tue, 27 Oct 2026 09:32:32 +0000	[thread overview]
Message-ID: <86wlr3xzdb.wl-maz@kernel.org> (raw)
In-Reply-To: <20261027081147.498183-4-fuad.tabba@linux.dev>

On Tue, 27 Oct 2026 08:11:47 +0000,
Fuad Tabba <fuad.tabba@linux.dev> wrote:
> 
> A protected guest has no PMU, and EL2 clears MDCR_EL2.HPME for it.
> However, HPME has no effect, since __pkvm_vcpu_load() sets HPMN to cover
> every event counter, and HPME never covers the cycle or instruction
> counter. The counters the host has enabled therefore keep counting the
> guest.
> 
> Stop them in the world switch while a protected guest runs, reading
> PMCNTENSET_EL0 rather than trusting the host-controlled events mask.
> Gate this on a new per-CPU HAS_PMUV3 flag, since system_supports_pmuv3()
> is false when the CPUs implement different PMU versions.
> 
> Side channels are outside pKVM's threat model, so this is hardening
> rather than a fix.
> 
> Reported-by: Oculytic <oculytic@gmail.com>
> Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
> ---
>  arch/arm64/include/asm/kvm_host.h |  1 +
>  arch/arm64/kvm/debug.c            |  4 +++-
>  arch/arm64/kvm/hyp/nvhe/switch.c  | 24 ++++++++++++++++++++++++
>  3 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 1c6632216e327..7ecb55e5018eb 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -834,6 +834,7 @@ struct kvm_host_data {
>  #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT		4
>  #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED		5
>  #define KVM_HOST_DATA_FLAG_HAS_BRBE			6
> +#define KVM_HOST_DATA_FLAG_HAS_PMUV3			7
>  	unsigned long flags;
>  
>  	struct kvm_cpu_context host_ctxt;
> diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c
> index f4d7b12045e8f..3c74b076b5278 100644
> --- a/arch/arm64/kvm/debug.c
> +++ b/arch/arm64/kvm/debug.c
> @@ -79,9 +79,11 @@ void kvm_init_host_debug_data(void)
>  	unsigned int pmuver = cpuid_feature_extract_unsigned_field(dfr0,
>  								   ID_AA64DFR0_EL1_PMUVer_SHIFT);
>  
> -	if (pmuv3_implemented(pmuver))
> +	if (pmuv3_implemented(pmuver)) {
>  		*host_data_ptr(nr_event_counters) = FIELD_GET(ARMV8_PMU_PMCR_N,
>  							      read_sysreg(pmcr_el0));
> +		host_data_set_flag(HAS_PMUV3);

Honestly, I don't think we need to work out which CPUs have PMUv3 and
which don't. I'd be perfectly happy to disable KVM on asymmetric
systems, simply because they don't exist.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2026-10-27  9:32 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-27  8:11 [PATCH 0/3] KVM: arm64: Fix PMU handling in pKVM Fuad Tabba
2026-10-27  8:11 ` [PATCH 1/3] KVM: arm64: Synchronise kvm_host_data before host deprivileging Fuad Tabba
2026-10-27  8:11 ` [PATCH 2/3] KVM: arm64: Pass the PMU events to the hyp vCPU of non-protected guests Fuad Tabba
2026-10-27 11:05   ` Vincent Donnefort
2026-10-27  8:11 ` [PATCH 3/3] KVM: arm64: Disable host PMU counters for protected guests Fuad Tabba
2026-10-27  9:32   ` Marc Zyngier [this message]
2026-10-27  9:41     ` Fuad Tabba

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