* [PATCH v5 2/2] arm64: dts: qcom: shikra: Add coresight nodes
2026-07-23 8:26 [PATCH v5 0/2] Add CoreSight nodes for Qualcomm Shikra SoC Jie Gan
2026-07-23 8:26 ` [PATCH v5 1/2] dt-bindings: arm: qcom,coresight-ctcu: Add Shikra Jie Gan
@ 2026-07-23 8:26 ` Jie Gan
2026-07-24 8:18 ` Konrad Dybcio
1 sibling, 1 reply; 6+ messages in thread
From: Jie Gan @ 2026-07-23 8:26 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yuanfang Zhang, Mao Jinlong,
Jie Gan, Bjorn Andersson, Konrad Dybcio, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree, linux-kernel
Add DT nodes for the CoreSight debug and trace subsystem on Qualcomm
Shikra SoC.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 1295 ++++++++++++++++++++++++++++++++++
1 file changed, 1295 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8e..eb0f3c36068f 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -113,6 +113,88 @@ l3: l3-cache {
};
};
+ dummy-eud {
+ compatible = "arm,coresight-dummy-sink";
+
+ label = "eud";
+
+ in-ports {
+ port {
+ eud_in: endpoint {
+ remote-endpoint = <&replicator_eud_out1>;
+ };
+ };
+ };
+ };
+
+ etm0 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in0>;
+ };
+ };
+ };
+ };
+
+ etm1 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in1>;
+ };
+ };
+ };
+ };
+
+ etm2 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in2>;
+ };
+ };
+ };
+ };
+
+ etm3 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in3>;
+ };
+ };
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-shikra", "qcom,scm";
@@ -131,6 +213,21 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ modem-etm0 {
+ compatible = "arm,coresight-dummy-source";
+
+ label = "modem_etm0";
+ arm,static-trace-id = <36>;
+
+ out-ports {
+ port {
+ modem_etm0_out: endpoint {
+ remote-endpoint = <&funnel_in1_in4>;
+ };
+ };
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@@ -640,6 +737,1189 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ ctcu@8001000 {
+ compatible = "qcom,shikra-ctcu", "qcom,sa8775p-ctcu";
+ reg = <0x0 0x08001000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb";
+
+ in-ports {
+ port {
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+ };
+ };
+
+ stm@8002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x08002000 0x0 0x1000>,
+ <0x0 0x0e280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel_in0_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@8003000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08003000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_dcc";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_dcc_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@8004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x08004000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_qdss_in0: endpoint {
+ remote-endpoint = <&tpdm_dcc_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_qdss_in1: endpoint {
+ remote-endpoint = <&tpdm_spdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out: endpoint {
+ remote-endpoint = <&funnel_in0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@800f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x0800f000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_spdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_spdm_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@8041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08041000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+
+ funnel_in0_in5: endpoint {
+ remote-endpoint = <&snoc_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_in0_in6: endpoint {
+ remote-endpoint = <&tpda_qdss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_in0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in0_out: endpoint {
+ remote-endpoint = <&funnel_merg_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@8042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08042000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ funnel_in1_in1: endpoint {
+ remote-endpoint = <&tpda_aodbg_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ funnel_in1_in4: endpoint {
+ remote-endpoint = <&modem_etm0_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_in1_in6: endpoint {
+ remote-endpoint = <&funnel_cpuss1_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_in1_in7: endpoint {
+ remote-endpoint = <&funnel_center_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in1_out: endpoint {
+ remote-endpoint = <&funnel_merg_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@8045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08045000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_merg_in0: endpoint {
+ remote-endpoint = <&funnel_in0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ funnel_merg_in1: endpoint {
+ remote-endpoint = <&funnel_in1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_merg_out: endpoint {
+ remote-endpoint = <&tmc_etf_in>;
+ };
+ };
+ };
+ };
+
+ replicator@8046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x08046000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ replicator_qdss_in: endpoint {
+ remote-endpoint = <&tmc_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ replicator_qdss_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ replicator_qdss_out1: endpoint {
+ remote-endpoint = <&replicator_eud_in>;
+ };
+ };
+ };
+ };
+
+ tmc@8047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x08047000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in: endpoint {
+ remote-endpoint = <&funnel_merg_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tmc_etf_out: endpoint {
+ remote-endpoint = <&replicator_qdss_in>;
+ };
+ };
+ };
+ };
+
+ tmc@8048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x08048000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ iommus = <&apps_smmu 0x0160 0x0>;
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&replicator_qdss_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@804a000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x0804a000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ replicator_eud_in: endpoint {
+ remote-endpoint = <&replicator_qdss_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ replicator_eud_out1: endpoint {
+ remote-endpoint = <&eud_in>;
+ };
+ };
+ };
+ };
+
+ tpdm@8800000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08800000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_cdsp";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <4>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_out: endpoint {
+ remote-endpoint = <&funnel_cdsp_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@8801000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08801000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_cdsp_in0: endpoint {
+ remote-endpoint = <&tpdm_cdsp_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_cdsp_out0: endpoint {
+ remote-endpoint = <&tpda_center_in3>;
+ };
+ };
+ };
+ };
+
+ cti@8807000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08807000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_turing_q6";
+ };
+
+ cti@8833000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08833000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_mss_q6";
+ };
+
+ tpdm@8840000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08840000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_vsense";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_vsense_out: endpoint {
+ remote-endpoint = <&tpda_center_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@8844000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08844000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_dlct_1";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_dlct_1_out: endpoint {
+ remote-endpoint = <&tpda_center_in13>;
+ };
+ };
+ };
+ };
+
+ tpda@8845000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x08845000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_center_in0: endpoint {
+ remote-endpoint = <&funnel_mcu_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_center_in2: endpoint {
+ remote-endpoint = <&tpdm_dlct_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_center_in3: endpoint {
+ remote-endpoint = <&funnel_cdsp_out0>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ tpda_center_in4: endpoint {
+ remote-endpoint = <&funnel_ddr_out0>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ tpda_center_in6: endpoint {
+ remote-endpoint = <&tpdm_vsense_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ tpda_center_in7: endpoint {
+ remote-endpoint = <&tpdm_prng_out>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ tpda_center_in8: endpoint {
+ remote-endpoint = <&tpdm_west_out>;
+ };
+ };
+
+ port@9 {
+ reg = <9>;
+
+ tpda_center_in9: endpoint {
+ remote-endpoint = <&tpdm_qm_out>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ tpda_center_in10: endpoint {
+ remote-endpoint = <&tpdm_pimem_out>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ tpda_center_in13: endpoint {
+ remote-endpoint = <&tpdm_dlct_1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_center_out: endpoint {
+ remote-endpoint = <&funnel_center_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@8846000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08846000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_center_in0: endpoint {
+ remote-endpoint = <&tpda_center_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_center_out: endpoint {
+ remote-endpoint = <&funnel_in1_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@884c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x0884c000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_prng";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_prng_out: endpoint {
+ remote-endpoint = <&tpda_center_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@8850000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08850000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_pimem";
+ qcom,cmb-element-bits = <64>;
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_pimem_out: endpoint {
+ remote-endpoint = <&tpda_center_in10>;
+ };
+ };
+ };
+ };
+
+ tpdm@8980000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08980000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_mcu";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <16>;
+
+ out-ports {
+ port {
+ tpdm_mcu_out: endpoint {
+ remote-endpoint = <&funnel_mcu_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@8982000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08982000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_mcu_in0: endpoint {
+ remote-endpoint = <&tpdm_mcu_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_mcu_out: endpoint {
+ remote-endpoint = <&tpda_center_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@89d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x089d0000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_qm";
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_qm_out: endpoint {
+ remote-endpoint = <&tpda_center_in9>;
+ };
+ };
+ };
+ };
+
+ tpdm@8a01000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08a01000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_mapss";
+ qcom,cmb-element-bits = <32>;
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <16>;
+
+ out-ports {
+ port {
+ tpdm_mapss_out: endpoint {
+ remote-endpoint = <&tpda_aodbg_in>;
+ };
+ };
+ };
+ };
+
+ cti@8a02000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08a02000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_mapss";
+ };
+
+ tpda@8a04000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x08a04000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tpda_aodbg_in: endpoint {
+ remote-endpoint = <&tpdm_mapss_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_aodbg_out: endpoint {
+ remote-endpoint = <&funnel_in1_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@8a58000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08a58000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_west";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <16>;
+
+ out-ports {
+ port {
+ tpdm_west_out: endpoint {
+ remote-endpoint = <&tpda_center_in8>;
+ };
+ };
+ };
+ };
+
+ cti@8b30000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b30000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_cortex_m3";
+ };
+
+ tpdm@8b58000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08b58000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_dlct";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <16>;
+
+ out-ports {
+ port {
+ tpdm_dlct_out: endpoint {
+ remote-endpoint = <&tpda_center_in2>;
+ };
+ };
+ };
+ };
+
+ cti@8b59000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b59000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_dlct_0";
+ };
+
+ cti@8b5a000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b5a000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_dlct_1";
+ };
+
+ cti@8b5b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b5b000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_dlct_2";
+ };
+
+ cti@8b5c000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b5c000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_dlct_3";
+ };
+
+ tpdm@8b60000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x08b60000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_ddr";
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <1>;
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_ddr_out: endpoint {
+ remote-endpoint = <&funnel_ddr_in0>;
+ };
+ };
+ };
+ };
+
+ cti@8b62000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b62000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_ddr_dl_0";
+ };
+
+ funnel@8b65000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x08b65000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_ddr_in0: endpoint {
+ remote-endpoint = <&tpdm_ddr_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_ddr_out0: endpoint {
+ remote-endpoint = <&tpda_center_in4>;
+ };
+ };
+ };
+ };
+
+ cti@8b70000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b70000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_ddr_dl_0_1";
+ };
+
+ cti@8b71000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x08b71000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_ddr_dl_1_1";
+ };
+
+ cti@9020000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x09020000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_pe0";
+ };
+
+ cti@90e0000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x090e0000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_cluster";
+ };
+
+ cti@9120000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x09120000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_pe1";
+ };
+
+ cti@9220000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x09220000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_pe2";
+ };
+
+ cti@9320000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x09320000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_pe3";
+ };
+
+ funnel@9800000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x09800000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_cpuss0_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ funnel_cpuss0_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ funnel_cpuss0_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ funnel_cpuss0_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_cpuss0_out: endpoint {
+ remote-endpoint = <&funnel_cpuss1_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@9810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x09810000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_cpuss1_in0: endpoint {
+ remote-endpoint = <&funnel_cpuss0_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ funnel_cpuss1_in3: endpoint {
+ remote-endpoint = <&tpda_apss_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_cpuss1_out: endpoint {
+ remote-endpoint = <&funnel_in1_in6>;
+ };
+ };
+ };
+ };
+
+ cti@982b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x0982b000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_riscv";
+ };
+
+ tpdm@9860000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x09860000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_actpm";
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <1>;
+
+ out-ports {
+ port {
+ tpdm_actpm_out: endpoint {
+ remote-endpoint = <&tpda_apss_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@9861000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x09861000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_hwe";
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_hwe_out: endpoint {
+ remote-endpoint = <&tpda_apss_in3>;
+ };
+ };
+ };
+ };
+
+ tpda@9863000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x09863000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_apss_in0: endpoint {
+ remote-endpoint = <&tpdm_llm_silver_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_apss_in2: endpoint {
+ remote-endpoint = <&tpdm_actpm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_apss_in3: endpoint {
+ remote-endpoint = <&tpdm_hwe_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_apss_out: endpoint {
+ remote-endpoint = <&funnel_cpuss1_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@98a0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x098a0000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ label = "tpdm_llm_silver";
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <12>;
+
+ out-ports {
+ port {
+ tpdm_llm_silver_out: endpoint {
+ remote-endpoint = <&tpda_apss_in0>;
+ };
+ };
+ };
+ };
+
+ cti@98e0000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x098e0000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_0";
+ };
+
+ cti@98f0000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x098f0000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_1";
+ };
+
+ cti@9900000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x09900000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ label = "cti_apss_2";
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
@@ -831,6 +2111,21 @@ frame@f42d000 {
};
};
+ snoc {
+ compatible = "arm,coresight-dummy-source";
+
+ label = "snoc";
+ arm,static-trace-id = <18>;
+
+ out-ports {
+ port {
+ snoc_out: endpoint {
+ remote-endpoint = <&funnel_in0_in5>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread