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From: Marc Zyngier <marc.zyngier@arm.com>
To: Guo Ren <ren_guo@c-sky.com>,
	tglx@linutronix.de, jason@lakedaemon.net, robh+dt@kernel.org,
	mark.rutland@arm.com, daniel.lezcano@linaro.org,
	will.deacon@arm.com, jhogan@kernel.org, paul.burton@mips.com,
	peterz@infradead.org, arnd@arndb.de
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V11 1/8] irqchip: add C-SKY SMP interrupt controller
Date: Tue, 9 Oct 2018 16:11:05 +0100	[thread overview]
Message-ID: <8772c090-a139-04e4-a55f-820afe1bb5bd@arm.com> (raw)
In-Reply-To: <83d216b3fed039037ebe8b8513f3c51a36934e74.1539095312.git.ren_guo@c-sky.com>

On 09/10/18 15:41, Guo Ren wrote:
>   - Irq-csky-mpintc is C-SKY smp system interrupt controller and it
>     could support 16 soft irqs, 16 private irqs, and 992 max common
>     irqs.
> 
> Changelog:
>   - Convert the cpumask to an interrupt-controller specific representation
>     in driver's code, and not the SMP code's.
>   - pass checkpatch.pl
>   - Move IPI_IRQ into the driver
>   - Remove irq_set_default_host() and use set_ipi_irq_mapping()
>   - Change name with upstream feed-back
>   - Change irq map, reserve soft_irq & private_irq space
>   - Add License and Copyright
>   - Support set_affinity for irq balance in SMP
> 
> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>

[...]

> +/* C-SKY multi processor interrupt controller */
> +static int __init
> +csky_mpintc_init(struct device_node *node, struct device_node *parent)
> +{
> +	unsigned int cpu, nr_irq;
> +	int ret;
> +
> +	if (parent)
> +		return 0;
> +
> +	ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq);
> +	if (ret < 0)
> +		nr_irq = INTC_IRQS;
> +
> +	if (INTCG_base == NULL) {
> +		INTCG_base = ioremap(mfcr("cr<31, 14>"),
> +				     INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
> +		if (INTCG_base == NULL)
> +			return -EIO;
> +
> +		INTCL_base = INTCG_base + INTCG_SIZE;
> +
> +		writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
> +	}
> +
> +	root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops,
> +					    NULL);
> +	if (!root_domain)
> +		return -ENXIO;
> +
> +	/* for every cpu */
> +	for_each_present_cpu(cpu) {
> +		per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
> +		writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
> +	}
> +
> +	set_handle_irq(&csky_mpintc_handler);
> +
> +#ifdef CONFIG_SMP
> +	set_send_ipi(&csky_mpintc_send_ipi);
> +
> +	set_ipi_irq_mapping(&csky_mpintc_ipi_irq_mapping);

Same remark as before.

You do not need this second callback, and you should redefine 
set_send_ipi to take an irq number:

	ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
	if (!ipi_irq)
		[handle error]

	set_send_ipi(csky_mpintc_send_ipi, ipi_irq);

and you can then delete both set_ipi_irq_mapping and 
csky_mpintc_handler, none of which serve any purpose.

In your SMP code:

void __init set_send_ipi(void (*func)(const struct cpumask *), int irq)
{
	if (send_arch_ipi)
		return;

	send_arch_ipi = func;
	ipi_irq = irq;
}

and simplify setup_smp_ipi.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2018-10-09 15:11 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-09 14:41 [PATCH V11 0/8] C-SKY(csky) Linux Kernel Driver Guo Ren
2018-10-09 14:41 ` [PATCH V11 1/8] irqchip: add C-SKY SMP interrupt controller Guo Ren
2018-10-09 15:11   ` Marc Zyngier [this message]
2018-10-12  3:21     ` Guo Ren
2018-10-09 14:41 ` [PATCH V11 2/8] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren
2018-10-09 14:41 ` [PATCH V11 3/8] irqchip: add C-SKY APB bus interrupt controller Guo Ren
2018-10-09 14:41 ` [PATCH V11 4/8] dt-bindings: interrupt-controller: C-SKY APB intc Guo Ren
2018-10-09 14:41 ` [PATCH V11 5/8] clocksource: add C-SKY SMP timer Guo Ren
2018-10-09 14:41 ` [PATCH V11 6/8] dt-bindings: timer: C-SKY Multi-processor timer Guo Ren
2018-10-09 14:41 ` [PATCH V11 7/8] clocksource: add gx6605s SOC system timer Guo Ren
2018-10-09 14:41 ` [PATCH V11 8/8] dt-bindings: timer: gx6605s SOC timer Guo Ren

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