Re: [PATCH 6/7] ASoC: renesas: rz-ssi: Add support for 24 bits sample width

[Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>]

Hi

> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add support for 24 bits sample format width for RZ/G2L SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
(snip)
>  	ssicr |= SSICR_CKDV(clk_ckdv);
> -	ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
> +	switch (ssi->hw_params_cache.sample_width) {
> +	case 16:
> +		ssicr |= SSICR_DWL(1);
> +		break;
> +	case 24:
> +		ssicr |= SSICR_PDTA;
> +		ssicr |= SSICR_DWL(5);

nitpick
It can be 1 line ?

> @@ -662,8 +697,13 @@ static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
>  	cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
>  	cfg.dst_addr = ssi->phys + SSIFTDR;
>  	cfg.src_addr = ssi->phys + SSIFRDR;
> -	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> -	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +	if (ssi->hw_params_cache.sample_width == 24) {
> +		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	} else {
> +		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +	}

You can reduce extra if check when 32 case ([7/7]) if it was

	if (xxx == 16) {
		...
	} else { // for 24, 32
		...
	}

Thank you for your help !!

Best regards
---
Kuninori Morimoto