[PATCH v3 0/2] J784S4/J742S2: Enable ACSPCIE0 output for PCIe1

[PATCH v3 0/2] J784S4/J742S2: Enable ACSPCIE0 output for PCIe1

[Siddharth Vadapalli]

Hello,

This series enables the reference clock output from the ACSPCIE0 module
to the PCIe Connector corresponding to the PCIe1 instance of PCIe on
J784S4-EVM and J742S2-EVM.

Series is based on linux-next tagged next-20250417.

The previous versions of this series were a single patch. Based on the
feedback received on previous versions, the SoC and Board support has
been split in order to allow reuse for other Boards based on the same
SoC.

v2 patch:
https://lore.kernel.org/r/20250411121307.793646-1-s-vadapalli@ti.com/
Changes since v2 patch:
- The SoC and board changes have been split across:
  k3-j784s4-j742s2-main-common.dtsi and k3-j784s4-j742s2-evm-common.dtsi
  respectively.

v1 patch:
https://lore.kernel.org/r/20240715123301.1184833-1-s-vadapalli@ti.com/
Changes since v1 patch:
- Rebased patch on linux-next tagged next-20241209.
- Moved changes from "k3-j784s4-main.dtsi" to its equivalent now which
  is "k3-j784s4-j742s2-main-common.dtsi" since PCIe1 is common to both
  J742S2 and J784S4.
- Renamed "acspcie0-proxy-ctrl" to "clock-controller" to follow generic
  node naming convention.
- Added "ti,syscon-acspcie-proxy-ctrl" property at the end of the node
  since vendor specific properties should be placed at the end.

Logs validating that an NVMe SSD connected to the PCIe Connector on
J784S4-EVM receives the reference clock from the ACSPCIE0 module and is
therefore enumerated successfully:
https://gist.github.com/Siddharth-Vadapalli-at-TI/905bceb2b6c0e1fc6b80cd2ddaf5bd0e

Regards,
Siddharth.

Siddharth Vadapalli (2):
  arm64: dts: ti: k3-j784s4-j742s2-main-common: add ACSPCIE0 node
  arm64: dts: ti: k3-j784s4-j742s2-evm-common: enable ACSPCIE0 output
    for PCIe1

 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi  | 6 ++++++
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 5 +++++
 2 files changed, 11 insertions(+)

-- 
2.34.1

[PATCH v3 1/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: add ACSPCIE0 node

[Siddharth Vadapalli]

The ACSPCIE0 module on TI's J784S4 SoC is capable of driving the
reference clock required by the PCIe Endpoint device. It is an
alternative to on-board and external reference clock generators.
Add the device-tree node for the same.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

The previous versions of this series were a single patch. Based on the
feedback received on previous versions, the SoC and Board support has
been split in order to allow reuse for other Boards based on the same
SoC.

v2 patch:
https://lore.kernel.org/r/20250411121307.793646-1-s-vadapalli@ti.com/
Changes since v2 patch:
- The SoC and board changes have been split across:
  k3-j784s4-j742s2-main-common.dtsi and k3-j784s4-j742s2-evm-common.dtsi
  respectively.

Regards,
Siddharth.

 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 1944616ab357..f03b2b6d5d03 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -126,6 +126,11 @@ audio_refclk1: clock@82e4 {
 			assigned-clock-parents = <&k3_clks 157 63>;
 			#clock-cells = <0>;
 		};
+
+		acspcie0_proxy_ctrl: clock-controller@1a090 {
+			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+			reg = <0x1a090 0x4>;
+		};
 	};
 
 	main_ehrpwm0: pwm@3000000 {
-- 
2.34.1

[PATCH v3 2/2] arm64: dts: ti: k3-j784s4-j742s2-evm-common: enable ACSPCIE0 output for PCIe1

[Siddharth Vadapalli]

The PCIe reference clock required by the PCIe Endpoints connected to the
PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM
and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree
support for enabling the same.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

The previous versions of this series were a single patch. Based on the
feedback received on previous versions, the SoC and Board support has
been split in order to allow reuse for other Boards based on the same
SoC.

v2 patch:
https://lore.kernel.org/r/20250411121307.793646-1-s-vadapalli@ti.com/
Changes since v2 patch:
- The SoC and board changes have been split across:
  k3-j784s4-j742s2-main-common.dtsi and k3-j784s4-j742s2-evm-common.dtsi
  respectively.

Regards,
Siddharth.

 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
index 2664f74a9c7a..fa656b7b13a1 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -5,6 +5,9 @@
  * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458
  * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001
  */
+
+#include <dt-bindings/phy/phy-cadence.h>
+
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
@@ -1407,10 +1410,13 @@ &main_mcan4 {
 
 &pcie1_rc {
 	status = "okay";
+	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+	clock-names = "fck", "pcie_refclk";
 	num-lanes = <2>;
 	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes0_pcie1_link>;
 	phy-names = "pcie-phy";
+	ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;
 };
 
 &serdes1 {
-- 
2.34.1

Re: [PATCH v3 2/2] arm64: dts: ti: k3-j784s4-j742s2-evm-common: enable ACSPCIE0 output for PCIe1

[Kumar, Udit]

Thanks for fixing at board level

On 4/22/2025 6:02 PM, Siddharth Vadapalli wrote:
> The PCIe reference clock required by the PCIe Endpoints connected to the
> PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM
> and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree
> support for enabling the same.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> The previous versions of this series were a single patch. Based on the
> feedback received on previous versions, the SoC and Board support has
> been split in order to allow reuse for other Boards based on the same
> SoC.
>
> v2 patch:
> https://lore.kernel.org/r/20250411121307.793646-1-s-vadapalli@ti.com/
> Changes since v2 patch:
> - The SoC and board changes have been split across:
>    k3-j784s4-j742s2-main-common.dtsi and k3-j784s4-j742s2-evm-common.dtsi
>    respectively.
>
> Regards,
> Siddharth.
>
>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> index 2664f74a9c7a..fa656b7b13a1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> @@ -5,6 +5,9 @@
>    * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458
>    * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001
>    */
> +
> +#include <dt-bindings/phy/phy-cadence.h>
> +
>   / {
>   	chosen {
>   		stdout-path = "serial2:115200n8";
> @@ -1407,10 +1410,13 @@ &main_mcan4 {
>   
>   &pcie1_rc {
>   	status = "okay";
> +	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
> +	clock-names = "fck", "pcie_refclk";
>   	num-lanes = <2>;
>   	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
>   	phys = <&serdes0_pcie1_link>;
>   	phy-names = "pcie-phy";
> +	ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;

Reviewed-by: Udit Kumar <u-kumar1@ti.com>


>   };
>   
>   &serdes1 {

Re: [PATCH v3 1/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: add ACSPCIE0 node

[Kumar, Udit]

On 4/22/2025 6:02 PM, Siddharth Vadapalli wrote:
> The ACSPCIE0 module on TI's J784S4 SoC is capable of driving the
> reference clock required by the PCIe Endpoint device. It is an
> alternative to on-board and external reference clock generators.
> Add the device-tree node for the same.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> The previous versions of this series were a single patch. Based on the
> feedback received on previous versions, the SoC and Board support has
> been split in order to allow reuse for other Boards based on the same
> SoC.
>
> v2 patch:
> https://lore.kernel.org/r/20250411121307.793646-1-s-vadapalli@ti.com/
> Changes since v2 patch:
> - The SoC and board changes have been split across:
>    k3-j784s4-j742s2-main-common.dtsi and k3-j784s4-j742s2-evm-common.dtsi
>    respectively.
>
> Regards,
> Siddharth.
>
>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index 1944616ab357..f03b2b6d5d03 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -126,6 +126,11 @@ audio_refclk1: clock@82e4 {
>   			assigned-clock-parents = <&k3_clks 157 63>;
>   			#clock-cells = <0>;
>   		};
> +
> +		acspcie0_proxy_ctrl: clock-controller@1a090 {
> +			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
> +			reg = <0x1a090 0x4>;

Reviewed-by: Udit Kumar <u-kumar1@ti.com>


> +		};
>   	};
>   
>   	main_ehrpwm0: pwm@3000000 {

Re: [PATCH v3 0/2] J784S4/J742S2: Enable ACSPCIE0 output for PCIe1

[Nishanth Menon]

Hi Siddharth Vadapalli,

On Tue, 22 Apr 2025 18:02:16 +0530, Siddharth Vadapalli wrote:
> This series enables the reference clock output from the ACSPCIE0 module
> to the PCIe Connector corresponding to the PCIe1 instance of PCIe on
> J784S4-EVM and J742S2-EVM.
> 
> Series is based on linux-next tagged next-20250417.
> 
> The previous versions of this series were a single patch. Based on the
> feedback received on previous versions, the SoC and Board support has
> been split in order to allow reuse for other Boards based on the same
> SoC.
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/2] arm64: dts: ti: k3-j784s4-j742s2-main-common: add ACSPCIE0 node
      commit: 9bfebd8750a06f5f8bf16ac58eb7deb638686d07
[2/2] arm64: dts: ti: k3-j784s4-j742s2-evm-common: enable ACSPCIE0 output for PCIe1
      commit: e3dfcf482d0787a5882f10a33daa4c1ec62b87d2

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
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