Re: [PATCH v6 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init

[Bryan O'Donoghue <bryan.odonoghue@linaro.org>]

On 05/06/2026 15:47, Michael Srba wrote:
>> So, hex values from downstream in this case are acceptable.
>>
>> OTOH vendors can and should enumerate their registers in an upstream 
>> submission.
> I thought this was the policy indeed, but this made me wonder if ALL the 
> magic numbers
> in that file were added by volunteers. And weirdly I found this:
> https://github.com/torvalds/linux/ 
> commit/7803b63a1640a0a39e3ebad487b33cb2d26e778b
> and possibly some other commits look like they were made by people on 
> Qualcomm's
> payroll. This specifically is QUIC, and idk how much documentation 
> access they have,
> but at minimum I assume they had access to the CTRLn register names? 
> (fwiw it's entirely
> plausible that the registers don't actually *have* better names).
> 
> I didn't follow the relevant ML discussions, but it seems to me like 
> they should've
> been told to document the registers?

"That money was just resting in my account"

There's alot of technical debt to digest, which I think should be solved 
in the new PHY API driver.

- Move to new driver
- Start enumerating registers correctly
- Transition to QMP PHY levels of lane config instead of long lists
   of "mission mode" writes.

If you ever rent a car in Ireland and get lost, you might ask a local 
"how do I get to Tip from here" and we'd scratch our heads under a flat 
cap and say something like "ah well shure, I wouldn't start from here" ;)

---
bod