Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

["Vesa Jääskeläinen" <vesa.jaaskelainen@vaisala.com>]

On 10.7.2023 21.38, Andrew Lunn wrote:
> On Mon, Jul 10, 2023 at 08:56:18PM +0300, Vesa Jääskeläinen wrote:
>> Add support to specify either class A or class B (default) for line driver.
>>
>> Class A: full MLT-3 on both Tx+ and Tx–
>> Class B: reduced MLT-3
>>
>> By default the PHY is in Class B mode.
> Hi Vesa
>
> Do you have a reference to 802.3 or some other document which
> describes these. How does reduced differ from full? Is this really a
> hardware property of the board?
>
> Thanks
> 	Andrew

Hi Andrew,

This is needed for configuration in link between DP83822 and Ethernet 
Switch chip. In the connection there there is no Ethernet cable at all 
but routes within the circuit boards but instead has capacitive coupling 
on routes.

The other Ethernet port with the same phy is connected to normal 
Ethernet cable and in there this configuration is not needed.

So the setting itself is related to specific circuit board design.

MLT-3 is related to encoding used in the signals -- I suppose wiki page 
is good introduction reference:

https://en.wikipedia.org/wiki/MLT-3_encoding

I suppose this question in TI's forum gives indication what is the 
effect of the setting:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/572998/dp83822hf-transformerless-operation

TI's datasheet is not too verbose about the effect:

https://www.ti.com/lit/ds/symlink/dp83822hf.pdf?ts=1688188848392&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83822HF

I cannot say I am expert on the Ethernet line encoding -- my 
understanding is that full MLT-3 is "normal" signaling mode and reduced 
MLT-3 mode is extension on the chip to perhaps reduce energy consumption 
with real Ethernet cables or something like that but in chip-to-chip 
link the reduced mode does not work and full MLT-3 is needed in order 
for link to come up.

I hope this helps?

Thanks,
Vesa Jääskeläinen