Re: [PATCH v3 1/2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 21/05/26 1:00 am, Bjorn Helgaas wrote:
> On Fri, May 15, 2026 at 12:37:52PM +0530, Manikanta Maddireddy wrote:
>> Program the Synopsys DesignWare PORT_AFR L1 entrance latency field from the
>> optional aspm-l1-entry-delay-ns device tree property (nanoseconds).
>>
>> Convert delay to whole microseconds with ceiling division (DIV_ROUND_UP),
>> then derive the 3-bit hw encoding as the minimum of order_base_2(us) and 7.
>> If the property is not present or cannot be read, default to 7.
>>
>> Hardware encoding (PORT_AFR L1 entrance latency, bits 27:29):
>>
>>    +--------------------------+----------+
>>    | Advertised maximum       | Code     |
>>    +--------------------------+----------+
>>    | Maximum of 1 us          | 000b     |
>>    +--------------------------+----------+
>>    | Maximum of 2 us          | 001b     |
>>    +--------------------------+----------+
>>    | Maximum of 4 us          | 010b     |
>>    +--------------------------+----------+
>>    | Maximum of 8 us          | 011b     |
>>    +--------------------------+----------+
>>    | Maximum of 16 us         | 100b     |
>>    +--------------------------+----------+
>>    | Maximum of 32 us         | 101b     |
>>    +--------------------------+----------+
>>    | Maximum of 64 us         | 110b     |
>>    +--------------------------+----------+
>>    | Rest                     | 111b     |
>>    +--------------------------+----------+
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> V2: Fixed commit message as per review comments.
>> V3: Fixed encoding to handle all cases per above table.
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 9dcfa194050e..5309a2f1356d 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -272,6 +272,7 @@ struct tegra_pcie_dw {
>>   	u32 aspm_cmrt;
>>   	u32 aspm_pwr_on_t;
>>   	u32 aspm_l0s_enter_lat;
>> +	u32 aspm_l1_enter_lat;
>>   
>>   	struct regulator *pex_ctl_supply;
>>   	struct regulator *slot_ctl_3v3;
>> @@ -715,6 +716,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>>   	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>>   	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
>>   	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
>> +	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
>> +	val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
> 
> Thanks for your patch!
> 
> I think follow-on patches could use FIELD_MODIFY() for
> PORT_AFR_L1_ENTRANCE_LAT_MASK and PORT_AFR_L0S_ENTRANCE_LAT_MASK.
> 
> It would be good to remove all these _SHIFT #defines in a future patch,
> if possible:
> 
>    PORT_AFR_L0S_ENTRANCE_LAT_SHIFT
>    PORT_AFR_L1_ENTRANCE_LAT_SHIFT
>    GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT
>    PCIE_MSIX_DOORBELL_PF_SHIFT
>    EVENT_COUNTER_ENABLE_SHIFT
>    EVENT_COUNTER_EVENT_SEL_SHIFT
>    EVENT_COUNTER_GROUP_SEL_SHIFT
> 
> The uses can probably be replaced with FIELD_MODIFY() and
> FIELD_PREP(), possibly with the addition of a _MASK #define or two.
> 


Noted, I will send a patch to remove all _SHIFT #defines.

Thanks,
Manikanta
>>   	val |= PORT_AFR_ENTER_ASPM;
>>   	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
>>   }
>> @@ -1115,6 +1118,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>>   {
>>   	struct platform_device *pdev = to_platform_device(pcie->dev);
>>   	struct device_node *np = pcie->dev->of_node;
>> +	u32 val;
>>   	int ret;
>>   
>>   	pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>> @@ -1141,6 +1145,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>>   		dev_info(pcie->dev,
>>   			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>>   
>> +	/* Default to max latency of 7. */
>> +	pcie->aspm_l1_enter_lat = 7;
>> +	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
>> +	if (!ret) {
>> +		u32 us = DIV_ROUND_UP(val, 1000);
>> +
>> +		pcie->aspm_l1_enter_lat = min_t(u32, order_base_2(us), 7);
>> +	}
>> +
>>   	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
>>   	if (ret < 0) {
>>   		dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
>> -- 
>> 2.34.1
>>

-- 
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