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From: Andrew Lunn <andrew@lunn.ch>
To: Tristram.Ha@microchip.com
Cc: linux@armlinux.org.uk, olteanv@gmail.com,
	Woojung.Huh@microchip.com, hkallweit1@gmail.com,
	maxime.chevallier@bootlin.com, davem@davemloft.net,
	edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
	UNGLinuxDriver@microchip.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [WARNING: ATTACHMENT UNSCANNED]Re: [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip KSZ9477 switch
Date: Fri, 31 Jan 2025 14:35:03 +0100	[thread overview]
Message-ID: <8866e9ba-642c-4b09-a6da-e352936956c5@lunn.ch> (raw)
In-Reply-To: <DM3PR11MB8736A58E065BF24C2CEA5808ECE82@DM3PR11MB8736.namprd11.prod.outlook.com>

> > So I'm going to say it clearly: never operate the link with dis-similar
> > negotiation protocols. Don't operate the link with 1000base-X at one end
> > and Cisco SGMII at the other end. It's wrong. It's incorrect. The
> > configuration words are different formats. The interpretation of the
> > configuration words are different. Don't do it. Am I clear?
> 
> I do not quite follow this.  The link partner is out of control.  The
> cable is a regular Ethernet cable.  It can be plugged into another PHY, a
> 100Mbit switch, and so on.  Currently using 1000Base-T SFP running in
> 1000BASEX mode and 10/100/1000Base-T SFP running in Cisco SGMII mode
> works in establishing network communication.

Russell is talking about PCS to PHY, the signalling over the SERDES
bus. You are talking PHY-to-PHY signalling over the media, 4 pairs of
copper. These are different signalling protocols, code words in the
in-band signalling of the SERDES data stream, and pulses on the
copper.

Russell is saying you should not mix a Cisco SGMII and 1000Base-X
between the PCS and the PHY. The code words are different format,
which might appear to work in some conditions, but in general is
broken. This is why phylink will try to talk to the PHY within the
SFP, and set is host side interface to Cisco SGMII, and configure the
PCS to Cisco SGMII.

> > If it's still that 1000base-X mode to another 1000base-X partner doesn't
> > generate a link-down interrupt, then you will have no option but to use
> > phylink's polling mode for all protocols with this version of XPCS.
> 
> It is always that case when running in 1000BASEX mode using fiber SFP or
> 1000Base-T copper SFP.

So in general, you would not use 1000BaseX between the PCS and the PHY
in the SFP. It gets tricky doing 10/100Mbps. Since 1000BaseX is hard
coded to 1G, there is no in-band signalling to say to the MAC to only
send at 10/100. So the PHY generally has back to back MACs, the host
side running at 1000, and the line side at 10/100, with a packet
buffer in the middle. As the buffer fills up, the host side MAC
generates pause frames to slow down the MAC to stop the buffer
overflowing.

	Andrew

  reply	other threads:[~2025-01-31 13:35 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-28  3:32 [PATCH RFC net-next 0/2] Add SGMII port support to " Tristram.Ha
2025-01-28  3:32 ` [PATCH RFC net-next 1/2] net: pcs: xpcs: Add special code to operate in Microchip " Tristram.Ha
2025-01-28  9:24   ` Russell King (Oracle)
2025-01-28 10:21     ` Vladimir Oltean
2025-01-28 12:33       ` Russell King (Oracle)
2025-01-28 15:23         ` Vladimir Oltean
2025-01-28 16:32           ` Russell King (Oracle)
2025-01-28 18:26             ` Vladimir Oltean
2025-01-29  0:31           ` Tristram.Ha
2025-01-29 21:12             ` Vladimir Oltean
2025-01-29 22:05               ` Russell King (Oracle)
2025-01-29 23:05                 ` Vladimir Oltean
2025-01-30 12:44                   ` Russell King (Oracle)
2025-01-30 17:42                     ` Russell King (Oracle)
2025-01-30  4:50                 ` [WARNING: ATTACHMENT UNSCANNED]Re: " Tristram.Ha
2025-01-30 10:02                   ` Vladimir Oltean
2025-01-30 11:02                     ` Russell King (Oracle)
2025-01-30 11:20                       ` Jose Abreu
2025-01-31 14:36                       ` Jose Abreu
2025-01-31 15:49                         ` Russell King (Oracle)
2025-02-01  1:12                           ` [WARNING: ATTACHMENT UNSCANNED]Re: " Tristram.Ha
2025-02-01  9:20                             ` Russell King (Oracle)
2025-01-31  2:35                     ` Tristram.Ha
2025-01-30 10:15                   ` Russell King (Oracle)
2025-01-31  2:35                     ` Tristram.Ha
2025-01-31 13:35                       ` Andrew Lunn [this message]
2025-02-01  1:11                         ` Tristram.Ha
2025-01-30  4:50               ` Tristram.Ha
2025-01-30  9:59                 ` Russell King (Oracle)
2025-01-31  2:24                   ` Tristram.Ha
2025-01-31  9:43                     ` Russell King (Oracle)
2025-01-30 13:24                 ` Andrew Lunn
2025-01-31  2:21                   ` Tristram.Ha
2025-01-28 12:40       ` Russell King (Oracle)
2025-01-28 13:16   ` Andrew Lunn
2025-01-28 13:39     ` Russell King (Oracle)
2025-01-28 15:43   ` Vladimir Oltean
2025-01-29  0:31     ` Tristram.Ha
2025-01-28  3:32 ` [PATCH RFC net-next 2/2] net: dsa: microchip: Add SGMII port support to " Tristram.Ha
2025-01-28  9:38   ` Russell King (Oracle)

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