From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,
bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <mani@kernel.org>
Subject: Re: [PATCH] PCI: Add quirk to disable ASPM L1 for Sandisk SN740 NVMe SSDs
Date: Thu, 20 Nov 2025 16:50:44 +0100 [thread overview]
Message-ID: <88778660-18de-40a7-83af-41f60334c4cc@oss.qualcomm.com> (raw)
In-Reply-To: <20251120154601.116806-1-mani@kernel.org>
On 11/20/25 4:46 PM, Manivannan Sadhasivam wrote:
> The Sandisk SN740 NVMe SSDs cause below AER errors on the upstream Root
> Port of PCIe controller in Lenovo Thinkpad T14s laptop when ASPM L1 is
^ Microsoft Surface Laptop 7
Konrad
> enabled:
>
> pcieport 0006:00:00.0: AER: Correctable error message received from 0006:01:00.0
> nvme 0006:01:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID)
> nvme 0006:01:00.0: device [15b7:5015] error status/mask=00000001/0000e000
> nvme 0006:01:00.0: [ 0] RxErr
>
> Hence, add a quirk to disable L1 state for this SSD.
>
> Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> drivers/pci/quirks.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 214ed060ca1b..a6f88c5ba2f4 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2525,6 +2525,18 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
> */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
>
> +static void quirk_disable_aspm_l1(struct pci_dev *dev)
> +{
> + pci_info(dev, "Disabling ASPM L1\n");
> + pci_disable_link_state(dev, PCIE_LINK_STATE_L1);
> +}
> +
> +/*
> + * Sandisk SN740 NVMe SSDs cause AER timeout errors on the upstream PCIe Root
> + * Port when ASPM L1 is enabled.
> + */
> +DECLARE_PCI_FIXUP_FINAL(0x15b7, 0x5015, quirk_disable_aspm_l1);
> +
> /*
> * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
> * Link bit cleared after starting the link retrain process to allow this
next prev parent reply other threads:[~2025-11-20 15:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 15:46 Manivannan Sadhasivam
2025-11-20 15:50 ` Konrad Dybcio [this message]
2025-11-20 16:04 ` Manivannan Sadhasivam
2025-11-20 16:04 ` Lukas Wunner
2025-11-20 16:07 ` Manivannan Sadhasivam
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