From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
To: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>,
amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org,
daniel.lezcano@linaro.org
Cc: rui.zhang@intel.com, lukasz.luba@arm.com,
david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org,
stefan.schmidt@linaro.org, quic_tsoni@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org,
dmitry.baryshkov@oss.qualcomm.com
Subject: Re: [PATCH v4 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required
Date: Thu, 29 May 2025 11:34:27 +0100 [thread overview]
Message-ID: <895a0004-04df-4b7e-9855-bc0033ca650b@linaro.org> (raw)
In-Reply-To: <20250528235026.4171109-2-anjelique.melendez@oss.qualcomm.com>
On 29/05/2025 00:50, Anjelique Melendez wrote:
> From: David Collins <david.collins@oss.qualcomm.com>
>
> Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature
> stage 2 automatic PMIC partial shutdown to be enabled in order to
stage 2 should be hyphenated to stage-2
> avoid repeated faults in the event of reaching over-temperature
> stage 3. Modify the stage 2 shutdown control logic to ensure that
> stage 2 shutdown is enabled on all affected PMICs. Read the
> digital major and minor revision registers to identify these
> PMICs.
>
> Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
> ---
> drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++--
> 1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> index a81e7d6e865f..47248a843591 100644
> --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
Should have the year in it.
grep -r Copyright * | grep Qualcomm
> */
>
> #include <linux/bitops.h>
> @@ -16,6 +17,7 @@
>
> #include "../thermal_hwmon.h"
>
> +#define QPNP_TM_REG_DIG_MINOR 0x00
> #define QPNP_TM_REG_DIG_MAJOR 0x01
> #define QPNP_TM_REG_TYPE 0x04
> #define QPNP_TM_REG_SUBTYPE 0x05
> @@ -78,6 +80,7 @@ struct qpnp_tm_chip {
> /* protects .thresh, .stage and chip registers */
> struct mutex lock;
> bool initialized;
> + bool require_s2_shutdown;
>
> struct iio_channel *adc;
> const long (*temp_map)[THRESH_COUNT][STAGE_COUNT];
> @@ -255,7 +258,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
>
> skip:
> reg |= chip->thresh;
> - if (disable_s2_shutdown)
> + if (disable_s2_shutdown && !chip->require_s2_shutdown)
> reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
>
> return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
> @@ -350,8 +353,8 @@ static int qpnp_tm_probe(struct platform_device *pdev)
> {
> struct qpnp_tm_chip *chip;
> struct device_node *node;
> - u8 type, subtype, dig_major;
> - u32 res;
> + u8 type, subtype, dig_major, dig_minor;
> + u32 res, dig_revision;
> int ret, irq;
>
> node = pdev->dev.of_node;
> @@ -402,6 +405,12 @@ static int qpnp_tm_probe(struct platform_device *pdev)
> return dev_err_probe(&pdev->dev, ret,
> "could not read dig_major\n");
>
> + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "could not read dig_minor\n");
> + return ret;
> + }
> +
> if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
> && subtype != QPNP_TM_SUBTYPE_GEN2)) {
> dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
> @@ -415,6 +424,23 @@ static int qpnp_tm_probe(struct platform_device *pdev)
> else
> chip->temp_map = &temp_map_gen1;
>
> + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
> + dig_revision = (dig_major << 8) | dig_minor;
> + /*
> + * Check if stage 2 automatic partial shutdown must remain
> + * enabled to avoid potential repeated faults upon reaching
> + * over-temperature stage 3.
> + */
> + switch (dig_revision) {
> + case 0x0001:
> + case 0x0002:
> + case 0x0100:
> + case 0x0101:
> + chip->require_s2_shutdown = true;
> + break;
> + }
> + }
> +
> /*
> * Register the sensor before initializing the hardware to be able to
> * read the trip points. get_temp() returns the default temperature
> --
> 2.34.1
>
>
---
bod
next prev parent reply other threads:[~2025-05-29 10:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 23:50 [PATCH v4 0/5] thermal: qcom-spmi-temp-alarm: Add support for new TEMP_ALARM subtypes Anjelique Melendez
2025-05-28 23:50 ` [PATCH v4 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Anjelique Melendez
2025-05-29 10:34 ` Bryan O'Donoghue [this message]
2025-06-03 10:50 ` Dmitry Baryshkov
2025-05-28 23:50 ` [PATCH v4 2/5] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Anjelique Melendez
2025-05-28 23:50 ` [PATCH v4 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Anjelique Melendez
2025-05-29 10:48 ` Bryan O'Donoghue
2025-05-28 23:50 ` [PATCH v4 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Anjelique Melendez
2025-05-29 10:59 ` Bryan O'Donoghue
2025-05-28 23:50 ` [PATCH v4 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE " Anjelique Melendez
2025-06-03 10:51 ` Dmitry Baryshkov
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