* Re: [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed
@ 2026-02-18 16:13 Billy Tsai
0 siblings, 0 replies; 4+ messages in thread
From: Billy Tsai @ 2026-02-18 16:13 UTC (permalink / raw)
To: Linus Walleij
Cc: Tony Lindgren, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Bartosz Golaszewski, patrickw3,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-aspeed, BMC-SW
Hi Krzysztof,
Thanks for the detailed review.
You are right regarding the example – it is not valid and would
trigger schema warnings. I should have tested it more thoroughly.
I will improve my testing workflow for future bindings.
Before sending the next revision, I will run:
make dt_binding_check
without constraining the schema selection, and ensure that no new
warnings are introduced by the patches.
However, based on further feedback from Linus,
I will change direction and drop the generic "pinctrl-packed" binding.
Instead, I will implement an AST2700-specific driver using static SoC
data and reuse the existing standard pinmux and pin configuration
bindings. This should address your concern about the binding being
too generic and introducing unnecessary custom properties.
Hi Linus,
Based on your feedback perhaps introducing a new generic
"pinctrl-packed" binding is not justified at this stage.
Instead, I plan to:
- Drop the generic pinctrl-packed binding.
- The implementation primarily comes down to
describing the pin-to-register-field ordering and the
value-to-function mapping in static SoC data and the rest of
the driver will rely on the generic pinctrl APIs/existing pinctrl-packed code.
- Name the driver "pinctrl-aspeed-ast2700-soc1".
- Reuse the existing standard pinmux and pin configuration
bindings (pinmux-node.yaml and pincfg-node.yaml),
without introducing any custom DT properties.
- Hard-code the function mask and field width in the driver,
since they are fixed by the AST2700 hardware
Thanks
Best regards,
Billy Tsai
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH RFC 0/2] pinctrl: add syscon-backed packed-field pinctrl driver and DT bindings
@ 2026-02-13 8:17 Billy Tsai
2026-02-13 8:17 ` [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed Billy Tsai
0 siblings, 1 reply; 4+ messages in thread
From: Billy Tsai @ 2026-02-13 8:17 UTC (permalink / raw)
To: Linus Walleij, Tony Lindgren, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Bartosz Golaszewski
Cc: patrickw3, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, linux-aspeed, BMC-SW, Billy Tsai
This work follows earlier review discussions around extending
pinctrl-single for bit-per-mux / packed-field controllers. Based on
feedback from Linus Walleij and Tony Lindgren, the direction was changed
towards introducing a separate targeted driver instead of further
increasing the complexity of pinctrl-single.
The prior pinctrl-single series is at:
https://lore.kernel.org/all/20260123-upstream_pinctrl_single-v2-0-40f8063cc5a2@aspeedtech.com/
This series is a replacement of that approach., targeted pinctrl driver
for controllers where pinmux and/or pin configuration are represented as
fixed-width fields packed sequentially within shared registers
(packed-field / bit-per-pin style controllers).
Although pinctrl-single contains support for some bit-per-mux use cases,
it was originally designed around direct MMIO ownership and has grown
in complexity over time. For SoCs where the pin controller lives inside
a larger SCU/syscon register block, using syscon + regmap-mmio provides
a clearer ownership model and naturally avoids MMIO resource conflicts.
The new driver is designed to be instantiated as a subnode of a syscon
device (e.g. SCU). It obtains a regmap from the parent and uses the
child node 'reg' as a window into the syscon register space.
This series includes:
1. A generic Devicetree binding for packed-field pin controllers.
2. The new pinctrl-packed driver (derived from pinctrl-single).
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Billy Tsai (2):
dt-bindings: pinctrl: Add pinctrl-packed
pinctrl: add syscon-backed packed-field pin controller driver
.../bindings/pinctrl/pinctrl-packed.yaml | 166 +++
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-packed.c | 1168 ++++++++++++++++++++
4 files changed, 1348 insertions(+)
---
base-commit: ea24857a76ad90632f86f1e8c8465f96c9f2e407
change-id: 20260211-pinctrl-single-bit-da213f282c95
Best regards,
--
Billy Tsai <billy_tsai@aspeedtech.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed
2026-02-13 8:17 [PATCH RFC 0/2] pinctrl: add syscon-backed packed-field pinctrl driver and DT bindings Billy Tsai
@ 2026-02-13 8:17 ` Billy Tsai
2026-02-13 9:57 ` Krzysztof Kozlowski
2026-02-13 13:47 ` Linus Walleij
0 siblings, 2 replies; 4+ messages in thread
From: Billy Tsai @ 2026-02-13 8:17 UTC (permalink / raw)
To: Linus Walleij, Tony Lindgren, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Bartosz Golaszewski
Cc: patrickw3, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, linux-aspeed, BMC-SW, Billy Tsai
Add a Devicetree binding for a generic pin controller where pinmux and/or
pin configuration are represented as fixed-width fields packed
sequentially within shared registers.
The binding targets controllers that are typically exposed as subnodes of
a syscon node and accessed via regmap-mmio through the parent.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../bindings/pinctrl/pinctrl-packed.yaml | 166 +++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml
new file mode 100644
index 000000000000..dd01ba2fed71
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-packed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Pin Controller with Packed-Field Registers
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description:
+ This binding describes pin controller hardware where pinmux and/or
+ pin configuration fields are represented as fixed-width fields packed
+ sequentially within shared registers.
+
+ Such controllers are commonly embedded within a larger system control
+ unit (SCU) register block and may be exposed as subnodes of a syscon
+ device.
+
+ Conceptually, this model is related to the pinctrl-single binding,
+ but instead of describing individual register offsets via
+ <offset, value, mask> tuples, the hardware provides fixed-width,
+ per-pin fields packed linearly within shared registers.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - pinctrl-packed
+ - pinconf-packed
+
+ reg:
+ maxItems: 1
+
+ '#pinctrl-cells':
+ description:
+ The pinctrl provider uses standard state nodes referenced by pinctrl-N
+ properties; consumers do not pass per-pin arguments via phandle.
+ const: 1
+
+ pinctrl-packed,function-mask:
+ description: Mask of the allowed register bits for a single pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ pinctrl-packed,gpio-range:
+ description: Optional list of pin base, nr pins & gpio function.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of a gpio-range node
+ - description: pin base
+ - description: number of pins
+ - description: gpio function
+
+patternProperties:
+ '-pins(-[0-9]+)?$|-pin$':
+ type: object
+ additionalProperties: false
+
+ properties:
+ pinctrl-packed,pins:
+ description: Array of pin index and function selector pairs.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ pinctrl-packed,bias-pullup:
+ description: Optional bias pull-up configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 4
+ items:
+ - description: Input value.
+ - description: Enabled pull-up bits.
+ - description: Disabled pull-up bits.
+ - description: Pull-up mask.
+ additionalItems: false
+
+ pinctrl-packed,bias-pulldown:
+ description: Optional bias pull-down configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 4
+ items:
+ - description: Input value.
+ - description: Enabled pull-down bits.
+ - description: Disabled pull-down bits.
+ - description: Pull-down mask.
+ additionalItems: false
+
+ pinctrl-packed,drive-strength:
+ description: Optional drive strength configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ items:
+ - description: Drive strength value.
+ - description: Drive strength mask.
+ additionalItems: false
+
+ pinctrl-packed,input-schmitt:
+ description: Optional input Schmitt trigger configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ items:
+ - description: Schmitt trigger value.
+ - description: Schmitt trigger mask.
+ additionalItems: false
+
+ pinctrl-packed,input-schmitt-enable:
+ description: Optional input Schmitt enable configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 4
+ items:
+ - description: Input value.
+ - description: Enable bits.
+ - description: Disable bits.
+ - description: Schmitt mask.
+ additionalItems: false
+
+ pinctrl-packed,low-power-mode:
+ description: Optional low power mode configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ items:
+ - description: Low power value.
+ - description: Low power mask.
+ additionalItems: false
+
+ pinctrl-packed,slew-rate:
+ description: Optional slew rate configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ items:
+ - description: Slew rate value.
+ - description: Slew rate mask.
+ additionalItems: false
+
+required:
+ - compatible
+ - reg
+ - "#pinctrl-cells"
+ - pinctrl-packed,function-mask
+
+additionalProperties: false
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+examples:
+ - |
+ syscon@0 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pinctrl@400 {
+ compatible = "pinctrl-packed";
+ reg = <0x400 0x80>;
+ #pinctrl-cells = <1>;
+ pinctrl-packed,function-mask = <0xf>;
+
+ uart0-pins {
+ /* <pin_index function_select> pairs */
+ pinctrl-packed,pins = <0 2>, <1 2>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed
2026-02-13 8:17 ` [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed Billy Tsai
@ 2026-02-13 9:57 ` Krzysztof Kozlowski
2026-02-13 13:47 ` Linus Walleij
1 sibling, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2026-02-13 9:57 UTC (permalink / raw)
To: Billy Tsai, Linus Walleij, Tony Lindgren, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Bartosz Golaszewski
Cc: patrickw3, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, linux-aspeed, BMC-SW
On 13/02/2026 09:17, Billy Tsai wrote:
> Add a Devicetree binding for a generic pin controller where pinmux and/or
> pin configuration are represented as fixed-width fields packed
> sequentially within shared registers.
>
> The binding targets controllers that are typically exposed as subnodes of
> a syscon node and accessed via regmap-mmio through the parent.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../bindings/pinctrl/pinctrl-packed.yaml | 166 +++++++++++++++++++++
> 1 file changed, 166 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml
> new file mode 100644
> index 000000000000..dd01ba2fed71
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/pinctrl-packed.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Generic Pin Controller with Packed-Field Registers
> +
> +maintainers:
> + - Billy Tsai <billy_tsai@aspeedtech.com>
> +
> +description:
> + This binding describes pin controller hardware where pinmux and/or
> + pin configuration fields are represented as fixed-width fields packed
> + sequentially within shared registers.
> +
> + Such controllers are commonly embedded within a larger system control
> + unit (SCU) register block and may be exposed as subnodes of a syscon
> + device.
> +
> + Conceptually, this model is related to the pinctrl-single binding,
> + but instead of describing individual register offsets via
> + <offset, value, mask> tuples, the hardware provides fixed-width,
> + per-pin fields packed linearly within shared registers.
Why this cannot be part of pinctrl-single then? Why all these properties
are needed? I imagine that you need them to customize the generic
binding to your device and that would be counter argument - generic
bindings are too generic so people need to grow them with hundreds
properties (see the very simple binding of simple audio card).
> +
> +properties:
> + compatible:
> + oneOf:
Drop oneOf
> + - enum:
> + - pinctrl-packed
> + - pinconf-packed
> +
> + reg:
> + maxItems: 1
> +
> + '#pinctrl-cells':
> + description:
> + The pinctrl provider uses standard state nodes referenced by pinctrl-N
> + properties; consumers do not pass per-pin arguments via phandle.
> + const: 1
> +
> + pinctrl-packed,function-mask:
> + description: Mask of the allowed register bits for a single pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + pinctrl-packed,gpio-range:
> + description: Optional list of pin base, nr pins & gpio function.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of a gpio-range node
> + - description: pin base
> + - description: number of pins
> + - description: gpio function
> +
> +patternProperties:
> + '-pins(-[0-9]+)?$|-pin$':
> + type: object
> + additionalProperties: false
> +
> + properties:
> + pinctrl-packed,pins:
No, use standard pinctrl properties.
> + description: Array of pin index and function selector pairs.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> + pinctrl-packed,bias-pullup:
> + description: Optional bias pull-up configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 4
> + items:
> + - description: Input value.
> + - description: Enabled pull-up bits.
> + - description: Disabled pull-up bits.
> + - description: Pull-up mask.
> + additionalItems: false
> +
> + pinctrl-packed,bias-pulldown:
> + description: Optional bias pull-down configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 4
> + items:
> + - description: Input value.
> + - description: Enabled pull-down bits.
> + - description: Disabled pull-down bits.
> + - description: Pull-down mask.
> + additionalItems: false
> +
> + pinctrl-packed,drive-strength:
> + description: Optional drive strength configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 2
> + items:
> + - description: Drive strength value.
> + - description: Drive strength mask.
> + additionalItems: false
> +
> + pinctrl-packed,input-schmitt:
> + description: Optional input Schmitt trigger configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 2
> + items:
> + - description: Schmitt trigger value.
> + - description: Schmitt trigger mask.
> + additionalItems: false
> +
> + pinctrl-packed,input-schmitt-enable:
> + description: Optional input Schmitt enable configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 4
> + items:
> + - description: Input value.
> + - description: Enable bits.
> + - description: Disable bits.
> + - description: Schmitt mask.
> + additionalItems: false
> +
> + pinctrl-packed,low-power-mode:
> + description: Optional low power mode configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 2
> + items:
> + - description: Low power value.
> + - description: Low power mask.
> + additionalItems: false
> +
> + pinctrl-packed,slew-rate:
> + description: Optional slew rate configuration.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + maxItems: 2
> + items:
> + - description: Slew rate value.
> + - description: Slew rate mask.
> + additionalItems: false
> +
> +required:
> + - compatible
> + - reg
> + - "#pinctrl-cells"
> + - pinctrl-packed,function-mask
> +
> +additionalProperties: false
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +examples:
> + - |
> + syscon@0 {
> + compatible = "syscon", "simple-mfd";
This is not allowed and you will have warnings here, which means you did
not test the binding correctly (completely). Not even needed here, drop
entire node.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed
2026-02-13 8:17 ` [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed Billy Tsai
2026-02-13 9:57 ` Krzysztof Kozlowski
@ 2026-02-13 13:47 ` Linus Walleij
1 sibling, 0 replies; 4+ messages in thread
From: Linus Walleij @ 2026-02-13 13:47 UTC (permalink / raw)
To: Billy Tsai
Cc: Tony Lindgren, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Bartosz Golaszewski, patrickw3,
linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-aspeed, BMC-SW
Hi Billy,
thanks for your patch!
This approach is better than trying to extend pinctrl-single in my
opinion, but it has a bit of road to cover.
On Fri, Feb 13, 2026 at 9:18 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote:
> Add a Devicetree binding for a generic pin controller where pinmux and/or
> pin configuration are represented as fixed-width fields packed
> sequentially within shared registers.
>
> The binding targets controllers that are typically exposed as subnodes of
> a syscon node and accessed via regmap-mmio through the parent.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
(...)
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - pinctrl-packed
> + - pinconf-packed
Why do you need two? Can't you just use one, pinctrl-packed.
> + pinctrl-packed,function-mask:
> + description: Mask of the allowed register bits for a single pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
To me this could be static data in the driver but I guess the whole
point is to do what pinctrl-single is doing and store all of this
information in the device tree, because reasons.
I guess the DT binding maintainers need to decide on this and
also what to name it.
> + pinctrl-packed,gpio-range:
> + description: Optional list of pin base, nr pins & gpio function.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle of a gpio-range node
> + - description: pin base
> + - description: number of pins
> + - description: gpio function
Just use the standard gpio-range.
> +patternProperties:
> + '-pins(-[0-9]+)?$|-pin$':
> + type: object
> + additionalProperties: false
> + properties:
> + pinctrl-packed,pins:
> + description: Array of pin index and function selector pairs.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
Just use pinmux = <...>; from pinmux-node.yaml
(make sure to use the ref include.)
> + pinctrl-packed,bias-pullup:
> + pinctrl-packed,bias-pulldown:
> + pinctrl-packed,drive-strength:
> + pinctrl-packed,input-schmitt:
> + pinctrl-packed,input-schmitt-enable:
> + pinctrl-packed,low-power-mode:
> + pinctrl-packed,slew-rate:
Just use the existing configs from
pincfg-node.yaml and abstain from any new
inventions here.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-02-13 8:17 ` [PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed Billy Tsai
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