* [PATCH v2 1/4] clk: qcom: gcc-glymur: Mark GCC AV1E AHB and XO clocks as critical
2026-11-04 5:07 [PATCH v2 0/4] clk: qcom: Add support for Glymur AV1E clock controller Jagadeesh Kona
@ 2026-11-04 5:07 ` Jagadeesh Kona
2026-11-04 5:07 ` [PATCH v2 2/4] dt-bindings: clock: qcom: Add AV1E clock controller on Glymur SoC Jagadeesh Kona
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Jagadeesh Kona @ 2026-11-04 5:07 UTC (permalink / raw)
To: Bjorn Andersson, Abel Vesa, Stephen Boyd, Brian Masney,
Jerome Brunet, Dmitry Baryshkov, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jagadeesh Kona, Konrad Dybcio
Cc: Ajit Pandey, Imran Shaik, Taniya Das, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Jagadeesh Kona, Abel Vesa
The GCC AV1E AHB and XO clocks are required for AV1ECC register access.
Hence remove their clock modelling and add them to the GCC critical
clock list.
Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller")
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-glymur.c | 32 ++------------------------------
1 file changed, 2 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c
index be18a555fe314a41e5335ce8cc100ae8ed226ccb..9418a9b2bbde4be8a28b6ba4405baa780de654e8 100644
--- a/drivers/clk/qcom/gcc-glymur.c
+++ b/drivers/clk/qcom/gcc-glymur.c
@@ -3373,21 +3373,6 @@ static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
},
};
-static struct clk_branch gcc_av1e_ahb_clk = {
- .halt_reg = 0x9b02c,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x9b02c,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x9b02c,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_av1e_ahb_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_av1e_axi_clk = {
.halt_reg = 0x9b030,
.halt_check = BRANCH_HALT_SKIP,
@@ -3403,19 +3388,6 @@ static struct clk_branch gcc_av1e_axi_clk = {
},
};
-static struct clk_branch gcc_av1e_xo_clk = {
- .halt_reg = 0x9b044,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x9b044,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_av1e_xo_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x34038,
.halt_check = BRANCH_HALT_VOTED,
@@ -7915,9 +7887,7 @@ static struct clk_regmap *gcc_glymur_clocks[] = {
[GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
[GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
- [GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
[GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
- [GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
@@ -8483,6 +8453,8 @@ static const u32 gcc_glymur_critical_cbcrs[] = {
0x32058, /* GCC_VIDEO_XO_CLK */
0x9b004, /* GCC_EVA_AHB_CLK */
0x9b024, /* GCC_EVA_XO_CLK */
+ 0x9b02c, /* GCC_AV1E_AHB_CLK */
+ 0x9b044, /* GCC_AV1E_XO_CLK */
};
static const struct regmap_config gcc_glymur_regmap_config = {
--
2.56.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 3/4] clk: qcom: av1ecc-glymur: Add AV1E clock controller driver
2026-11-04 5:07 [PATCH v2 0/4] clk: qcom: Add support for Glymur AV1E clock controller Jagadeesh Kona
2026-11-04 5:07 ` [PATCH v2 1/4] clk: qcom: gcc-glymur: Mark GCC AV1E AHB and XO clocks as critical Jagadeesh Kona
2026-11-04 5:07 ` [PATCH v2 2/4] dt-bindings: clock: qcom: Add AV1E clock controller on Glymur SoC Jagadeesh Kona
@ 2026-11-04 5:07 ` Jagadeesh Kona
2026-11-05 13:16 ` Konrad Dybcio
2026-11-04 5:07 ` [PATCH v2 4/4] arm64: dts: qcom: glymur: Add support for AV1E clock controller Jagadeesh Kona
3 siblings, 1 reply; 6+ messages in thread
From: Jagadeesh Kona @ 2026-11-04 5:07 UTC (permalink / raw)
To: Bjorn Andersson, Abel Vesa, Stephen Boyd, Brian Masney,
Jerome Brunet, Dmitry Baryshkov, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jagadeesh Kona, Konrad Dybcio
Cc: Ajit Pandey, Imran Shaik, Taniya Das, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Jagadeesh Kona
Add support for the AV1 encoder clock controller (AV1ECC) driver
for clients to be able to request for AV1ECC clocks on Qualcomm
Glymur platform.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 11 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/av1ecc-glymur.c | 393 +++++++++++++++++++++++++++++++++++++++
3 files changed, 405 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 27d0ab24d50a4ca5587ed8d6085c4d6fcd57eb8c..94f3445f6bd0ecd297d83b5804ff0e4433d48261 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -69,6 +69,17 @@ config CLK_ELIZA_TCSRCC
Support for the TCSR clock controller on Eliza devices.
Say Y if you want to use peripheral devices such as USB/PCIe/UFS.
+config CLK_GLYMUR_AV1ECC
+ tristate "Glymur AV1E Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select CLK_GLYMUR_GCC
+ default m if ARCH_QCOM
+ help
+ Support for the video AV1 encoder clock controller on
+ Qualcomm Technologies, Inc. Glymur devices.
+ Say Y if you want to support functionality such as AV1
+ encoding.
+
config CLK_GLYMUR_CAMCC
tristate "Glymur Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6affb5073f269d18f1b78d6c7f92e14baeade1e5..61d4efb7547146544902dddf52e4853d073d5467 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
+obj-$(CONFIG_CLK_GLYMUR_AV1ECC) += av1ecc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
diff --git a/drivers/clk/qcom/av1ecc-glymur.c b/drivers/clk/qcom/av1ecc-glymur.c
new file mode 100644
index 0000000000000000000000000000000000000000..e59c8ecef44543f6c2c79f3f44f838fca8c142ab
--- /dev/null
+++ b/drivers/clk/qcom/av1ecc-glymur.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,glymur-av1ecc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_IFACE,
+};
+
+enum {
+ P_AV1E_CC_PLL0_OUT_EVEN,
+ P_AV1E_CC_PLL0_OUT_MAIN,
+ P_AV1E_CC_PLL0_OUT_ODD,
+ P_BI_TCXO,
+};
+
+static const struct pll_vco taycan_eko_t_vco[] = {
+ { 249600000, 2500000000, 0 },
+};
+
+/* 600.0 MHz Configuration */
+static const struct alpha_pll_config av1e_cc_pll0_config = {
+ .l = 0x1f,
+ .cal_l = 0x48,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x25c400e7,
+ .config_ctl_hi_val = 0x0a8060e0,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000008,
+ .user_ctl_hi_val = 0x00000002,
+};
+
+static struct clk_alpha_pll av1e_cc_pll0 = {
+ .offset = 0x0,
+ .config = &av1e_cc_pll0_config,
+ .vco_table = taycan_eko_t_vco,
+ .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_taycan_eko_t_ops,
+ },
+ },
+};
+
+static const struct parent_map av1e_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_AV1E_CC_PLL0_OUT_MAIN, 1 },
+ { P_AV1E_CC_PLL0_OUT_ODD, 2 },
+ { P_AV1E_CC_PLL0_OUT_EVEN, 3 },
+};
+
+static const struct clk_parent_data av1e_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &av1e_cc_pll0.clkr.hw },
+ { .hw = &av1e_cc_pll0.clkr.hw },
+ { .hw = &av1e_cc_pll0.clkr.hw },
+};
+
+static const struct parent_map av1e_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data av1e_cc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct freq_tbl ftbl_av1e_cc_av1e_core_clk_src[] = {
+ F(300000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(400000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(600000000, P_AV1E_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 av1e_cc_av1e_core_clk_src = {
+ .cmd_rcgr = 0x4018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = av1e_cc_parent_map_0,
+ .freq_tbl = ftbl_av1e_cc_av1e_core_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_core_clk_src",
+ .parent_data = av1e_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(av1e_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_av1e_cc_av1e_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 av1e_cc_av1e_xo_clk_src = {
+ .cmd_rcgr = 0x601c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = av1e_cc_parent_map_1,
+ .freq_tbl = ftbl_av1e_cc_av1e_xo_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_xo_clk_src",
+ .parent_data = av1e_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(av1e_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div av1e_cc_av1e_noc_ahb_div_clk_src = {
+ .reg = 0x5020,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_noc_ahb_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch av1e_cc_ahb_clk = {
+ .halt_reg = 0x6000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x6000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_core_apb_clk = {
+ .halt_reg = 0x4044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_core_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_core_axi_clk = {
+ .halt_reg = 0x4040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_core_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_core_clk = {
+ .halt_reg = 0x4030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_gdsc_noc_ahb_clk = {
+ .halt_reg = 0x5024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_gdsc_noc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_noc_ahb_clk = {
+ .halt_reg = 0x5028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_noc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_noc_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_noc_core_axi_clk = {
+ .halt_reg = 0x5004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_noc_core_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch av1e_cc_av1e_noc_xo_clk = {
+ .halt_reg = 0x6038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "av1e_cc_av1e_noc_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &av1e_cc_av1e_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc av1e_cc_core_gdsc = {
+ .gdscr = 0x4004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "av1e_cc_core_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *av1e_cc_glymur_clocks[] = {
+ [AV1E_CC_AHB_CLK] = &av1e_cc_ahb_clk.clkr,
+ [AV1E_CC_AV1E_CORE_APB_CLK] = &av1e_cc_av1e_core_apb_clk.clkr,
+ [AV1E_CC_AV1E_CORE_AXI_CLK] = &av1e_cc_av1e_core_axi_clk.clkr,
+ [AV1E_CC_AV1E_CORE_CLK] = &av1e_cc_av1e_core_clk.clkr,
+ [AV1E_CC_AV1E_CORE_CLK_SRC] = &av1e_cc_av1e_core_clk_src.clkr,
+ [AV1E_CC_AV1E_GDSC_NOC_AHB_CLK] = &av1e_cc_av1e_gdsc_noc_ahb_clk.clkr,
+ [AV1E_CC_AV1E_NOC_AHB_CLK] = &av1e_cc_av1e_noc_ahb_clk.clkr,
+ [AV1E_CC_AV1E_NOC_AHB_DIV_CLK_SRC] = &av1e_cc_av1e_noc_ahb_div_clk_src.clkr,
+ [AV1E_CC_AV1E_NOC_CORE_AXI_CLK] = &av1e_cc_av1e_noc_core_axi_clk.clkr,
+ [AV1E_CC_AV1E_NOC_XO_CLK] = &av1e_cc_av1e_noc_xo_clk.clkr,
+ [AV1E_CC_AV1E_XO_CLK_SRC] = &av1e_cc_av1e_xo_clk_src.clkr,
+ [AV1E_CC_PLL0] = &av1e_cc_pll0.clkr,
+};
+
+static struct gdsc *av1e_cc_glymur_gdscs[] = {
+ [AV1E_CC_CORE_GDSC] = &av1e_cc_core_gdsc,
+};
+
+static const struct qcom_reset_map av1e_cc_glymur_resets[] = {
+ [AV1E_CC_AV1E_CORE_AXI_CLK_ARES] = { 0x4040, 2 },
+ [AV1E_CC_AV1E_CORE_CLK_ARES] = { 0x4030, 2 },
+ [AV1E_CC_AV1E_GDSC_NOC_AHB_CLK_ARES] = { 0x5024, 2 },
+ [AV1E_CC_AV1E_NOC_CORE_AXI_CLK_ARES] = { 0x5004, 2 },
+ [AV1E_CC_AV1E_NOC_XO_CLK_ARES] = { 0x6038, 2 },
+ [AV1E_CC_CORE_BCR] = { 0x4000 },
+ [AV1E_CC_NOC_BCR] = { 0x5000 },
+};
+
+static struct clk_alpha_pll *av1e_cc_glymur_plls[] = {
+ &av1e_cc_pll0,
+};
+
+static const u32 av1e_cc_glymur_critical_cbcrs[] = {
+ 0x6034, /* AV1E_CC_AV1E_CC_XO_CLK */
+ 0x6054, /* AV1E_CC_SLEEP_CLK */
+};
+
+static const struct regmap_config av1e_cc_glymur_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xa01c,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_driver_data av1e_cc_glymur_driver_data = {
+ .alpha_plls = av1e_cc_glymur_plls,
+ .num_alpha_plls = ARRAY_SIZE(av1e_cc_glymur_plls),
+ .clk_cbcrs = av1e_cc_glymur_critical_cbcrs,
+ .num_clk_cbcrs = ARRAY_SIZE(av1e_cc_glymur_critical_cbcrs),
+};
+
+static const struct qcom_cc_desc av1e_cc_glymur_desc = {
+ .config = &av1e_cc_glymur_regmap_config,
+ .clks = av1e_cc_glymur_clocks,
+ .num_clks = ARRAY_SIZE(av1e_cc_glymur_clocks),
+ .resets = av1e_cc_glymur_resets,
+ .num_resets = ARRAY_SIZE(av1e_cc_glymur_resets),
+ .gdscs = av1e_cc_glymur_gdscs,
+ .num_gdscs = ARRAY_SIZE(av1e_cc_glymur_gdscs),
+ .use_rpm = true,
+ .driver_data = &av1e_cc_glymur_driver_data,
+};
+
+static const struct of_device_id av1e_cc_glymur_match_table[] = {
+ { .compatible = "qcom,glymur-av1ecc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, av1e_cc_glymur_match_table);
+
+static int av1e_cc_glymur_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &av1e_cc_glymur_desc);
+}
+
+static struct platform_driver av1e_cc_glymur_driver = {
+ .probe = av1e_cc_glymur_probe,
+ .driver = {
+ .name = "av1ecc-glymur",
+ .of_match_table = av1e_cc_glymur_match_table,
+ },
+};
+
+module_platform_driver(av1e_cc_glymur_driver);
+
+MODULE_DESCRIPTION("QTI AV1ECC Glymur Driver");
+MODULE_LICENSE("GPL");
--
2.56.0
^ permalink raw reply [flat|nested] 6+ messages in thread