Re: [PATCH 1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint

[Krzysztof Kozlowski <krzk@kernel.org>]

On 05/12/2025 13:58, Mrinmay Sarkar wrote:
>>>  1 file changed, 114 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..970f65d46c8e2fa4c44665cb7a346dea1dc9e06a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
>>> @@ -0,0 +1,114 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Qualcomm firmware managed PCIe Endpoint Controller
>>> +
>>> +description:
>>> +  Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys
>>> +  DesignWare PCIe IP which is managed by firmware.
>>> +
>>> +maintainers:
>>> +  - Manivannan Sadhasivam <mani@kernel.org>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: qcom,sa8255p-pcie-ep
>>> +
>>> +  reg:
>>> +    minItems: 6
>>
>> Why is this flexible?
> 
> The reason for `minItems: 6` is that the DMA register space can be
> skipped if DMA is not used.

But the hardware has this anyway, so this must be here. You do not write
bindings depending how drivers use them in your use case.

Either drop minItems (fixed size of array) or provide rationale in terms
of hardware in commit msg.

...


>>> +
>>> +  dma-coherent: true
>>> +
>>> +  num-lanes:
>>> +    default: 2
>>
>> Isn't this deducible from the compatible? Do you have have different
>> PCIe controllers with different lanes?
> 
> SA8255p has 2 pcie controllers(pcie0 and pcie1).
> pcie0 supports 2 lanes, and pcie1 supports 4 lanes.

That's ok, thanks.


Best regards,
Krzysztof