Re: [PATCH 1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint

[Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>]

On Fri, Dec 5, 2025 at 2:40 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Wed, Dec 03, 2025 at 06:56:47PM +0530, Mrinmay Sarkar wrote:
> > Document the required configuration to enable the PCIe Endpoint controller
> > on SA8255p which is managed by firmware using power-domain based handling.
> >
> > Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
> > ---
> >  .../bindings/pci/qcom,pcie-ep-sa8255p.yaml         | 114 +++++++++++++++++++++
>
> Filename must match the compatible. In your case, the filename is
> correct but you wanted old format for the compatible (so compatible
> should be rewritten to match filename).

Thanks Krzysztof for the review.
I will fix the compatible string to match the filename (`qcom,pcie-ep-sa8255p`).

>
> >  1 file changed, 114 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..970f65d46c8e2fa4c44665cb7a346dea1dc9e06a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
> > @@ -0,0 +1,114 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm firmware managed PCIe Endpoint Controller
> > +
> > +description:
> > +  Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys
> > +  DesignWare PCIe IP which is managed by firmware.
> > +
> > +maintainers:
> > +  - Manivannan Sadhasivam <mani@kernel.org>
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,sa8255p-pcie-ep
> > +
> > +  reg:
> > +    minItems: 6
>
> Why is this flexible?

The reason for `minItems: 6` is that the DMA register space can be
skipped if DMA is not used.

>
> > +    items:
> > +      - description: Qualcomm-specific PARF configuration registers
> > +      - description: DesignWare PCIe registers
> > +      - description: External local bus interface registers
> > +      - description: Address Translation Unit (ATU) registers
> > +      - description: Memory region used to map remote RC address space
> > +      - description: BAR memory region
> > +      - description: DMA register space
> > +
> > +  reg-names:
> > +    minItems: 6
> > +    items:
> > +      - const: parf
> > +      - const: dbi
> > +      - const: elbi
> > +      - const: atu
> > +      - const: addr_space
> > +      - const: mmio
> > +      - const: dma
> > +
> > +  interrupts:
> > +    minItems: 2
>
> And this/

Similarly, DMA interrupt can be skipped if DMA is not used.

>
> > +    items:
> > +      - description: PCIe Global interrupt
> > +      - description: PCIe Doorbell interrupt
> > +      - description: DMA interrupt
> > +
> > +  interrupt-names:
> > +    minItems: 2
> > +    items:
> > +      - const: global
> > +      - const: doorbell
> > +      - const: dma
> > +
> > +  iommus:
> > +    maxItems: 1
> > +
> > +  reset-gpios:
> > +    description: GPIO used as PERST# input signal
> > +    maxItems: 1
> > +
> > +  wake-gpios:
> > +    description: GPIO used as WAKE# output signal
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  dma-coherent: true
> > +
> > +  num-lanes:
> > +    default: 2
>
> Isn't this deducible from the compatible? Do you have have different
> PCIe controllers with different lanes?

SA8255p has 2 pcie controllers(pcie0 and pcie1).
pcie0 supports 2 lanes, and pcie1 supports 4 lanes.

-Mrinmay
>
>
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - interrupt-names
> > +  - reset-gpios
> > +  - power-domains
> > +
> > +additionalProperties: false
>
> Best regards,
> Krzysztof
>