[PATCH] media: iris: reset AHB bridge before enabling HW mode

[PATCH] media: iris: reset AHB bridge before enabling HW mode

[Vikash Garodia]

When video power domain is switched from software-controlled mode to
hardware-controlled mode, the core may be powered down without the AHB
bridge going through the required reset sequence. This may leave the
bridge FIFO in a stale state.
Reset the CPU-to-VPU AHB bridge before switching the power domain to
hardware-controlled mode. This ensures that the bridge FIFO are in
reset state before going for mode switch.

Reported-by: Birk Skyum <birk.skyum@pm.me>
Link: https://lore.kernel.org/all/20260913194707.91885-1-birk.skyum@pm.me
Fixes: 95a337f92f0a ("media: iris: switch to hardware mode after firmware boot")
Cc: stable@vger.kernel.org
Co-developed-by: Renjiang Han <renjiang.han@oss.qualcomm.com>
Signed-off-by: Renjiang Han <renjiang.han@oss.qualcomm.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
This is tested on X1E80100, and is applicable to all VPUs.
---
 drivers/media/platform/qcom/iris/iris_vpu_common.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index e4847c1077097160cfc8324e807b4aabd9747812..2ef8004e976e34ac3e5ad1971894253fee77648d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -311,6 +311,11 @@ int iris_vpu_power_on_hw(struct iris_core *core)
 
 int iris_vpu_set_hwmode(struct iris_core *core)
 {
+	writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
+	       core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+	writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+	writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
 	return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
 }
 

---
base-commit: 3d7783543c2646af69ad65825e810060494bea21
change-id: 20260924-vpu_hwmode_fix-e4da1cc447d0

Best regards,
-- 
Vikash Garodia <vikash.garodia@oss.qualcomm.com>

Re: [PATCH] media: iris: reset AHB bridge before enabling HW mode

[Birk Skyum]

This fixes the SID override assertion I reported on the Lenovo Yoga
Slim 7x. The test details are in my reply on the Link: thread.

Tested-by: Birk Skyum <birk.skyum@pm.me> # Lenovo Yoga Slim 7x

Re: [PATCH] media: iris: reset AHB bridge before enabling HW mode

[Vishnu Reddy]

On 9/24/2026 8:00 PM, Vikash Garodia wrote:
> When video power domain is switched from software-controlled mode to
> hardware-controlled mode, the core may be powered down without the AHB
> bridge going through the required reset sequence. This may leave the
> bridge FIFO in a stale state.
> Reset the CPU-to-VPU AHB bridge before switching the power domain to
> hardware-controlled mode. This ensures that the bridge FIFO are in
> reset state before going for mode switch.
>
> Reported-by: Birk Skyum <birk.skyum@pm.me>
> Link: https://lore.kernel.org/all/20260913194707.91885-1-birk.skyum@pm.me
> Fixes: 95a337f92f0a ("media: iris: switch to hardware mode after firmware boot")
> Cc: stable@vger.kernel.org
> Co-developed-by: Renjiang Han <renjiang.han@oss.qualcomm.com>
> Signed-off-by: Renjiang Han <renjiang.han@oss.qualcomm.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> This is tested on X1E80100, and is applicable to all VPUs.
> ---
>  drivers/media/platform/qcom/iris/iris_vpu_common.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index e4847c1077097160cfc8324e807b4aabd9747812..2ef8004e976e34ac3e5ad1971894253fee77648d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -311,6 +311,11 @@ int iris_vpu_power_on_hw(struct iris_core *core)
>  
>  int iris_vpu_set_hwmode(struct iris_core *core)
>  {
> +	writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
> +	       core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
> +	writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
> +	writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
> +
>  	return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
>  }

Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>