Re: [PATCH v5 07/40] x86/resctrl: Add max_bw to struct resctrl_membw

[Reinette Chatre <reinette.chatre@intel.com>]

Hi James,

On 10/4/24 11:03 AM, James Morse wrote:
> __rdt_get_mem_config_amd() and __get_mem_config_intel() both use
> the default_ctrl property as a maximum value. This is because the
> MBA schema works differently between these platforms. Doing this

The schema works differently but they can still use the same property
as maximum, is that a problem?

> complicates determining whether the default_ctrl property belongs
> to the arch code, or can be derived from the schema format.

So instead of Intel and AMD both using default_ctrl as a maximum this patch
introduces a new max_bw with both using that as maximum instead.
Unclear how this change fixes the unclear complication.

> 
> Add a max_bw property for x86 platforms to specify their maximum
> MBA bandwidth. This isn't needed for other schema formats.

It is not clear to me how replacing one value with a new value that is
used in exactly the same way addresses the initial complaint of complication.

> 
> This will allow the default_ctrl to be generated from the schema
> properties when it is needed.
> 
> Signed-off-by: James Morse <james.morse@arm.com>
> Tested-by: Carl Worth <carl@os.amperecomputing.com> # arm64
> Tested-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
> Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
> ---
> Changes since v2:
>  * This patch is new.
> ---
>  arch/x86/kernel/cpu/resctrl/core.c        | 3 +++
>  arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 9 +++++----
>  include/linux/resctrl.h                   | 2 ++
>  3 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index 4c16e58c4a1b..e79807a8f060 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -212,6 +212,7 @@ static bool __get_mem_config_intel(struct rdt_resource *r)
>  	hw_res->num_closid = edx.split.cos_max + 1;
>  	max_delay = eax.split.max_delay + 1;
>  	r->default_ctrl = MAX_MBA_BW;
> +	r->membw.max_bw = MAX_MBA_BW;
>  	r->membw.arch_needs_linear = true;
>  	if (ecx & MBA_IS_LINEAR) {
>  		r->membw.delay_linear = true;
> @@ -248,6 +249,8 @@ static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
>  	cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx);
>  	hw_res->num_closid = edx + 1;
>  	r->default_ctrl = 1 << eax;
> +	r->schema_fmt = RESCTRL_SCHEMA_RANGE;

Stray change?

> +	r->membw.max_bw = 1 << eax;
>  
>  	/* AMD does not use delay */
>  	r->membw.delay_linear = false;
> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> index 8d1bdfe89692..56c41bfd07e4 100644
> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> @@ -57,10 +57,10 @@ static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r)
>  		return false;
>  	}
>  
> -	if ((bw < r->membw.min_bw || bw > r->default_ctrl) &&
> +	if ((bw < r->membw.min_bw || bw > r->membw.max_bw) &&
>  	    !is_mba_sc(r)) {
>  		rdt_last_cmd_printf("MB value %ld out of range [%d,%d]\n", bw,
> -				    r->membw.min_bw, r->default_ctrl);
> +				    r->membw.min_bw, r->membw.max_bw);
>  		return false;
>  	}
>  
> @@ -108,8 +108,9 @@ static int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s,
>   */
>  static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
>  {
> -	unsigned long first_bit, zero_bit, val;
> +	u32 supported_bits = BIT_MASK(r->cache.cbm_len + 1) - 1;

Same issue as V4:
https://lore.kernel.org/all/ca528ebd-fb76-40cd-a495-88c2de443cd8@intel.com/

>  	unsigned int cbm_len = r->cache.cbm_len;
> +	unsigned long first_bit, zero_bit, val;
>  	int ret;
>  
>  	ret = kstrtoul(buf, 16, &val);
> @@ -118,7 +119,7 @@ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
>  		return false;
>  	}
>  
> -	if ((r->cache.min_cbm_bits > 0 && val == 0) || val > r->default_ctrl) {
> +	if ((r->cache.min_cbm_bits > 0 && val == 0) || val > supported_bits) {
>  		rdt_last_cmd_puts("Mask out of range\n");
>  		return false;
>  	}

The above two changes have nothing to do with memory bandwidth. They are unrelated
to the changelog.

> diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h
> index 0f61673c9165..b66cd977b658 100644
> --- a/include/linux/resctrl.h
> +++ b/include/linux/resctrl.h
> @@ -165,6 +165,7 @@ enum membw_throttle_mode {
>  /**
>   * struct resctrl_membw - Memory bandwidth allocation related data
>   * @min_bw:		Minimum memory bandwidth percentage user can request
> + * @max_bw:		Maximum memory bandwidth value, used as the reset value
>   * @bw_gran:		Granularity at which the memory bandwidth is allocated
>   * @delay_linear:	True if memory B/W delay is in linear scale
>   * @arch_needs_linear:	True if we can't configure non-linear resources
> @@ -175,6 +176,7 @@ enum membw_throttle_mode {
>   */
>  struct resctrl_membw {
>  	u32				min_bw;
> +	u32				max_bw;
>  	u32				bw_gran;
>  	u32				delay_linear;
>  	bool				arch_needs_linear;

Reinette