[PATCH v2 0/2] Add device-tree support for CPSW9G on J721E SoC

[PATCH v2 0/2] Add device-tree support for CPSW9G on J721E SoC

[Siddharth Vadapalli]

Hello,

This series adds the device-tree nodes for CPSW9G instance of CPSW
Ethernet Switch on TI's J721E SoC. Additionally, an overlay file is also
added to enable CPSW9G nodes in QSGMII mode with the Add-On J7 QUAD Port
Ethernet expansion QSGMII daughtercard.

---
Changes from v1:
1. Rename node name "mdio_pins_default" to "mdio0-pins-default", since
   node names shouldn't contain underscores.
2. Change node label "mdio_pins_default" to "mdio0_pins_default".

The reason for adding 0 after mdio with the above changes, is to indicate
the association of the cpsw0 instance of CPSW with this instance of MDIO.

v1:
https://lore.kernel.org/r/20230310092804.692303-1-s-vadapalli@ti.com

Siddharth Vadapalli (2):
  arm64: dts: ti: k3-j721e: Add CPSW9G nodes
  arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII
    mode

 arch/arm64/boot/dts/ti/Makefile               |   4 +
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 107 +++++++++++++
 .../dts/ti/k3-j721e-quad-port-eth-exp.dtso    | 148 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e.dtsi          |   1 +
 4 files changed, 260 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso

-- 
2.25.1

[PATCH v2 1/2] arm64: dts: ti: k3-j721e: Add CPSW9G nodes

[Siddharth Vadapalli]

TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external
ports and 1 host port, referred to as CPSW9G.

Add device-tree nodes for CPSW9G and disable it by default. Device-tree
overlays will be used to enable it.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 107 ++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e.dtsi      |   1 +
 2 files changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c935622f0102..1ac7a47fc437 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -61,6 +61,13 @@ serdes_ln_ctrl: mux-controller@4080 {
 				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 		};
 
+		cpsw0_phy_gmii_sel: phy@4044 {
+			compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
+			ti,qsgmii-main-ports = <2>, <2>;
+			reg = <0x4044 0x20>;
+			#phy-cells = <1>;
+		};
+
 		usb_serdes_mux: mux-controller@4000 {
 			compatible = "mmio-mux";
 			#mux-control-cells = <1>;
@@ -404,6 +411,106 @@ cpts@310d0000 {
 		};
 	};
 
+	cpsw0: ethernet@c000000 {
+		compatible = "ti,j721e-cpswxg-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0xc000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
+		clocks = <&k3_clks 19 89>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xca00>,
+		       <&main_udmap 0xca01>,
+		       <&main_udmap 0xca02>,
+		       <&main_udmap 0xca03>,
+		       <&main_udmap 0xca04>,
+		       <&main_udmap 0xca05>,
+		       <&main_udmap 0xca06>,
+		       <&main_udmap 0xca07>,
+		       <&main_udmap 0x4a00>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		status = "disabled";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cpsw0_port1: port@1 {
+				reg = <1>;
+				ti,mac-only;
+				label = "port1";
+			};
+
+			cpsw0_port2: port@2 {
+				reg = <2>;
+				ti,mac-only;
+				label = "port2";
+			};
+
+			cpsw0_port3: port@3 {
+				reg = <3>;
+				ti,mac-only;
+				label = "port3";
+			};
+
+			cpsw0_port4: port@4 {
+				reg = <4>;
+				ti,mac-only;
+				label = "port4";
+			};
+
+			cpsw0_port5: port@5 {
+				reg = <5>;
+				ti,mac-only;
+				label = "port5";
+			};
+
+			cpsw0_port6: port@6 {
+				reg = <6>;
+				ti,mac-only;
+				label = "port6";
+			};
+
+			cpsw0_port7: port@7 {
+				reg = <7>;
+				ti,mac-only;
+				label = "port7";
+			};
+
+			cpsw0_port8: port@8 {
+				reg = <8>;
+				ti,mac-only;
+				label = "port8";
+			};
+		};
+
+		cpsw9g_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x0 0xf00 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 19 89>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,j721e-cpts";
+			reg = <0x0 0x3d000 0x0 0x400>;
+			clocks = <&k3_clks 19 16>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
 	main_crypto: crypto@4e00000 {
 		compatible = "ti,j721e-sa2ul";
 		reg = <0x0 0x4e00000 0x0 0x1200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 6975cae644d9..ddbaa06e21bd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -135,6 +135,7 @@ cbass_main: bus@100000 {
 			 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
 			 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+			 <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
 			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
 			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
 			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
-- 
2.25.1

[PATCH v2 2/2] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode

[Siddharth Vadapalli]

The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode.

Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.

Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile               |   4 +
 .../dts/ti/k3-j721e-quad-port-eth-exp.dtso    | 148 ++++++++++++++++++
 2 files changed, 152 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6acd12409d59..167bcd9b09b7 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -45,3 +45,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+DTC_FLAGS_k3-j721e-common-proc-board += -@
+
+# Device-tree overlays
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-quad-port-eth-exp.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
new file mode 100644
index 000000000000..d7977d16c921
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J721E board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+/ {
+	fragment@102 {
+		target-path = "/";
+		__overlay__ {
+			aliases {
+				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
+				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
+			};
+		};
+	};
+};
+
+&cpsw0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio0_pins_default>;
+};
+
+&cpsw0_port1 {
+	phy-handle = <&cpsw9g_phy0>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+	phy-handle = <&cpsw9g_phy1>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+	phy-handle = <&cpsw9g_phy2>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+	phy-handle = <&cpsw9g_phy3>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw0_port5 {
+	status = "disabled";
+};
+
+&cpsw0_port6 {
+	status = "disabled";
+};
+
+&cpsw0_port7 {
+	status = "disabled";
+};
+
+&cpsw0_port8 {
+	status = "disabled";
+};
+
+&cpsw9g_mdio {
+	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+	reset-post-delay-us = <120000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpsw9g_phy0: ethernet-phy@17 {
+		reg = <17>;
+	};
+	cpsw9g_phy1: ethernet-phy@16 {
+		reg = <16>;
+	};
+	cpsw9g_phy2: ethernet-phy@18 {
+		reg = <18>;
+	};
+	cpsw9g_phy3: ethernet-phy@19 {
+		reg = <19>;
+	};
+};
+
+&exp2 {
+	qsgmii-line-hog {
+		gpio-hog;
+		gpios = <16 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "qsgmii-pwrdn-line";
+	};
+};
+
+&main_pmx0 {
+	mdio0_pins_default: mdio0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
+			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
+		>;
+	};
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
+		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz0 {
+	status = "okay";
+};
+
+&serdes0 {
+	status = "okay";
+
+	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	serdes0_qsgmii_link: phy@1 {
+		reg = <1>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_QSGMII>;
+		resets = <&serdes_wiz0 2>;
+	};
+};
-- 
2.25.1

Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode

[Andrew Davis]

On 3/10/23 4:35 AM, Siddharth Vadapalli wrote:
> The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports
> QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode.
> 
> Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.
> 
> Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
> directly from U-Boot.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>   arch/arm64/boot/dts/ti/Makefile               |   4 +
>   .../dts/ti/k3-j721e-quad-port-eth-exp.dtso    | 148 ++++++++++++++++++
>   2 files changed, 152 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
> 
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 6acd12409d59..167bcd9b09b7 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -45,3 +45,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>   
>   # Enable support for device-tree overlays
>   DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
> +DTC_FLAGS_k3-j721e-common-proc-board += -@
> +
> +# Device-tree overlays
> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-quad-port-eth-exp.dtbo

I'd recommend this; since the EVM as sold comes with the quad port
expansion, let's call that the J721e "EVM". That will allow us to
keep it separate from the Beagle and SK boards. Since this overlay
applies only to the EVM it should named like this:

k3-j721e-evm-quad-port-eth-exp.dtbo

and then when it is applied to the common-proc-board then the result
is called:

k3-j721e-evm.dtb

This way you can take the EVM and run it with that DTB or take the
base board DTB and apply different overlays (there are the GESI and
the Infotainment overlays next). So the full change to this Makefile
in this patch should be this:



--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
  dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
  
  # Boards with J721e SoC
+k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
  dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
-dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
  dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb



Notice we do not need to do that " += -@" stuff either, since
an overlay is applied to make the k3-j721e-evm.dtb, the base DT,

k3-j721e-common-proc-board.dtb

is given symbols automatically.

Yet another benefit is this causes the build to test applying the
overlay and warn us of any missing symbols.

> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
> new file mode 100644
> index 000000000000..d7977d16c921
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
> + * J721E board.
> + *
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/mux/ti-serdes.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-cadence.h>
> +
> +/ {
> +	fragment@102 {
> +		target-path = "/";

This is the old style for fragments, just use

&{/} {
	aliases {


> +		__overlay__ {
> +			aliases {
> +				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
> +				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
> +				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
> +				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
> +			};
> +		};
> +	};
> +};
> +
> +&cpsw0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mdio0_pins_default>;

The MDIO pinmux belongs in the mdio node. Then since it doesn't need
any extra info here, leave this node enabled in the base dtbs.

> +};
> +
> +&cpsw0_port1 {
> +	phy-handle = <&cpsw9g_phy0>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 1>;
> +};
> +
> +&cpsw0_port2 {
> +	phy-handle = <&cpsw9g_phy1>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 2>;
> +};
> +
> +&cpsw0_port3 {
> +	phy-handle = <&cpsw9g_phy2>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 3>;
> +};
> +
> +&cpsw0_port4 {
> +	phy-handle = <&cpsw9g_phy3>;
> +	phy-mode = "qsgmii";
> +	mac-address = [00 00 00 00 00 00];
> +	phys = <&cpsw0_phy_gmii_sel 4>;
> +};
> +
> +&cpsw0_port5 {
> +	status = "disabled";

Since these need phy handles to function, disable them in the base
dtb and only enable the ones connected in this overlay.

Andrew

> +};
> +
> +&cpsw0_port6 {
> +	status = "disabled";
> +};
> +
> +&cpsw0_port7 {
> +	status = "disabled";
> +};
> +
> +&cpsw0_port8 {
> +	status = "disabled";
> +};
> +
> +&cpsw9g_mdio {
> +	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
> +	reset-post-delay-us = <120000>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	cpsw9g_phy0: ethernet-phy@17 {
> +		reg = <17>;
> +	};
> +	cpsw9g_phy1: ethernet-phy@16 {
> +		reg = <16>;
> +	};
> +	cpsw9g_phy2: ethernet-phy@18 {
> +		reg = <18>;
> +	};
> +	cpsw9g_phy3: ethernet-phy@19 {
> +		reg = <19>;
> +	};
> +};
> +
> +&exp2 {
> +	qsgmii-line-hog {
> +		gpio-hog;
> +		gpios = <16 GPIO_ACTIVE_HIGH>;
> +		output-low;
> +		line-name = "qsgmii-pwrdn-line";
> +	};
> +};
> +
> +&main_pmx0 {
> +	mdio0_pins_default: mdio0-pins-default {
> +		pinctrl-single,pins = <
> +			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
> +			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
> +		>;
> +	};
> +};
> +
> +&serdes_ln_ctrl {
> +	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
> +		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
> +		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
> +		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
> +		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
> +		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
> +};
> +
> +&serdes_wiz0 {
> +	status = "okay";
> +};
> +
> +&serdes0 {
> +	status = "okay";
> +
> +	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
> +	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	serdes0_qsgmii_link: phy@1 {
> +		reg = <1>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_QSGMII>;
> +		resets = <&serdes_wiz0 2>;
> +	};
> +};

Re: [PATCH v2 2/2] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode

[Siddharth Vadapalli]

Hello Andrew,

On 15/03/23 03:12, Andrew Davis wrote:
> On 3/10/23 4:35 AM, Siddharth Vadapalli wrote:
>> The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports
>> QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode.
>>
>> Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.
>>
>> Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
>> directly from U-Boot.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/Makefile               |   4 +
>>   .../dts/ti/k3-j721e-quad-port-eth-exp.dtso    | 148 ++++++++++++++++++
>>   2 files changed, 152 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
>> index 6acd12409d59..167bcd9b09b7 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -45,3 +45,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>>     # Enable support for device-tree overlays
>>   DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
>> +DTC_FLAGS_k3-j721e-common-proc-board += -@
>> +
>> +# Device-tree overlays
>> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-quad-port-eth-exp.dtbo
> 
> I'd recommend this; since the EVM as sold comes with the quad port
> expansion, let's call that the J721e "EVM". That will allow us to
> keep it separate from the Beagle and SK boards. Since this overlay
> applies only to the EVM it should named like this:
> 
> k3-j721e-evm-quad-port-eth-exp.dtbo
> 
> and then when it is applied to the common-proc-board then the result
> is called:
> 
> k3-j721e-evm.dtb
> 
> This way you can take the EVM and run it with that DTB or take the
> base board DTB and apply different overlays (there are the GESI and
> the Infotainment overlays next). So the full change to this Makefile
> in this patch should be this:
> 
> 
> 
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
>  dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
>  
>  # Boards with J721e SoC
> +k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb
> k3-j721e-evm-quad-port-eth-exp.dtbo
>  dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
> -dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
>  dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
> 
> 
> 
> Notice we do not need to do that " += -@" stuff either, since
> an overlay is applied to make the k3-j721e-evm.dtb, the base DT,
> 
> k3-j721e-common-proc-board.dtb
> 
> is given symbols automatically.
> 
> Yet another benefit is this causes the build to test applying the
> overlay and warn us of any missing symbols.

I will implement this. I had posted another series for J7200 at:
https://lore.kernel.org/r/20230310101407.722334-1-s-vadapalli@ti.com/
which also attempts to add an overlay with the same approach as done by this
series. I will combine both series, implementing the new approach for both of them.

> 
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
>> b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
>> new file mode 100644
>> index 000000000000..d7977d16c921
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso
>> @@ -0,0 +1,148 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On
>> Ethernet Card with
>> + * J721E board.
>> + *
>> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/mux/ti-serdes.h>
>> +#include <dt-bindings/pinctrl/k3.h>
>> +#include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-cadence.h>
>> +
>> +/ {
>> +    fragment@102 {
>> +        target-path = "/";
> 
> This is the old style for fragments, just use
> 
> &{/} {
>     aliases {
> 
> 

I will fix this.

>> +        __overlay__ {
>> +            aliases {
>> +                ethernet1 =
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
>> +                ethernet2 =
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
>> +                ethernet3 =
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
>> +                ethernet4 =
>> "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
>> +            };
>> +        };
>> +    };
>> +};
>> +
>> +&cpsw0 {
>> +    status = "okay";
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&mdio0_pins_default>;
> 
> The MDIO pinmux belongs in the mdio node. Then since it doesn't need
> any extra info here, leave this node enabled in the base dtbs.

I will do so.

> 
>> +};
>> +
>> +&cpsw0_port1 {
>> +    phy-handle = <&cpsw9g_phy0>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 1>;
>> +};
>> +
>> +&cpsw0_port2 {
>> +    phy-handle = <&cpsw9g_phy1>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 2>;
>> +};
>> +
>> +&cpsw0_port3 {
>> +    phy-handle = <&cpsw9g_phy2>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 3>;
>> +};
>> +
>> +&cpsw0_port4 {
>> +    phy-handle = <&cpsw9g_phy3>;
>> +    phy-mode = "qsgmii";
>> +    mac-address = [00 00 00 00 00 00];
>> +    phys = <&cpsw0_phy_gmii_sel 4>;
>> +};
>> +
>> +&cpsw0_port5 {
>> +    status = "disabled";
> 
> Since these need phy handles to function, disable them in the base
> dtb and only enable the ones connected in this overlay.

I will implement this change and post the v3 series.

Regards,
Siddharth.