Re: [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes

[Andrew Davis <afd@ti.com>]

On 8/8/23 3:18 PM, Apurva Nandan wrote:
> From: Hari Nagalla <hnagalla@ti.com>
> 
> The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
> subsystems/clusters in MAIN voltage domain. Each of these can be
> configured at boot time to be either run in a LockStep mode or in an
> Asymmetric Multi Processing (AMP) fashion in Split-mode. These
> subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
> memories for each core split between two banks - ATCM and BTCM
> (further interleaved into two banks). The TCMs of both Cores are
> combined in LockStep-mode to provide a larger 128 KB of memory, but
> otherwise are functionally similar to those on J721E SoCs.
> 
> Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two
> R5F cores are added as child nodes to each of the R5F cluster nodes.
> The clusters are configured to run in LockStep mode by default, with
> the ATCMs enabled to allow the R5 cores to execute code from DDR
> with boot-strapping code from ATCM. The inter-processor communication
> between the main A72 cores and these processors is achieved through
> shared memory and Mailboxes.
> 
> The following firmware names are used by default for these cores, and
> can be overridden in a board dts file if desired:
>          MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes)
>          MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode)
>          MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes)
>          MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode)
> 
> The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The
> C71x DSPs are 64 bit machine with fixed and floating point DSP operations.
> Similar to the R5F remote cores, the inter-processor communication
> between the main A72 cores and these DSP cores is achieved through
> shared memory and Mailboxes.
> 
> The following firmware names are used by default for these DSP cores,
> and can be overridden in a board dts file if desired:
>          MAIN C71_0 : j721s2-c71_0-fw
>          MAIN C71_1 : j721s2-c71_1-fw
> 
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 104 +++++++++++++++++++++
>   1 file changed, 104 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index dc7920a35237..c428a2b624fb 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -1688,4 +1688,108 @@ dss: dss@4a00000 {
>   		dss_ports: ports {
>   		};
>   	};
> +
> +	main_r5fss0: r5fss@5c00000 {
> +		compatible = "ti,j721s2-r5fss";
> +		ti,cluster-mode = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
> +			 <0x5d00000 0x00 0x5d00000 0x20000>;
> +		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
> +
> +		main_r5fss0_core0: r5f@5c00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5c00000 0x00010000>,
> +			      <0x5c10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <279>;
> +			ti,sci-proc-ids = <0x06 0xff>;
> +			resets = <&k3_reset 279 1>;
> +			firmware-name = "j721s2-main-r5f0_0-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +
> +		main_r5fss0_core1: r5f@5d00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5d00000 0x00010000>,
> +			      <0x5d10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <280>;
> +			ti,sci-proc-ids = <0x07 0xff>;
> +			resets = <&k3_reset 280 1>;
> +			firmware-name = "j721s2-main-r5f0_1-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +	};
> +
> +	main_r5fss1: r5fss@5e00000 {
> +		compatible = "ti,j721s2-r5fss";
> +		ti,cluster-mode = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
> +			 <0x5f00000 0x00 0x5f00000 0x20000>;
> +		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> +
> +		main_r5fss1_core0: r5f@5e00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5e00000 0x00010000>,
> +			      <0x5e10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <281>;
> +			ti,sci-proc-ids = <0x08 0xff>;
> +			resets = <&k3_reset 281 1>;
> +			firmware-name = "j721s2-main-r5f1_0-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +
> +		main_r5fss1_core1: r5f@5f00000 {
> +			compatible = "ti,j721s2-r5f";
> +			reg = <0x5f00000 0x00010000>,
> +			      <0x5f10000 0x00010000>;
> +			reg-names = "atcm", "btcm";
> +			ti,sci = <&sms>;
> +			ti,sci-dev-id = <282>;
> +			ti,sci-proc-ids = <0x09 0xff>;
> +			resets = <&k3_reset 282 1>;
> +			firmware-name = "j721s2-main-r5f1_1-fw";
> +			ti,atcm-enable = <1>;
> +			ti,btcm-enable = <1>;
> +			ti,loczrama = <1>;
> +		};
> +	};
> +
> +	c71_0: dsp@64800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x64800000 0x00 0x00080000>,
> +		      <0x00 0x64e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <8>;
> +		ti,sci-proc-ids = <0x30 0xff>;
> +		resets = <&k3_reset 8 1>;
> +		firmware-name = "j721s2-c71_0-fw";

We are moving to disabled by default for these nodes, see:

https://lore.kernel.org/lkml/20230809180145.53158-2-afd@ti.com/

The C7x stuff should be split out from the R5 stuff, each
should have a patch.

Andrew

> +	};
> +
> +	c71_1: dsp@65800000 {
> +		compatible = "ti,j721s2-c71-dsp";
> +		reg = <0x00 0x65800000 0x00 0x00080000>,
> +		      <0x00 0x65e00000 0x00 0x0000c000>;
> +		reg-names = "l2sram", "l1dram";
> +		ti,sci = <&sms>;
> +		ti,sci-dev-id = <11>;
> +		ti,sci-proc-ids = <0x31 0xff>;
> +		resets = <&k3_reset 11 1>;
> +		firmware-name = "j721s2-c71_1-fw";
> +	};
>   };