* [PATCH v2 1/3] arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes
2023-08-08 20:18 [PATCH v2 0/3] Add R5F and C7x DSP nodes for J721S2 SoC Apurva Nandan
@ 2023-08-08 20:18 ` Apurva Nandan
2023-08-08 20:18 ` [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes Apurva Nandan
2023-08-08 20:18 ` [PATCH v2 3/3] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F and C71x DSPs Apurva Nandan
2 siblings, 0 replies; 5+ messages in thread
From: Apurva Nandan @ 2023-08-08 20:18 UTC (permalink / raw)
To: Apurva Nandan, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
devicetree, linux-kernel, Udit Kumar, Hari Nagalla
From: Hari Nagalla <hnagalla@ti.com>
The J721S2 SoCs have a dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/cluster in MCU voltage domain. It can be configured at boot
time to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode to
provide a larger 128 KB of memory, but otherwise are functionally
similar to those on J721E SoCs.
Add the DT nodes for the MCU domain R5F cluster/subsystem, the two R5F
cores are added as child nodes to each of the R5F cluster nodes. The
clusters are configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication between
the main A72 cores and these processors is achieved through shared memory
and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
MCU R5FSS0 Core0: j721s2-mcu-r5f0_0-fw (both in LockStep and Split modes)
MCU R5FSS0 Core1: j721s2-mcu-r5f0_1-fw (needed only in Split mode)
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 736ec5fa0ea2..d4624d8461b2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -652,4 +652,44 @@ wkup_vtm0: temperature-sensor@42040000 {
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41000000 0x00010000>,
+ <0x41010000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <284>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 284 1>;
+ firmware-name = "j721s2-mcu-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41400000 0x00010000>,
+ <0x41410000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <285>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 285 1>;
+ firmware-name = "j721s2-mcu-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
};
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes
2023-08-08 20:18 [PATCH v2 0/3] Add R5F and C7x DSP nodes for J721S2 SoC Apurva Nandan
2023-08-08 20:18 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes Apurva Nandan
@ 2023-08-08 20:18 ` Apurva Nandan
2023-08-11 15:03 ` Andrew Davis
2023-08-08 20:18 ` [PATCH v2 3/3] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F and C71x DSPs Apurva Nandan
2 siblings, 1 reply; 5+ messages in thread
From: Apurva Nandan @ 2023-08-08 20:18 UTC (permalink / raw)
To: Apurva Nandan, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
devicetree, linux-kernel, Udit Kumar, Hari Nagalla
From: Hari Nagalla <hnagalla@ti.com>
The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters in MAIN voltage domain. Each of these can be
configured at boot time to be either run in a LockStep mode or in an
Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). The TCMs of both Cores are
combined in LockStep-mode to provide a larger 128 KB of memory, but
otherwise are functionally similar to those on J721E SoCs.
Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two
R5F cores are added as child nodes to each of the R5F cluster nodes.
The clusters are configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR
with boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes)
MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes)
MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode)
The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The
C71x DSPs are 64 bit machine with fixed and floating point DSP operations.
Similar to the R5F remote cores, the inter-processor communication
between the main A72 cores and these DSP cores is achieved through
shared memory and Mailboxes.
The following firmware names are used by default for these DSP cores,
and can be overridden in a board dts file if desired:
MAIN C71_0 : j721s2-c71_0-fw
MAIN C71_1 : j721s2-c71_1-fw
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 104 +++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index dc7920a35237..c428a2b624fb 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1688,4 +1688,108 @@ dss: dss@4a00000 {
dss_ports: ports {
};
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5c00000 0x00010000>,
+ <0x5c10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <279>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 279 1>;
+ firmware-name = "j721s2-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5d00000 0x00010000>,
+ <0x5d10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <280>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 280 1>;
+ firmware-name = "j721s2-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@5e00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+ <0x5f00000 0x00 0x5f00000 0x20000>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@5e00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5e00000 0x00010000>,
+ <0x5e10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <281>;
+ ti,sci-proc-ids = <0x08 0xff>;
+ resets = <&k3_reset 281 1>;
+ firmware-name = "j721s2-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@5f00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5f00000 0x00010000>,
+ <0x5f10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <282>;
+ ti,sci-proc-ids = <0x09 0xff>;
+ resets = <&k3_reset 282 1>;
+ firmware-name = "j721s2-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <8>;
+ ti,sci-proc-ids = <0x30 0xff>;
+ resets = <&k3_reset 8 1>;
+ firmware-name = "j721s2-c71_0-fw";
+ };
+
+ c71_1: dsp@65800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x65800000 0x00 0x00080000>,
+ <0x00 0x65e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <11>;
+ ti,sci-proc-ids = <0x31 0xff>;
+ resets = <&k3_reset 11 1>;
+ firmware-name = "j721s2-c71_1-fw";
+ };
};
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes
2023-08-08 20:18 ` [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes Apurva Nandan
@ 2023-08-11 15:03 ` Andrew Davis
0 siblings, 0 replies; 5+ messages in thread
From: Andrew Davis @ 2023-08-11 15:03 UTC (permalink / raw)
To: Apurva Nandan, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
devicetree, linux-kernel, Udit Kumar, Hari Nagalla
On 8/8/23 3:18 PM, Apurva Nandan wrote:
> From: Hari Nagalla <hnagalla@ti.com>
>
> The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
> subsystems/clusters in MAIN voltage domain. Each of these can be
> configured at boot time to be either run in a LockStep mode or in an
> Asymmetric Multi Processing (AMP) fashion in Split-mode. These
> subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
> memories for each core split between two banks - ATCM and BTCM
> (further interleaved into two banks). The TCMs of both Cores are
> combined in LockStep-mode to provide a larger 128 KB of memory, but
> otherwise are functionally similar to those on J721E SoCs.
>
> Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two
> R5F cores are added as child nodes to each of the R5F cluster nodes.
> The clusters are configured to run in LockStep mode by default, with
> the ATCMs enabled to allow the R5 cores to execute code from DDR
> with boot-strapping code from ATCM. The inter-processor communication
> between the main A72 cores and these processors is achieved through
> shared memory and Mailboxes.
>
> The following firmware names are used by default for these cores, and
> can be overridden in a board dts file if desired:
> MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes)
> MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode)
> MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes)
> MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode)
>
> The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The
> C71x DSPs are 64 bit machine with fixed and floating point DSP operations.
> Similar to the R5F remote cores, the inter-processor communication
> between the main A72 cores and these DSP cores is achieved through
> shared memory and Mailboxes.
>
> The following firmware names are used by default for these DSP cores,
> and can be overridden in a board dts file if desired:
> MAIN C71_0 : j721s2-c71_0-fw
> MAIN C71_1 : j721s2-c71_1-fw
>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 104 +++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index dc7920a35237..c428a2b624fb 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -1688,4 +1688,108 @@ dss: dss@4a00000 {
> dss_ports: ports {
> };
> };
> +
> + main_r5fss0: r5fss@5c00000 {
> + compatible = "ti,j721s2-r5fss";
> + ti,cluster-mode = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
> + <0x5d00000 0x00 0x5d00000 0x20000>;
> + power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
> +
> + main_r5fss0_core0: r5f@5c00000 {
> + compatible = "ti,j721s2-r5f";
> + reg = <0x5c00000 0x00010000>,
> + <0x5c10000 0x00010000>;
> + reg-names = "atcm", "btcm";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <279>;
> + ti,sci-proc-ids = <0x06 0xff>;
> + resets = <&k3_reset 279 1>;
> + firmware-name = "j721s2-main-r5f0_0-fw";
> + ti,atcm-enable = <1>;
> + ti,btcm-enable = <1>;
> + ti,loczrama = <1>;
> + };
> +
> + main_r5fss0_core1: r5f@5d00000 {
> + compatible = "ti,j721s2-r5f";
> + reg = <0x5d00000 0x00010000>,
> + <0x5d10000 0x00010000>;
> + reg-names = "atcm", "btcm";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <280>;
> + ti,sci-proc-ids = <0x07 0xff>;
> + resets = <&k3_reset 280 1>;
> + firmware-name = "j721s2-main-r5f0_1-fw";
> + ti,atcm-enable = <1>;
> + ti,btcm-enable = <1>;
> + ti,loczrama = <1>;
> + };
> + };
> +
> + main_r5fss1: r5fss@5e00000 {
> + compatible = "ti,j721s2-r5fss";
> + ti,cluster-mode = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
> + <0x5f00000 0x00 0x5f00000 0x20000>;
> + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> +
> + main_r5fss1_core0: r5f@5e00000 {
> + compatible = "ti,j721s2-r5f";
> + reg = <0x5e00000 0x00010000>,
> + <0x5e10000 0x00010000>;
> + reg-names = "atcm", "btcm";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <281>;
> + ti,sci-proc-ids = <0x08 0xff>;
> + resets = <&k3_reset 281 1>;
> + firmware-name = "j721s2-main-r5f1_0-fw";
> + ti,atcm-enable = <1>;
> + ti,btcm-enable = <1>;
> + ti,loczrama = <1>;
> + };
> +
> + main_r5fss1_core1: r5f@5f00000 {
> + compatible = "ti,j721s2-r5f";
> + reg = <0x5f00000 0x00010000>,
> + <0x5f10000 0x00010000>;
> + reg-names = "atcm", "btcm";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <282>;
> + ti,sci-proc-ids = <0x09 0xff>;
> + resets = <&k3_reset 282 1>;
> + firmware-name = "j721s2-main-r5f1_1-fw";
> + ti,atcm-enable = <1>;
> + ti,btcm-enable = <1>;
> + ti,loczrama = <1>;
> + };
> + };
> +
> + c71_0: dsp@64800000 {
> + compatible = "ti,j721s2-c71-dsp";
> + reg = <0x00 0x64800000 0x00 0x00080000>,
> + <0x00 0x64e00000 0x00 0x0000c000>;
> + reg-names = "l2sram", "l1dram";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <8>;
> + ti,sci-proc-ids = <0x30 0xff>;
> + resets = <&k3_reset 8 1>;
> + firmware-name = "j721s2-c71_0-fw";
We are moving to disabled by default for these nodes, see:
https://lore.kernel.org/lkml/20230809180145.53158-2-afd@ti.com/
The C7x stuff should be split out from the R5 stuff, each
should have a patch.
Andrew
> + };
> +
> + c71_1: dsp@65800000 {
> + compatible = "ti,j721s2-c71-dsp";
> + reg = <0x00 0x65800000 0x00 0x00080000>,
> + <0x00 0x65e00000 0x00 0x0000c000>;
> + reg-names = "l2sram", "l1dram";
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <11>;
> + ti,sci-proc-ids = <0x31 0xff>;
> + resets = <&k3_reset 11 1>;
> + firmware-name = "j721s2-c71_1-fw";
> + };
> };
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F and C71x DSPs
2023-08-08 20:18 [PATCH v2 0/3] Add R5F and C7x DSP nodes for J721S2 SoC Apurva Nandan
2023-08-08 20:18 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes Apurva Nandan
2023-08-08 20:18 ` [PATCH v2 2/3] arm64: dts: ti: k3-j721s2-main: Add R5F and C7x remote processsor nodes Apurva Nandan
@ 2023-08-08 20:18 ` Apurva Nandan
2 siblings, 0 replies; 5+ messages in thread
From: Apurva Nandan @ 2023-08-08 20:18 UTC (permalink / raw)
To: Apurva Nandan, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
devicetree, linux-kernel, Udit Kumar, Hari Nagalla
From: Hari Nagalla <hnagalla@ti.com>
Two carveout reserved memory nodes each have been added for each of the
R5F and C71x remote processor devices/DSP/DSPs within both the MCU and
MAIN domains for the TI J721S2 EVM boards. These nodes are assigned to
the respective rproc device nodes as well. The first region will be used
as the DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for each
device. The R5F processors do not have an MMU, and as such require the
exact memory used by the firmwares to be set-aside. The firmware images
do not require any RSC_CARVEOUT entries in their resource tables either
to allocate the memory for firmware memory segments.
The C71x DSP processor does support a MMU called CMMU, but is not
currently supported and as such requires the exact memory used by the
firmware to be set-aside.
Note that the R5F1 carveouts are needed only if the R5F cluster is running
in Split (non-LockStep) mode. The reserved memory nodes can be disabled
later on if there is no use-case defined to use the corresponding
remote processor.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 206 +++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 594766482071..0b926ff4dd9a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -29,6 +29,108 @@ secure_ddr: optee@9e800000 {
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_1_memory_region: c71-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a8000000 {
+ reg = <0x00 0xa8000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
mux0: mux-controller {
@@ -154,3 +256,107 @@ flash@0 {
cdns,read-delay = <4>;
};
};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c71_1: mbox-c71-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+&c71_1 {
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ memory-region = <&c71_1_dma_memory_region>,
+ <&c71_1_memory_region>;
+};
--
2.34.1
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