Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line

[Mikko Perttunen <mperttunen@nvidia.com>]

On Wednesday, September 30, 2026 5:29 PM Thierry Reding wrote:
> On Wed, Sep 30, 2026 at 09:40:51AM +0200, Thierry Reding wrote:
> > On Wed, Sep 30, 2026 at 01:54:55PM +0900, Mikko Perttunen wrote:
> > > The DSI driver ignores the reset line if a power domain is configured.
> > > This was originally added to support Tegra210, where the power domain
> > > provider has to control the reset line -- at that time, older SoCs
> > > didn't have a power domain for DSI. Now, however, they do with the core
> > > power domain.
> > > 
> > > This happens to work on most systems due to DSI already being out of
> > > reset when booting the kernel, but on Tegra114 Dalmore, this is not the
> > > case and causes the system to hang during boot.
> > > 
> > > Ownership of the reset line is no longer a problem with reset
> > > acquire/release semantics, so control the DSI reset unconditionally
> > > from the DSI driver (possibly in addition to the power domain driver).
> > > The device tree bindings already require the reset and it is present
> > > on all platforms, so this is safe to do.
> > 
> > That seems backwards to me. The whole point of doing this via power
> > domains was because it's explicitly not safe to toggle that reset line
> > outside of the powergate switching sequence.

If you're referring to the MBIST workaround, unless I misremember, it 
doesn't mean the reset cannot be used outside the powergate sequence, 
just that it has to be used within in.

> > 
> > Also, the power domain code paths are supposed to work regardless of
> > whether the DSI was already out of reset or not. If that's not working
> > right now, I think that would qualify as a bug in the power domain code
> > rather than the DSI driver.
> > 
> > Shouldn't this be fixed at the powergate level? My recollection is that
> > DSI is tightly coupled to the display powergates, though it's been a
> > long time. Do we maybe need to reflect that in DT? There's a TODO in
> > tegra114.dtsi that seems to indicate that we're missing DIS and DISB
> > powergate implementations, so maybe that's where we should start to try
> > and resolve this.
> 
> Looking at this a bit more, pd_core doesn't seem to make sense for DSI.
> Basically what that does, semantically, is claim that there's a power
> domain responsible for powering up and down the device, but in reality
> it doesn't to squat.

Doesn't that reasoning apply for every device? Technically, pd_core 
corresponds to the core power rail. DSI is powered from it.. we 
certainly haven't always had an expectation that the power domain 
provider handles resets for the device.

On Tegra114 it looks like DSI indeed is in the DIS domain so that would 
handle it, but on Tegra20/Tegra30 that isn't the case (even if those 
device seem to be working right now anyway).

> 
> Does the hang you observe go away if you remove the power-domains
> property for DSI? pd_core should probably be removed for both display
> controllers and HDMI as well. Probably also TSEC, though the TRM isn't
> clear about what power partition that's in (probably DISB because it's
> used primary for HDMI, which is in DISB as well).

I'd expect it would go away since the reset code in the driver would 
activate then.

> 
> Thierry