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From: Thierry Reding <thierry.reding@kernel.org>
To: Mikko Perttunen <mperttunen@nvidia.com>
Cc: David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	 Jonathan Hunter <jonathanh@nvidia.com>,
	Thierry Reding <treding@nvidia.com>,
	 dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line
Date: Wed, 30 Sep 2026 09:40:51 +0200	[thread overview]
Message-ID: <ary71zC1e-bySLFW@orome> (raw)
In-Reply-To: <20260930-dalmore-fixes-dsi-reset-v1-1-58c9d12f5ebd@nvidia.com>

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On Wed, Sep 30, 2026 at 01:54:55PM +0900, Mikko Perttunen wrote:
> The DSI driver ignores the reset line if a power domain is configured.
> This was originally added to support Tegra210, where the power domain
> provider has to control the reset line -- at that time, older SoCs
> didn't have a power domain for DSI. Now, however, they do with the core
> power domain.
> 
> This happens to work on most systems due to DSI already being out of
> reset when booting the kernel, but on Tegra114 Dalmore, this is not the
> case and causes the system to hang during boot.
> 
> Ownership of the reset line is no longer a problem with reset
> acquire/release semantics, so control the DSI reset unconditionally
> from the DSI driver (possibly in addition to the power domain driver).
> The device tree bindings already require the reset and it is present
> on all platforms, so this is safe to do.

That seems backwards to me. The whole point of doing this via power
domains was because it's explicitly not safe to toggle that reset line
outside of the powergate switching sequence.

Also, the power domain code paths are supposed to work regardless of
whether the DSI was already out of reset or not. If that's not working
right now, I think that would qualify as a bug in the power domain code
rather than the DSI driver.

Shouldn't this be fixed at the powergate level? My recollection is that
DSI is tightly coupled to the display powergates, though it's been a
long time. Do we maybe need to reflect that in DT? There's a TODO in
tegra114.dtsi that seems to indicate that we're missing DIS and DISB
powergate implementations, so maybe that's where we should start to try
and resolve this.

Thierry

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  reply	other threads:[~2026-09-30  7:40 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-30  4:54 Mikko Perttunen
2026-09-30  7:40 ` Thierry Reding [this message]
2026-09-30  8:29   ` Thierry Reding
2026-09-30  8:46     ` Mikko Perttunen
2026-09-30  9:22       ` Thierry Reding

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