From: David Brown <davidb@codeaurora.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Russell King - ARM Linux <linux@arm.linux.org.uk>
Subject: Re: [PATCH v6 00/18] ARM: Add support for the Large Physical Address Extensions
Date: Tue, 24 May 2011 16:56:28 -0700 [thread overview]
Message-ID: <8yapqn7fyab.fsf@huya.qualcomm.com> (raw)
In-Reply-To: <1306273164-18217-1-git-send-email-catalin.marinas@arm.com> (Catalin Marinas's message of "Tue, 24 May 2011 22:39:06 +0100")
On Tue, May 24 2011, Catalin Marinas wrote:
> This set of patches adds support for the Large Physical Extensions on
> the ARM architecture (available with the Cortex-A15 processor). LPAE
> comes with a 3-level page table format (compared to 2-level for the
> classic one), allowing up to 40-bit physical address space.
Do you expect non LPAE targets to be able to boot with these changes
applied (and LPAE enabled)? I am able to build this tree for the
MSM8660 (with a minor patch below), but it fails to boot with LPAE
enabled. It seems to work fine with LPAE not enabled.
I did have to fix the msm timer code to get the branch you mentioned to
compile. The return type of the function changed back to 'void' without
changing the returns:
---
arch/arm/mach-msm/timer.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 50cc0bc..6e659e4 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -268,7 +268,7 @@ static void __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
- return 0;
+ return;
writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@@ -296,7 +296,8 @@ static void __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
if (res) {
pr_err("local_timer_setup: request_irq failed for %s\n",
clock->clockevent.name);
- return res;
+ /* TODO: How to handle this error. */
+ return;
}
clockevents_register_device(evt);
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-05-24 23:56 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-24 21:39 Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 01/18] ARM: LPAE: Use long long printk format for displaying the pud Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 02/18] ARM: LPAE: add ISBs around MMU enabling code Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 03/18] ARM: LPAE: Use unsigned long for __phys_to_virt and __virt_to_phys Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 04/18] ARM: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_* Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 05/18] ARM: LPAE: Factor out 2-level page table definitions into separate files Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 06/18] ARM: LPAE: Add (pte|pmd|pgd|pgprot)val_t type definitions as u32 Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 07/18] ARM: LPAE: Use a mask for physical addresses in page table entries Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 08/18] ARM: LPAE: Introduce the 3-level page table format definitions Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 09/18] ARM: LPAE: Page table maintenance for the 3-level format Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 10/18] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 11/18] ARM: LPAE: Invalidate the TLB before freeing the PMD Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 12/18] ARM: LPAE: Add fault handling support Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 13/18] ARM: LPAE: Add context switching support Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 14/18] ARM: LPAE: Add identity mapping support for the 3-level page table format Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 15/18] ARM: LPAE: Use generic dma_addr_t type definition Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 16/18] ARM: LPAE: mark memory banks with start > ULONG_MAX as highmem Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 17/18] ARM: LPAE: add support for ATAG_MEM64 Catalin Marinas
2011-05-24 21:39 ` [PATCH v6 18/18] ARM: LPAE: Add the Kconfig entries Catalin Marinas
2011-05-24 23:56 ` David Brown [this message]
2011-05-25 0:44 ` [PATCH v6 00/18] ARM: Add support for the Large Physical Address Extensions Nicolas Pitre
2011-05-25 11:10 ` Arnd Bergmann
2011-05-25 11:22 ` Catalin Marinas
2011-05-25 12:43 ` Catalin Marinas
2011-05-25 8:33 ` Catalin Marinas
2011-07-01 16:24 ` Catalin Marinas
2011-07-02 12:19 ` Russell King - ARM Linux
2011-07-04 17:23 ` Catalin Marinas
2011-07-08 19:21 ` Russell King - ARM Linux
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