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* [PATCH 0/3] drm/amd: Enable 2x1 tiled display support on Apple 5K iMacs
@ 2026-10-26 22:45 Richard Lane
  0 siblings, 0 replies; only message in thread
From: Richard Lane @ 2026-10-26 22:45 UTC (permalink / raw)
  To: amd-gfx
  Cc: Alex Deucher, Christian König, Harry Wentland, Leo Li,
	Rodrigo Siqueira, Mario Limonciello, David Airlie, Simona Vetter,
	Richard Lane, dri-devel, linux-kernel

Hi folks,

Apple 27" 5K iMacs (2014-2019, iMac15,1 through Polaris-based iMac19,1)
drive their internal 5120x2880 panel as a 2x1 tiled display using two
2560x2880 streams over an internal eDP root link and a secondary DP
link.

At boot, the Apple EFI firmware initializes only a single 2560x2880 pipe
and leaves the secondary DP tile unlatched with HPD deasserted. Because
the secondary tile reports HPD low and requires a vendor-specific DPCD
handshake before it responds as a DisplayPort sink, amdgpu currently
fails to detect the second tile, leaving Linux limited to single-tile
resolutions.

This series enables full 5120x2880 dual-tile operation on DCE < 12 Apple
5K iMacs so that the internal 5K panel behaves like a standard DisplayID
tiled monitor:

1. Reserve the full 64 MiB stolen EFI framebuffer region in GMC when
   handing over from the relocated Apple EFI framebuffer.
2. Pair the two internal links via an EDID quirk on DCE < 12 (covering
   iMac15,1, iMac17,1, iMac18,3, and Polaris-based iMac19,1), latch the
   secondary tile via DPCD 0x4F1 on the root eDP link, write the 3-byte
   Boot Camp source table (0x310) on the secondary link, keep the
   secondary tile out of D3 power-down, expose both tiles as
   DRM_MODE_CONNECTOR_eDP for userspace compositors, and unlatch the
   TCON back to single-pipe mode on suspend/shutdown. (DCE >= 12 support
   for Vega-equipped iMac19,1, iMacPro1,1, and 2020 iMac20,x is noted as
   TODO)
3. Report the hardware-synchronized state of the two tiles
   (all_displays_in_sync = true) to PowerPlay after dc_commit_streams()
   on DCE < 12. While program_timing_sync() already aligns both CRTCs at
   modeset, DCE < 12 leaves all_displays_in_sync unset, preventing SMU7
   from downclocking MCLK at idle without modeset underflows.

Note for review: Excluding explanatory comments, this series is ~ 47
lines of functional code. All added code comments are intended to be
removed before final submission, except for the comment starting
"Workaround for..." in amdgpu_dm_helpers.c.

Regards,
Richard

Richard Lane (3):
  drm/amdgpu: reserve 64M stolen memory for Apple 5K iMac
  drm/amd/display: unlock secondary tile on Apple 5K iMac panels
  drm/amd/display: report synced Apple 5K tiles to PowerPlay for MCLK
    switch

 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 10 ++++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 44 +++++++++++++++++++
 .../display/amdgpu_dm/amdgpu_dm_connector.c   |  6 +++
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 34 ++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc.h           | 12 +++++
 .../drm/amd/display/dc/link/link_detection.c  | 14 +++++-
 .../dc/link/protocols/link_dp_capability.c    |  7 +++
 .../display/dc/link/protocols/link_dp_phy.c   |  8 ++++
 8 files changed, 133 insertions(+), 2 deletions(-)

-- 
2.55.0

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