From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>, <thierry.reding@gmail.com>
Cc: <linux-pwm@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
Date: Tue, 2 May 2017 16:23:24 +0100 [thread overview]
Message-ID: <908ed0dc-2a75-4348-357c-191fa7348974@nvidia.com> (raw)
In-Reply-To: <1493733937-15822-1-git-send-email-ldewangan@nvidia.com>
On 02/05/17 15:05, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> Before Tegra186, it is 38.4MHz.
> In Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency to the maximum IP
> supported frequency. Provide these values via SoC chipdata.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>
> ---
> Changes from V1:
> - Set the 48MHz maximum frequency for Tegra210 and earlier.
I think that your changelog needs to be updated, because it still says
38.4MHz and not 48MHz.
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2017-05-02 15:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-02 14:05 Laxman Dewangan
2017-05-02 15:23 ` Jon Hunter [this message]
2017-05-02 17:43 ` Laxman Dewangan
2017-05-02 20:10 ` Jon Hunter
2017-05-15 15:17 ` Laxman Dewangan
2017-06-13 12:32 ` Thierry Reding
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