Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 17/07/2025 15:53, Tomer Maimon wrote:
> Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by
> adding device nodes for Ethernet controllers, MMC controller, SPI
> controllers, USB device controllers, random number generator, ADC,
> PWM-FAN controller, I2C controllers, and PECI interface.
> Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and
> aliases for device access.
> This patch enhances functionality for NPCM845-EVB platform.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
>  1 file changed, 445 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> index 2638ee1c3846..46d5bd1c2129 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
> @@ -10,6 +10,42 @@ / {
>  
>  	aliases {
>  		serial0 = &serial0;
> +		ethernet1 = &gmac1;
> +		ethernet2 = &gmac2;
> +		ethernet3 = &gmac3;
> +		mdio-gpio0 = &mdio0;
> +		mdio-gpio1 = &mdio1;
> +		fiu0 = &fiu0;
> +		fiu1 = &fiu3;
> +		fiu2 = &fiux;
> +		fiu3 = &fiu1;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
> +		i2c8 = &i2c8;
> +		i2c9 = &i2c9;
> +		i2c10 = &i2c10;
> +		i2c11 = &i2c11;
> +		i2c12 = &i2c12;
> +		i2c13 = &i2c13;
> +		i2c14 = &i2c14;
> +		i2c15 = &i2c15;
> +		i2c16 = &i2c16;
> +		i2c17 = &i2c17;
> +		i2c18 = &i2c18;
> +		i2c19 = &i2c19;
> +		i2c20 = &i2c20;
> +		i2c21 = &i2c21;
> +		i2c22 = &i2c22;
> +		i2c23 = &i2c23;
> +		i2c24 = &i2c24;
> +		i2c25 = &i2c25;
> +		i2c26 = &i2c26;
>  	};
>  
>  	chosen {
> @@ -25,12 +61,421 @@ refclk: refclk-25mhz {
>  		clock-frequency = <25000000>;
>  		#clock-cells = <0>;
>  	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tip_reserved: tip@0 {
> +			reg = <0x0 0x0 0x0 0x6200000>;
> +		};
> +	};
> +
> +	mdio0: mdio@0 {

Huh... this should fail checks. It's not MMIO node, is it?


> +		compatible = "virtual,mdio-gpio";

where is the reg?

Please confirm that you introduced no new dtbs_check W=1 warnings.

> +		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
> +			<&gpio1 26 GPIO_ACTIVE_HIGH>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		phy0: ethernet-phy@1 {
> +		};
> +	};
> +

...

> +		reg = <0x05>;
> +		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +	fan@6 {
> +		reg = <0x06>;
> +		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +	fan@7 {
> +		reg = <0x07>;
> +		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
> +		cooling-levels = /bits/ 8 <127 255>;
> +	};
> +};
> +
> +&pspi {
> +	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +	Flash@0 {

DTS coding style, naming...



Best regards,
Krzysztof