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From: Melody Olvera <quic_molvera@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"Satya Durga Srinivasu Prabhala" <quic_satyap@quicinc.com>,
	Trilok Soni <quic_tsoni@quicinc.com>
Cc: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 2/4] soc: qcom: llcc-qcom: Add support for LLCC V6
Date: Wed, 9 Apr 2025 14:16:13 -0700	[thread overview]
Message-ID: <92b6ea9d-0b13-472f-afad-2b67d869a0bb@quicinc.com> (raw)
In-Reply-To: <0ca929c6-6ff5-4ab0-8ebf-aed3cc5f350b@oss.qualcomm.com>



On 3/26/2025 6:39 AM, Konrad Dybcio wrote:
> On 3/24/25 9:29 PM, Melody Olvera wrote:
>> Add support for LLCC V6. V6 adds several additional usecase IDs,
>> rearrages several registers and offsets, and supports slice IDs
>> over 31, so add a new function for programming LLCC V6.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
> [...]
>
>> +
>> +	if (config->parent_slice_id && config->fixed_size) {
>> +		attr2_val |= FIELD_PREP(ATTR2_PARENT_SCID_MASK, config->parent_slice_id);
>> +		attr2_val |= ATTR2_IN_A_GROUP_MASK;
>> +	}
> This is fragile if parent_slice_id == 0, but let's say this is not an issue
> for now..

Agreed, but I don't anticipate that being an issue. I don't think any 
slice ID is/will be 0.

>
>> +
>> +	attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
>> +	attr3_val /= drv_data->num_banks;
>> +	attr3_val >>= CACHE_LINE_SIZE_SHIFT;
>> +
>> +	ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
>> +	if (ret)
>> +		return ret;
>> +
>> +	slice_offset = config->slice_id % 32;
>> +	reg_offset = (config->slice_id / 32) * 4;
>> +
>> +	wren = config->write_scid_en << slice_offset;If I'm reading the wrappers right, you should be able to drop both the
> shifting and intermediate variables with regmap_assign_bits()

I'm not so sure. I tried with regmap_assign_bits and it seems the 
correct way to use it would be roughly:

regmap_assign_bits(drv_data->bcast_regmap,
             cfg->reg_offset[LLCC_TRP_WRS_EN], BIT(config->slice_id),
             (bool)config->write_scid_en);

but the third argument is an unsigned int (the BIT(config->slice_id)). I 
tried just putting the slice_id there,
but got some bizarre results leading me to believe that's not the 
correct way to use this api. If I'm missing
something, let me know, but AFAICT, this is six one way, a half-dozen 
another.

Thanks,
Melody

>
> Looks good otherwise
>
> Konrad


  reply	other threads:[~2025-04-09 21:16 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-24 20:29 [PATCH v3 0/4] Introduce LLCC v6 used on the SM8750 SoCs Melody Olvera
2025-03-24 20:29 ` [PATCH v3 1/4] dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block Melody Olvera
2025-03-24 20:29 ` [PATCH v3 2/4] soc: qcom: llcc-qcom: Add support for LLCC V6 Melody Olvera
2025-03-26 13:39   ` Konrad Dybcio
2025-04-09 21:16     ` Melody Olvera [this message]
2025-04-14 13:17       ` Konrad Dybcio
2025-03-24 20:29 ` [PATCH v3 3/4] soc: qcom: llcc-qcom: Add support for SM8750 Melody Olvera
2025-04-14 13:24   ` Konrad Dybcio
2025-04-14 23:07     ` Melody Olvera
2025-03-24 20:29 ` [PATCH v3 4/4] arm64: dts: qcom: sm8750: Add LLCC node Melody Olvera
2025-03-26 13:40   ` Konrad Dybcio

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