Re: [PATCH v3 2/4] soc: qcom: llcc-qcom: Add support for LLCC V6

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 3/24/25 9:29 PM, Melody Olvera wrote:
> Add support for LLCC V6. V6 adds several additional usecase IDs,
> rearrages several registers and offsets, and supports slice IDs
> over 31, so add a new function for programming LLCC V6.
> 
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---

[...]

> +
> +	if (config->parent_slice_id && config->fixed_size) {
> +		attr2_val |= FIELD_PREP(ATTR2_PARENT_SCID_MASK, config->parent_slice_id);
> +		attr2_val |= ATTR2_IN_A_GROUP_MASK;
> +	}

This is fragile if parent_slice_id == 0, but let's say this is not an issue
for now..

> +
> +	attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
> +	attr3_val /= drv_data->num_banks;
> +	attr3_val >>= CACHE_LINE_SIZE_SHIFT;
> +
> +	ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
> +	if (ret)
> +		return ret;
> +
> +	slice_offset = config->slice_id % 32;
> +	reg_offset = (config->slice_id / 32) * 4;
> +
> +	wren = config->write_scid_en << slice_offset;If I'm reading the wrappers right, you should be able to drop both the
shifting and intermediate variables with regmap_assign_bits()

Looks good otherwise

Konrad