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From: Vikash Garodia <quic_vgarodia@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5
Date: Tue, 12 Aug 2025 21:01:36 +0530	[thread overview]
Message-ID: <956e5828-303a-44ce-d41e-0f7b977581a8@quicinc.com> (raw)
In-Reply-To: <2ok6o4e5pz4ichhchycqkns2afzce5y6ppjr2av4yz3wc3iatk@m3cdck7csavt>


On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>> different powering up sequence than previous SM8650, thus different
>>> clocks and resets.  For consistency keep existing clock and clock-names
>>> naming, so the list shares common part.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>
>>> ---
>>
>> [...]
>>
>>> +			iris_opp_table: opp-table {
>>> +				compatible = "operating-points-v2";
>>> +
>>> +				opp-240000000 {
>>> +					opp-hz = /bits/ 64 <240000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>> +							<&rpmhpd_opp_low_svs_d1>;
>>> +				};
>>> +
>>> +				opp-338000000 {
>>> +					opp-hz = /bits/ 64 <338000000>;
>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>> +							<&rpmhpd_opp_low_svs>;
>>> +				};
>>> +
>>> +				opp-420000000 {
>>> +					opp-hz = /bits/ 64 <420000000>;
>>> +					required-opps = <&rpmhpd_opp_svs>,
>>> +							<&rpmhpd_opp_svs>;
>>> +				};
>>> +
>>> +				opp-444000000 {
>>> +					opp-hz = /bits/ 64 <444000000>;
>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>> +							<&rpmhpd_opp_svs_l1>;
>>> +				};
>>> +
>>> +				opp-533333334 {
>>> +					opp-hz = /bits/ 64 <533333334>;
>>> +					required-opps = <&rpmhpd_opp_nom>,
>>> +							<&rpmhpd_opp_nom>;
>>> +				};
>>
>> There's an additional OPP: 570 MHz @ NOM_L1
>>
>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
> 
> We still don't have a way to describe it other way at this point.

I could validate the extended "iommu-map-masks" proposal. Given that we have a
new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
such that later if new property is introduced "iommu-map-mask", it does not
break ABI.

iommus = <&apps_smmu 0x1940 0>;
iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;

[1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/

Regards,
Vikash
> 
>>
>> the other properties look OK
>>
>> Konrad
> 

  reply	other threads:[~2025-08-12 15:31 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-06 12:38 [PATCH RFC v2 0/3] " Krzysztof Kozlowski
2025-08-06 12:38 ` [PATCH RFC v2 1/3] " Krzysztof Kozlowski
2025-08-12 14:21   ` Konrad Dybcio
2025-08-12 14:24     ` Krzysztof Kozlowski
2025-08-12 14:26       ` Konrad Dybcio
2025-08-12 14:39         ` Krzysztof Kozlowski
2025-08-12 14:45           ` Krzysztof Kozlowski
2025-08-12 14:54             ` Krzysztof Kozlowski
2025-08-12 14:39     ` Dmitry Baryshkov
2025-08-12 15:31       ` Vikash Garodia [this message]
2025-08-13 18:41         ` Dmitry Baryshkov
2025-08-14  5:19           ` Vikash Garodia
2025-08-06 12:38 ` [PATCH DO NOT MERGE RFC v2 2/3] arm64: dts: qcom: sm8750-mtp: Enable Iris codec Krzysztof Kozlowski
2025-08-09  9:42   ` Dmitry Baryshkov
2025-08-11 16:10     ` Bjorn Andersson
2025-08-06 12:38 ` [PATCH DO NOT MERGE RFC v2 3/3] arm64: dts: qcom: sm8750-qrd: " Krzysztof Kozlowski
2025-08-06 14:40 ` [PATCH RFC v2 0/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 Rob Herring (Arm)
2025-08-11 16:15   ` Bjorn Andersson
2025-08-11 17:27     ` Neil Armstrong

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