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From: Alexandre Chartre <alexandre.chartre@oracle.com>
To: Chao Gao <chao.gao@intel.com>, Andrew Cooper <andrew.cooper3@citrix.com>
Cc: alexandre.chartre@oracle.com, x86@kernel.org,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	daniel.sneddon@linux.intel.com,
	pawan.kumar.gupta@linux.intel.com, tglx@linutronix.de,
	konrad.wilk@oracle.com, peterz@infradead.org,
	gregkh@linuxfoundation.org, seanjc@google.com,
	dave.hansen@linux.intel.com, nik.borisov@suse.com,
	kpsingh@kernel.org, longman@redhat.com, bp@alien8.de,
	pbonzini@redhat.com
Subject: Re: [PATCH] KVM: x86: Set BHI_NO in guest when host is not affected by BHI
Date: Thu, 11 Apr 2024 15:20:29 +0200	[thread overview]
Message-ID: <95902795-0c2c-43cc-8d87-89302a2eed2b@oracle.com> (raw)
In-Reply-To: <ZhfGHpAz7W7d/pSa@chao-email>


On 4/11/24 13:14, Chao Gao wrote:
>>> The problem is that we can end up with a guest running extra BHI
>>> mitigations
>>> while this is not needed. Could we inform the guest that eIBRS is not
>>> available
>>> on the system so a Linux guest doesn't run with extra BHI mitigations?
>>
>> Well, that's why Intel specified some MSRs at 0x5000xxxx.
> 
> Yes. But note that there is a subtle difference. Those MSRs are used for guest
> to communicate in-used software mitigations to the host. Such information is
> stable across migration. Here we need the host to communicate that eIBRS isn't
> available to the guest. this isn't stable as the guest may be migrated from
> a host without eIBRS to one with it.
> 
>>
>> Except I don't know anyone currently interested in implementing them,
>> and I'm still not sure if they work correctly for some of the more
>> complicated migration cases.
> 
> Looks you have the same opinion on the Intel-defined virtual MSRs as Sean.
> If we all agree the issue here and the effectivenss problem of the short
> BHB-clearing sequence need to be resolved and don't think the Intel-defined
> virtual MSRs can handle all cases correctly, we have to define a better
> interface through community collaboration as Sean suggested.

Another solution could be to add cpus to cpu_vuln_whitelist with BHI_NO.
(e.g. explicitly add cpus which have eIBRS). That way, the kernel will
figure out the right mitigation on the host and guest.

alex.

  reply	other threads:[~2024-04-11 13:21 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-11  7:24 Alexandre Chartre
2024-04-11  7:34 ` Nikolay Borisov
2024-04-11  7:49   ` Alexandre Chartre
2024-04-11  7:51 ` Greg KH
2024-04-11  8:00   ` Alexandre Chartre
2024-04-11  7:51 ` Nikolay Borisov
2024-04-11  8:43 ` Andrew Cooper
2024-04-11  9:33   ` Alexandre Chartre
2024-04-11  9:38     ` Andrew Cooper
2024-04-11 11:14       ` Chao Gao
2024-04-11 13:20         ` Alexandre Chartre [this message]
2024-04-15 15:14           ` Alexandre Chartre
2024-04-15 17:17             ` Dave Hansen
2024-04-16  8:41               ` Alexandre Chartre
2024-04-25 20:45                 ` Konrad Rzeszutek Wilk
2024-04-11 13:22     ` Paolo Bonzini
2024-04-11 13:32       ` Alexandre Chartre
2024-04-11 14:13         ` Andrew Cooper
2024-04-11 14:33           ` Alexandre Chartre
2024-04-11 14:46             ` Paolo Bonzini
2024-04-11 15:12               ` Alexandre Chartre
2024-04-11 15:20                 ` Paolo Bonzini
2024-04-11 15:56                   ` Chao Gao
2024-04-11 20:50                     ` Konrad Rzeszutek Wilk
2024-04-12  3:24                       ` Chao Gao
2024-04-12 16:33                         ` Konrad Rzeszutek Wilk

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