Re: [PATCH v2 3/7] arm64: dts: freescale: Add Lino iMX93

[Andrew Lunn <andrew@lunn.ch>]

> Would you mind to articulate in which situation such race condition can
> happen?

Most PHYs have a number of interrupt sources. Taking a random example:

/* DM9161 Interrupt Register */
#define MII_DM9161_INTR_DPLX_CHANGE     0x0010
#define MII_DM9161_INTR_SPD_CHANGE      0x0008
#define MII_DM9161_INTR_LINK_CHANGE     0x0004

#define MII_DM9161_INTR_CHANGE  \
        (MII_DM9161_INTR_DPLX_CHANGE | \
         MII_DM9161_INTR_SPD_CHANGE | \
         MII_DM9161_INTR_LINK_CHANGE)

and a completely made up example which results in problems...

Three interrupts are enabled. Say the PHY reports a duplex change
first. That causes the interrupt line to go low, giving a downward
edge. The interrupt handler fires, and reads the interrupt status
register. In order the clear the interrupt you need to access another
register about duplex. Before you do that, the link interrupt fires,
setting the link bit in the status register. However, there is not
another edge, because the duplex interrupt has not been cleared
yet. The PHY driver does clear the duplex interrupt and exits the
interrupt handler.

The interrupt line is still low, indicating a link interrupt, but
without an edge, no interrupt handler is triggered. The interrupt has
been lost, and the link is reported down, despite being up.

If however you are using level interrupts, as soon as the interrupt
handler exits, and reenables the interrupt in the parent interrupt
controller, it fires again, and the link interrupt is handled.

If you have multiple interrupts indicated by a single line, you should
use level handling in the parent interrupt controller.

	Andrew