[PATCH v4 0/3] Devicetree updates for MT8186

[PATCH v4 0/3] Devicetree updates for MT8186

[Rohit Agarwal]

Hi,

Changes in v4:
 - Rebased on this series https://lore.kernel.org/all/20240603-mtk-thermal-mt818x-dtsi-v7-0-8c8e3c7a3643@baylibre.com/
 - Updated the overlapping starting address of svs node.

Changes in v3:
 - Update some formatting errors in the bindings patch.

Changes in v2:
 - Update the binding to include power domain in only some
   specific variants.

This series updates the DPI node to add power domain and
adds the Mediatek SVS node as well to MT8186.

Thanks,
Rohit.

Rohit Agarwal (3):
  dt-bindings: display: mediatek: dpi: Add power domains
  arm64: dts: mediatek: mt8186: Add power domain for DPI
  arm64: dts: mediatek: mt8186: Add svs node

 .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8186.dtsi        | 17 +++++++++++++++++
 2 files changed, 34 insertions(+)

-- 
2.46.0.469.g59c65b2a67-goog

[PATCH v4 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Rohit Agarwal]

Add power domain binding to the mediatek DPI controller
for MT8186.
Also, add power domain binding for other SoCs like
MT6795 and MT8173 that already had power domain property.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 5ca7679d5427..3a82aec9021c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -62,6 +62,9 @@ properties:
       - const: default
       - const: sleep
 
+  power-domains:
+    maxItems: 1
+
   port:
     $ref: /schemas/graph.yaml#/properties/port
     description:
@@ -76,6 +79,20 @@ required:
   - clock-names
   - port
 
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - mediatek,mt6795-dpi
+                - mediatek,mt8173-dpi
+                - mediatek,mt8186-dpi
+    then:
+      properties:
+        power-domains: false
+
 additionalProperties: false
 
 examples:
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH v4 2/3] arm64: dts: mediatek: mt8186: Add power domain for DPI

[Rohit Agarwal]

Add power domain phandle to the DPI controller in mediatek
mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index caec83f5eece..85b77ec033c1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1843,6 +1843,7 @@ dpi: dpi@1400a000 {
 			assigned-clocks = <&topckgen CLK_TOP_DPI>;
 			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
 			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
 			status = "disabled";
 
 			port {
-- 
2.46.0.469.g59c65b2a67-goog

[PATCH v4 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Rohit Agarwal]

Add clock/irq/efuse setting in svs nodes for mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 85b77ec033c1..3bd023cdcac0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1372,6 +1372,18 @@ lvts: thermal-sensor@1100b000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		svs: svs@1100bc00 {
+			compatible = "mediatek,mt8186-svs";
+			reg = <0 0x1100bc00 0 0x400>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+			clock-names = "main";
+			nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>;
+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+			resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>;
+			reset-names = "svs_rst";
+		};
+
 		pwm0: pwm@1100e000 {
 			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
 			reg = <0 0x1100e000 0 0x1000>;
@@ -1695,6 +1707,10 @@ lvts_efuse_data2: lvts2-calib@2f8 {
 				reg = <0x2f8 0x14>;
 			};
 
+			svs_calibration: calib@550 {
+				reg = <0x550 0x50>;
+			};
+
 			gpu_speedbin: gpu-speedbin@59c {
 				reg = <0x59c 0x4>;
 				bits = <0 3>;
-- 
2.46.0.469.g59c65b2a67-goog

Re: [PATCH v4 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Chun-Kuang Hu]

Hi, Rohit:

Rohit Agarwal <rohiagar@chromium.org> 於 2024年8月30日 週五 下午4:46寫道：
>
> Add power domain binding to the mediatek DPI controller
> for MT8186.
> Also, add power domain binding for other SoCs like
> MT6795 and MT8173 that already had power domain property.

For this patch, applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

>
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index 5ca7679d5427..3a82aec9021c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -62,6 +62,9 @@ properties:
>        - const: default
>        - const: sleep
>
> +  power-domains:
> +    maxItems: 1
> +
>    port:
>      $ref: /schemas/graph.yaml#/properties/port
>      description:
> @@ -76,6 +79,20 @@ required:
>    - clock-names
>    - port
>
> +allOf:
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - mediatek,mt6795-dpi
> +                - mediatek,mt8173-dpi
> +                - mediatek,mt8186-dpi
> +    then:
> +      properties:
> +        power-domains: false
> +
>  additionalProperties: false
>
>  examples:
> --
> 2.46.0.469.g59c65b2a67-goog
>

Re: [PATCH v4 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Nícolas F. R. A. Prado]

On Fri, Aug 30, 2024 at 08:45:44AM +0000, Rohit Agarwal wrote:
> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Although FWIW the SVS driver fails to probe as is, as for MT8186 it expects
"cpu-big", "cpu-little" and "cci" thermal zones, which are not present in DT
currently. The first two seem to be a matter of renaming (eg there's cpu-little0
and cpu-little1), while cci is completely missing in DT.

Thanks,
Nícolas

Re: [PATCH v4 2/3] arm64: dts: mediatek: mt8186: Add power domain for DPI

[Matthias Brugger]

On 30/08/2024 10:45, Rohit Agarwal wrote:
> Add power domain phandle to the DPI controller in mediatek
> mt8186 SoC.
> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index caec83f5eece..85b77ec033c1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1843,6 +1843,7 @@ dpi: dpi@1400a000 {
>   			assigned-clocks = <&topckgen CLK_TOP_DPI>;
>   			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
>   			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
> +			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
>   			status = "disabled";
>   
>   			port {

Re: [PATCH v4 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Matthias Brugger]

On 30/08/2024 10:45, Rohit Agarwal wrote:
> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 85b77ec033c1..3bd023cdcac0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1372,6 +1372,18 @@ lvts: thermal-sensor@1100b000 {
>   			#thermal-sensor-cells = <1>;
>   		};
>   
> +		svs: svs@1100bc00 {
> +			compatible = "mediatek,mt8186-svs";
> +			reg = <0 0x1100bc00 0 0x400>;
> +			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
> +			clock-names = "main";
> +			nvmem-cells = <&svs_calibration>, <&lvts_efuse_data1>;
> +			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
> +			resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>;
> +			reset-names = "svs_rst";
> +		};
> +
>   		pwm0: pwm@1100e000 {
>   			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
>   			reg = <0 0x1100e000 0 0x1000>;
> @@ -1695,6 +1707,10 @@ lvts_efuse_data2: lvts2-calib@2f8 {
>   				reg = <0x2f8 0x14>;
>   			};
>   
> +			svs_calibration: calib@550 {
> +				reg = <0x550 0x50>;
> +			};
> +
>   			gpu_speedbin: gpu-speedbin@59c {
>   				reg = <0x59c 0x4>;
>   				bits = <0 3>;