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* [PATCH] Remove some PMU events for FUJITSU-MONAKA
@ 2025-02-27  5:40 Yoshihiro Furudera
  2025-02-27 10:53 ` James Clark
  0 siblings, 1 reply; 7+ messages in thread
From: Yoshihiro Furudera @ 2025-02-27  5:40 UTC (permalink / raw)
  To: John Garry, Will Deacon, James Clark, Mike Leach, Leo Yan,
	Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
	Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa,
	Ian Rogers, Adrian Hunter, Liang, Kan, linux-arm-kernel,
	linux-perf-users, linux-kernel, Akio Kakuno, Yoshihiro Furudera

The following events are not counted properly:

0x0037 LL_CACHE_MISS_RD
0x400B L3D_CACHE_LMISS_RD
0x0396 L2D_CACHE_REFILL_L3D_MISS
0x039A L2D_CACHE_REFILL_L3D_MISS_PRF
0x039B L2D_CACHE_REFILL_L3D_MISS_HWPRF
0x039C L2D_CACHE_REFILL_L3D_HIT
0x03A0 L2D_CACHE_REFILL_L3D_HIT_PRF
0x03A1 L2D_CACHE_REFILL_L3D_HIT_HWPRF

Specifically, these events are always counted as misses,
regardless of whether the L3 prefetch is a hit or a miss.
So I remove these events in l3_cache.json, ll_cache.json

Signed-off-by: Yoshihiro Furudera <fj5100bi@fujitsu.com>
---
 .../arch/arm64/fujitsu/monaka/l3_cache.json   | 34 -------------------
 .../arch/arm64/fujitsu/monaka/ll_cache.json   |  4 ---
 2 files changed, 38 deletions(-)

diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json
index 3f3e0d22ac68..917b9b5bf8bb 100644
--- a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json
+++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l3_cache.json
@@ -37,11 +37,6 @@
         "EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF",
         "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access."
     },
-    {
-        "EventCode": "0x0396",
-        "EventName": "L2D_CACHE_REFILL_L3D_MISS",
-        "BriefDescription": "This event counts operations that cause a miss of the L3 cache."
-    },
     {
         "EventCode": "0x0397",
         "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM",
@@ -57,21 +52,6 @@
         "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR",
         "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access."
     },
-    {
-        "EventCode": "0x039A",
-        "EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF",
-        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access."
-    },
-    {
-        "EventCode": "0x039B",
-        "EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF",
-        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access."
-    },
-    {
-        "EventCode": "0x039C",
-        "EventName": "L2D_CACHE_REFILL_L3D_HIT",
-        "BriefDescription": "This event counts operations that cause a hit of the L3 cache."
-    },
     {
         "EventCode": "0x039D",
         "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM",
@@ -87,16 +67,6 @@
         "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_WR",
         "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access."
     },
-    {
-        "EventCode": "0x03A0",
-        "EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF",
-        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access."
-    },
-    {
-        "EventCode": "0x03A1",
-        "EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF",
-        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access."
-    },
     {
         "EventCode": "0x03A2",
         "EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT",
@@ -151,9 +121,5 @@
         "EventCode": "0x03AC",
         "EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L3",
         "BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests."
-    },
-    {
-        "ArchStdEvent": "L3D_CACHE_LMISS_RD",
-        "BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and  a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
     }
 ]
diff --git a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json
index a441b84729ab..c2325855eda3 100644
--- a/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json
+++ b/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ll_cache.json
@@ -2,9 +2,5 @@
     {
         "ArchStdEvent": "LL_CACHE_RD",
         "BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
-    },
-    {
-        "ArchStdEvent": "LL_CACHE_MISS_RD",
-        "BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
     }
 ]
-- 
2.43.0


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2025-03-27  4:24 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-02-27  5:40 [PATCH] Remove some PMU events for FUJITSU-MONAKA Yoshihiro Furudera
2025-02-27 10:53 ` James Clark
2025-02-28  9:55   ` Yoshihiro Furudera (Fujitsu)
2025-03-05  6:40     ` Yoshihiro Furudera (Fujitsu)
2025-03-05  9:37       ` James Clark
2025-03-07  3:10         ` Yoshihiro Furudera (Fujitsu)
2025-03-27  4:24           ` Koichi Okuno (Fujitsu)

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