Re: [PATCH] spi: amd: validate FIFO usage before executing message

["M, Krishnamoorthi" <krishnamoorthi.m@amd.com>]

Hi,


On 10/27/2026 7:43 AM, Weibin Liu wrote:
> The RX FIFO bound is checked in the drain loop, after
> amd_spi_execute_opcode(). A message whose cumulative RX length exceeds
> AMD_SPI_FIFO_SIZE can therefore issue an SPI transaction before being
> rejected.
> 
> Check tx_len + rx_len while walking the message and drop the drain-loop
> check. This validates the complete message before executing the command.
> 
> Tested with a user-space replica covering TX, RX and mixed messages at
> the 70/71-byte boundary. Oversized split-RX messages are now rejected
> without executing the command. No AMD SPI hardware was available.
> 
> Assisted-by: LLM
> Suggested-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
> Fixes: e2f4edfc061e ("spi: amd: fix len==0 underflow and FIFO overflow")
> Reviewed-by: Guanglei Zhu <zhugl3@xiaopeng.com>
> Signed-off-by: Weibin Liu <liuwb@xiaopeng.com>


Thanks, patch looks good to me:

Reviewed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>

Regards,
Krishna