mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Nitin Rawat <quic_nitirawa@quicinc.com>
To: Bjorn Andersson <quic_bjorande@quicinc.com>
Cc: <mani@kernel.org>, <agross@kernel.org>, <andersson@kernel.org>,
	<konrad.dybcio@linaro.org>, <jejb@linux.ibm.com>,
	<martin.petersen@oracle.com>, <quic_cang@quicinc.com>,
	<quic_nguyenb@quicinc.com>, <linux-scsi@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
	"Naveen Kumar Goud Arepalli" <quic_narepall@quicinc.com>
Subject: Re: [PATCH V6 1/6] scsi: ufs: qcom: Align mask for core_clk_1us_cycles
Date: Mon, 4 Sep 2023 20:01:24 +0530	[thread overview]
Message-ID: <9a69fbb0-8a0b-ed74-1ee0-49272d180b9d@quicinc.com> (raw)
In-Reply-To: <20230901151713.GQ818859@hu-bjorande-lv.qualcomm.com>



On 9/1/2023 8:47 PM, Bjorn Andersson wrote:
> On Fri, Sep 01, 2023 at 05:13:31PM +0530, Nitin Rawat wrote:
>> Align core_clk_1us_cycles mask for Qualcomm UFS Controller V4.0.0
> 
> "Align clk mask for ... as per hardware specification."? Are you trying
> to say "The DME_VS_CORE_CLK_CTRL register has changed in v4 of the
> Qualcomm UFS controller, introduce support for the new register layout"?
> 
> You're not aligning the code to match the hardware specification, you're
> fixing the code because the register has changed.
> 
>> onwards as per Hardware Specification.
>>

Hi Bjorn,

Yes, will update the commit text in next patchset



>> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>> ---
>>   drivers/ufs/host/ufs-qcom.c | 28 ++++++++++++++++++----------
>>   drivers/ufs/host/ufs-qcom.h |  5 +++--
>>   2 files changed, 21 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index f88febb23123..fe36003faaa8 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -1297,22 +1297,30 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
>>   }
>>
>>   static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
>> -						       u32 clk_cycles)
>> +						       u32 cycles_in_1us)
> 
> This is a nice clarification, but changing the function prototype gives
> a sense that you changed the parameters - and that's not the case.
> 
> So if you drop this rename, you make the purpose of the patch clearer.
> 
>>   {
>> -	int err;
>> +	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>>   	u32 core_clk_ctrl_reg;
>> +	int ret;
> 
> Renaming err to ret is unrelated and only unnecessary complexity to the
> patch.
> 

ok..Would take care of this comment in next patchset.


>>
>> -	if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
>> -		return -EINVAL;
>> -
>> -	err = ufshcd_dme_get(hba,
>> +	ret = ufshcd_dme_get(hba,
>>   			    UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
>>   			    &core_clk_ctrl_reg);
>> -	if (err)
>> -		return err;
>> +	if (ret)
>> +		return ret;
>>
>> -	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
>> -	core_clk_ctrl_reg |= clk_cycles;
>> +	/* Bit mask is different for UFS host controller V4.0.0 onwards */
>> +	if (host->hw_ver.major >= 4) {
>> +		if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
>> +			return -ERANGE;
>> +		core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
>> +		core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
>> +	} else {
>> +		if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
>> +			return -ERANGE;
>> +		core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
>> +		core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
>> +	}
>>
>>   	/* Clear CORE_CLK_DIV_EN */
>>   	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
>> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>> index d6f8e74bd538..8a9d3dbec297 100644
>> --- a/drivers/ufs/host/ufs-qcom.h
>> +++ b/drivers/ufs/host/ufs-qcom.h
>> @@ -129,8 +129,9 @@ enum {
>>   #define PA_VS_CONFIG_REG1	0x9000
>>   #define DME_VS_CORE_CLK_CTRL	0xD002
>>   /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
>> -#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT		BIT(8)
>> -#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	0xFF
>> +#define CLK_1US_CYCLES_MASK_V4				GENMASK(27, 16)
>> +#define CLK_1US_CYCLES_MASK				GENMASK(7, 0)
>> +#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT	BIT(8)
> 
> Hard to say without applying the patch, please double check that the
> values here have matching indentation level.
> 
> Thank you,
> Bjorn

-Yes I applied and confirmed it's proper.

Thanks,
Nitin


> 
>>
>>   static inline void
>>   ufs_qcom_get_controller_revision(struct ufs_hba *hba,
>> --
>> 2.17.1
>>

  reply	other threads:[~2023-09-04 14:34 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-01 11:43 [PATCH V6 0/6] scsi: ufs: qcom: Align programming sequence as per HW spec Nitin Rawat
2023-09-01 11:43 ` [PATCH V6 1/6] scsi: ufs: qcom: Align mask for core_clk_1us_cycles Nitin Rawat
2023-09-01 15:17   ` Bjorn Andersson
2023-09-04 14:31     ` Nitin Rawat [this message]
2023-09-01 11:43 ` [PATCH V6 2/6] scsi: ufs: qcom: Configure PA_VS_CORE_CLK_40NS_CYCLES Nitin Rawat
2023-09-01 15:30   ` Bjorn Andersson
2023-09-04 14:35     ` Nitin Rawat
2023-09-01 11:43 ` [PATCH V6 3/6] scsi: ufs: qcom: Add multiple frequency support for unipro clk attributes Nitin Rawat
2023-09-01 15:40   ` Bjorn Andersson
2023-09-04 14:41     ` Nitin Rawat
2023-09-01 11:43 ` [PATCH V6 4/6] scsi: ufs: qcom: Align unipro clk attributes configuration as per HPG Nitin Rawat
2023-09-01 15:43   ` Bjorn Andersson
2023-09-04 14:44     ` Nitin Rawat
2023-09-01 11:43 ` [PATCH V6 5/6] scsi: ufs: qcom: Refactor ufs_qcom_cfg_timers function Nitin Rawat
2023-09-01 16:06   ` Bjorn Andersson
2023-09-04 14:48     ` Nitin Rawat
2023-09-01 11:43 ` [PATCH V6 6/6] scsi: ufs: qcom: Configure clk HW division based on scaling conditions Nitin Rawat
2023-09-01 16:13   ` Bjorn Andersson
2023-09-01 12:20 ` [PATCH V6 0/6] scsi: ufs: qcom: Align programming sequence as per HW spec Konrad Dybcio
2023-09-01 14:56 ` Andrew Halaney
2023-09-01 15:18   ` Bjorn Andersson
  -- strict thread matches above, loose matches on Subject: below --
2023-09-01 11:42 Nitin Rawat
2023-09-01 11:42 ` [PATCH V6 1/6] scsi: ufs: qcom: Align mask for core_clk_1us_cycles Nitin Rawat

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9a69fbb0-8a0b-ed74-1ee0-49272d180b9d@quicinc.com \
    --to=quic_nitirawa@quicinc.com \
    --cc=agross@kernel.org \
    --cc=andersson@kernel.org \
    --cc=jejb@linux.ibm.com \
    --cc=konrad.dybcio@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-scsi@vger.kernel.org \
    --cc=mani@kernel.org \
    --cc=martin.petersen@oracle.com \
    --cc=quic_bjorande@quicinc.com \
    --cc=quic_cang@quicinc.com \
    --cc=quic_narepall@quicinc.com \
    --cc=quic_nguyenb@quicinc.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®