mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Larson, Bradley" <Bradley.Larson@amd.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	"Larson, Bradley" <Bradley.Larson@amd.com>,
	Rob Herring <robh@kernel.org>
Cc: "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	"adrian.hunter@intel.com" <adrian.hunter@intel.com>,
	"alcooperx@gmail.com" <alcooperx@gmail.com>,
	"andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>,
	"arnd@arndb.de" <arnd@arndb.de>,
	"brijeshkumar.singh@amd.com" <brijeshkumar.singh@amd.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"gsomlo@gmail.com" <gsomlo@gmail.com>,
	"gerg@linux-m68k.org" <gerg@linux-m68k.org>,
	"krzysztof.kozlowski+dt@linaro.org" 
	<krzysztof.kozlowski+dt@linaro.org>,
	"lee.jones@linaro.org" <lee.jones@linaro.org>,
	"broonie@kernel.org" <broonie@kernel.org>,
	"yamada.masahiro@socionext.com" <yamada.masahiro@socionext.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"piotrs@cadence.com" <piotrs@cadence.com>,
	"p.yadav@ti.com" <p.yadav@ti.com>,
	"rdunlap@infradead.org" <rdunlap@infradead.org>,
	"samuel@sholland.org" <samuel@sholland.org>,
	"fancer.lancer@gmail.com" <fancer.lancer@gmail.com>,
	"Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>,
	"Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
	"ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
	"will@kernel.org" <will@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip
Date: Tue, 13 Sep 2022 21:57:04 +0000	[thread overview]
Message-ID: <9a98d026-7f70-a69b-64de-c77419888e42@amd.com> (raw)
In-Reply-To: <0852ffa5-9996-0f42-c5a8-d1fe9d39887e@linaro.org>

On 9/8/22 4:27 AM, Krzysztof Kozlowski wrote:
> On 01/09/2022 22:37, Larson, Bradley wrote:
>> On 9/1/22 12:20 AM, Krzysztof Kozlowski wrote:
>>> On 01/09/2022 02:01, Larson, Bradley wrote:
>>>>>> +  is implemented by a sub-device reset-controller which accesses
>>>>>> +  a CS0 control register.
>>>>>> +
>>>>>> +maintainers:
>>>>>> +  - Brad Larson <blarson@amd.com>
>>>>>> +
>>>>>> +properties:
>>>>>> +  compatible:
>>>>>> +    items:
>>>>>> +      - enum:
>>>>>> +          - amd,pensando-elbasr
>>>>>> +
>>>>>> +  spi-max-frequency:
>>>>>> +    description: Maximum SPI frequency of the device in Hz.
>>>>> No need for generic descriptions of common properties.
>>>> Changed to "spi-max-frequency: true" and moved to end of properties.
>>> Then you should rather reference spi-peripheral-props just like other
>>> SPI devices.
>>
>> Will look at this dependent on the result of below
>>
>>
>>>>>> +
>>>>>> +  reg:
>>>>>> +    maxItems: 1
>>>>>> +
>>>>>> +  '#address-cells':
>>>>>> +    const: 1
>>>>>> +
>>>>>> +  '#size-cells':
>>>>>> +    const: 0
>>>>>> +
>>>>>> +  interrupts:
>>>>>> +    maxItems: 1
>>>>>> +
>>>>>> +required:
>>>>>> +  - compatible
>>>>>> +  - reg
>>>>>> +  - spi-max-frequency
>>>>>> +
>>>>>> +patternProperties:
>>>>>> +  '^reset-controller@[a-f0-9]+$':
>>>>>> +    $ref: /schemas/reset/amd,pensando-elbasr-reset.yaml
>>>>>> +
>>>>>> +additionalProperties: false
>>>>>> +
>>>>>> +examples:
>>>>>> +  - |
>>>>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>> +
>>>>>> +    spi {
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <0>;
>>>>>> +        num-cs = <4>;
>>>>>> +
>>>>>> +        sysc: system-controller@0 {
>>>>>> +            compatible = "amd,pensando-elbasr";
>>>>>> +            reg = <0>;
>>>>>> +            #address-cells = <1>;
>>>>>> +            #size-cells = <0>;
>>>>>> +            spi-max-frequency = <12000000>;
>>>>>> +
>>>>>> +            rstc: reset-controller@0 {
>>>>>> +                compatible = "amd,pensando-elbasr-reset";
>>>>>> +                reg = <0>;
>>>>> What does 0 represent here? A register address within 'elbasr' device?
>>>> Removed, I recall a check threw a warning or error without reg.
>>>>
>>>>> Why do you need a child node for this? Are there other sub-devices and
>>>>> your binding is incomplete? Just put '#reset-cells' in the parent.
>>>> Without a reset-controller node and booting the function
>>>> __of_reset_control_get(...) fails to find a match in the list here
>>> That's not actually the answer to the question. There was no concerns
>>> whether you need or not reset controller. The question was why do you
>>> need a child device instead of elbasr being the reset controller.
>>>
>>> Your answer does not cover this at all, so again - why do you need a
>>> child for this?
>>>
>> If the parent becomes a reset-controller compatible with
>> "amd,pensando-elbasr-reset" then the /dev node will not be created
> Why /dev node will not be created? How bindings affect having or not
> having something in /dev ?
>
>> as there is no match to "amd,pensando-elbasr" for cs0.  For cs0 internal
>> to linux the reset-controller manages one register bit to hardware reset
>> the mmc device.  A userspace application opens the device node to manage
>> transceiver leds, system leds, reporting temps to host, other reset
>> controls, etc.  Looking at future requirements there likely will be other
>> child devices.
> You mean "amd,pensando-elbasr" will instantiate some more devices? Why
> you cannot add the binding for them now? This is actually important
> because earlier we agreed you remove unit address from children.
>
>> Going down this path with one compatible should reset-elbasr.c just be
>> deleted and fold it into the parent driver pensando-elbasr.c? Then I
>> wonder if it even belongs in drivers/mfd and should just be modified
>> and put in drivers/spi.
> How is it related to bindings?
The compatible "amd,pensando-elbasr" is matched in 
drivers/mfd/pensando-elbasr.c
which creates /dev/pensr0.<cs> for spi chip-selects defined in the 
parent node as:

         num-cs = <4>;
         cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
                    <&porta 7 GPIO_ACTIVE_LOW>;

The compatible "amd,pensando-elbasr-reset" is in 
drivers/reset/reset-elbasr.c
which uses regmap to control one bit in the function at cs0 to hardware 
reset the eMMC.
This is the reason for the reset-controller child and the two driver 
files.  The
probe in drivers/mfd/pensando-elbasr.c is called 4 times, once per spi 
chip-select
and for cs0 mfd_add_devices() is called for the reset controller.

I'll change "rstc: reset-controller@0" to "rstc: reset-controller".

Maybe I've gotten off track following what looked like an appropriate model
to follow ("altr,a10sr") that was initially added in 2017 and has the same
device topology which is SoC <= spi => CPLD/FPGA where a10sr has a 3rd 
driver
file for a gpio controller resulting in two child nodes.

In our case its not one function its four in the device where the function
at chip-select 0 is where the hardware team provided the bit to control
eMMC hardware reset.  Is this a bad approach to follow and if so please
recommend an acceptable approach.  Also, "amd,pensando-elbasr" will not
instantiate more devices.

Snippets below for a10sr in linux-next: Device on other end of spi,
one chip select, two child devices and 3 driver files in mfd, reset, and 
gpio.

FILE: arch/arm/boot/dts/socfpga_arria10_socdk.dtsi:
&spi1 {
         status = "okay";

         resource-manager@0 {
                 compatible = "altr,a10sr";
                 reg = <0>;
                 spi-max-frequency = <100000>;
                 /* low-level active IRQ at GPIO1_5 */
                 interrupt-parent = <&portb>;
                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
                 interrupt-controller;
                 #interrupt-cells = <2>;

                 a10sr_gpio: gpio-controller {
                         compatible = "altr,a10sr-gpio";
                         gpio-controller;
                         #gpio-cells = <2>;
                 };

                 a10sr_rst: reset-controller {
                         compatible = "altr,a10sr-reset";
                         #reset-cells = <1>;
                 };
         };
};

FILE: drivers/mfd/altera-a10sr.c (parent)
static const struct mfd_cell altr_a10sr_subdev_info[] = {
         {
                 .name = "altr_a10sr_gpio",
                 .of_compatible = "altr,a10sr-gpio",
         },
         {
                 .name = "altr_a10sr_reset",
                 .of_compatible = "altr,a10sr-reset",
         },
};

static const struct of_device_id altr_a10sr_spi_of_match[] = {
         { .compatible = "altr,a10sr" },
         { },
};

FILE: drivers/reset/reset-a10sr.c (reset driver)
static const struct of_device_id a10sr_reset_of_match[] = {
         { .compatible = "altr,a10sr-reset" },
         { },
};

FILE: ./drivers/gpio/gpio-altera-a10sr.c (gpio driver)
static const struct of_device_id altr_a10sr_gpio_of_match[] = {
         { .compatible = "altr,a10sr-gpio" },
         { },
};

In comparision, the pensando device is also on the other end of spi,
four chip selects with /dev created for each for userspace control,
and one child device on cs0 for hw reset emmc that the Linux block
layer controls (single bit managed only by kernel).

Pensando:
&spi0 {
         num-cs = <4>;
         cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
                    <&porta 7 GPIO_ACTIVE_LOW>;
         status = "okay";
         system-controller@0 {
                 compatible = "amd,pensando-elbasr";
                 reg = <0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 spi-max-frequency = <12000000>;

                 rstc: reset-controller {
                         compatible = "amd,pensando-elbasr-reset";
                         #reset-cells = <1>;
                 };
         };

         system-controller@1 {
                 compatible = "amd,pensando-elbasr";
                 reg = <1>;
                 spi-max-frequency = <12000000>;
         };

         system-controller@2 {
                 compatible = "amd,pensando-elbasr";
                 reg = <2>;
                 spi-max-frequency = <12000000>;
                 interrupt-parent = <&porta>;
                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
         };

         system-controller@3 {
                 compatible = "amd,pensando-elbasr";
                 reg = <3>;
                 spi-max-frequency = <12000000>;
         };
};

Regards,
Brad

  reply	other threads:[~2022-09-13 21:57 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-20 19:57 [PATCH v6 00/17] Support AMD Pensando Elba SoC Brad Larson
2022-08-20 19:57 ` [PATCH v6 01/17] dt-bindings: arm: add AMD Pensando boards Brad Larson
2022-08-22 18:15   ` Krzysztof Kozlowski
2022-08-31 22:40     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 02/17] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson
2022-08-22 21:29   ` Rob Herring
2022-08-31 22:36     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 03/17] dt-bindings: spi: cdns: Add compatible for " Brad Larson
2022-08-22 18:22   ` Krzysztof Kozlowski
2022-08-31 18:37     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 04/17] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Brad Larson
2022-08-21 17:49   ` Serge Semin
2022-08-31 18:28     ` Larson, Bradley
2022-09-11 18:34       ` Serge Semin
2022-09-14 18:47         ` Larson, Bradley
2022-08-22 18:19   ` Krzysztof Kozlowski
2022-08-31 18:45     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 05/17] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Brad Larson
2022-08-22 18:23   ` Krzysztof Kozlowski
2022-08-31 18:35     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Brad Larson
2022-08-21 20:21   ` Rob Herring
2022-08-22 14:25   ` Rob Herring
2022-08-31 23:01     ` Larson, Bradley
2022-09-01  7:20       ` Krzysztof Kozlowski
2022-09-01 20:37         ` Larson, Bradley
2022-09-08 11:27           ` Krzysztof Kozlowski
2022-09-13 21:57             ` Larson, Bradley [this message]
2022-09-16  9:56               ` Krzysztof Kozlowski
2022-09-29 22:50                 ` Larson, Bradley
2022-10-07 15:53                   ` Krzysztof Kozlowski
2022-08-20 19:57 ` [PATCH v6 07/17] dt-bindings: reset: amd,pensando-elbasr-reset: Add AMD Pensando SR Reset Controller bindings Brad Larson
2022-08-21 20:21   ` Rob Herring
2022-08-20 19:57 ` [PATCH v6 08/17] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson
2022-08-20 19:57 ` [PATCH v6 09/17] arm64: Add config for AMD Pensando SoC platforms Brad Larson
2022-08-20 19:57 ` [PATCH v6 10/17] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson
2022-09-30  7:27   ` Krzysztof Kozlowski
2022-10-04 19:46     ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 11/17] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson
2022-08-20 19:57 ` [PATCH v6 12/17] spi: dw: Add support " Brad Larson
2022-08-21 18:18   ` Serge Semin
2022-08-31 18:04     ` Larson, Bradley
2022-09-11 18:20       ` Serge Semin
2022-09-14 17:03         ` Larson, Bradley
2022-08-20 19:57 ` [PATCH v6 13/17] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson
2022-08-20 19:57 ` [PATCH v6 14/17] mfd: pensando-elbasr: Add AMD Pensando Elba System Resource chip Brad Larson
2022-08-20 19:57 ` [PATCH v6 15/17] reset: elbasr: Add AMD Pensando Elba SR Reset Controller Brad Larson
2022-08-22  7:04   ` Philipp Zabel
2022-08-20 19:57 ` [PATCH v6 16/17] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson
2022-08-20 19:57 ` [PATCH v6 17/17] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson
2022-08-22  7:03   ` Philipp Zabel
2022-08-31 22:49     ` Larson, Bradley
2022-08-22 10:53   ` Ulf Hansson
2022-08-22 12:25     ` Mark Brown
2022-08-31 23:29     ` Larson, Bradley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9a98d026-7f70-a69b-64de-c77419888e42@amd.com \
    --to=bradley.larson@amd.com \
    --cc=Suravee.Suthikulpanit@amd.com \
    --cc=Thomas.Lendacky@amd.com \
    --cc=adrian.hunter@intel.com \
    --cc=alcooperx@gmail.com \
    --cc=andy.shevchenko@gmail.com \
    --cc=arnd@arndb.de \
    --cc=brijeshkumar.singh@amd.com \
    --cc=broonie@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=gerg@linux-m68k.org \
    --cc=gsomlo@gmail.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=lee.jones@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mmc@vger.kernel.org \
    --cc=p.yadav@ti.com \
    --cc=p.zabel@pengutronix.de \
    --cc=piotrs@cadence.com \
    --cc=rdunlap@infradead.org \
    --cc=robh@kernel.org \
    --cc=samuel@sholland.org \
    --cc=ulf.hansson@linaro.org \
    --cc=will@kernel.org \
    --cc=yamada.masahiro@socionext.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®