* [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver [not found] <CGME20250930035518epcas5p2395afdb6f22d2a6b42f9daaec6bc3c1f@epcas5p2.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan [not found] ` <CGME20250930035521epcas5p428367b20b9498eb8862d17f4bb75f663@epcas5p4.samsung.com> ` (30 more replies) 0 siblings, 31 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan Exynos MFC new driver upstream proposal +++++++++++++++++++++++++++++++++++++++ The s5p-mfc driver in the kernel is quite outdated and has not kept up with the hardware advances of the MFC IP. Going forward, we want to provide support for all the later versions of MFC in open source (both mobile and ExynosAuto would be supported by Samsung) We (Samsung) would like to propose a new driver for the latest generation of Samsung MFC (Multi-Format Codec) hardware. Although the kernel already contains a Samsung MFC driver (drivers/media/platform/s5p-mfc/), the newer hardware diverges significantly from the previous generations, in features supported, register interface and in system integration. This has necessitated a new driver, rather than updating the existing one. Current driver vs targetted driver comparison +++++++++++++++++++++++++++++++++++++++++++++ Target Feature Current mainline : Simple V4L2/ VB2 interface based encoder/ decoder New proposed driver: Dual core support, NAL-q support, LLC, Coredump, performance measurement, plugin driver architecture, hardware manager(meerkat), DRM/OTF, Resource manager, bandwidth compression, New Pixel formats (NV12N, YV12, P010, SBWC, RGB family), 10 bit support, HDR support, Prio and RR Process Scheduler support, Register map Current mainline : Fixed register layout, compatible across s5p variants New proposed driver: Completely redesigned register set, incompatible with old layout Command model Current mainline : Mailbox-style command queue New proposed driver: Ring-buffer command queue with different signaling Memory management Current mainline : CMA-backed contiguous buffers, ION legacy New proposed driver: dma-heap / scatter-gather buffers with strict alignment rules Firmware Current mainline : Supports up to Firmware v12, Legacy binary format, loaded via shared mechanism New proposed driver: New firmware format, different protocol for control messages. Support Firmware v13 onwards DT bindings Current mainline : Single clock + reset, simple PM New proposed driver: Multiple clocks, reset domains, runtime PM dependencies Error handling Current mainline : Simple IRQ error flags New proposed driver: Detailed error codes, recovery sequences required Code impact Current mainline :~8k LOC, minimal conditionals New proposed driver: ~65KLOC with full features Plan for supporting latest MFC (Best balance between code clarity and long-term kernel health, while still respecting ABI and legacy users.) 1 We propose a new driver (exynos-mfc) for the latest generation of Samsung MFC (Multi-Format Codec) hardware. 2 MFC FW V6 to V12 will be supported by existing mainline (s5p-mfc) and later versions by Exynos-mfc driver 3 The existing MFC driver will remain available for older SoC’s and will not be broken. The new driver will only bind to new compatible strings in DT, avoiding regressions for legacy hardware. Samsung will take responsibility for maintaining both drivers until the old one can be formally marked as “legacy.” 4 Keep it buildable for old SoCs but clearly say new SoCs should use the new driver. 5 VIDEO_SAMSUNG_S5P_MFC and VIDEO_EXYNOS_MFC will both be supported for an agreed time 6 Long term Support for new driver - commitment from Samsung 7 The hardware has diverged to the point where conditionally supporting both in one codebase is worse for long-term kernel health 8 Splitting keeps the code clean, testable, and reviewable, while ensuring legacy users aren’t broken due to user space ABI guarantees. This seems more clean and easier approach Both can coexist without code spaghetti. Features and description supported ++++++++++++++++++++++++++++++++++ 1 MFC driver registration Probe functionality and video nodes registration 2 MFC driver open & close support MFC firmware loading, "ls" & "cat" on the video nodes and udev rules on the video nodes 3 H264 decoding H264 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) 4 HEVC decoding HEVC decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) 5 VP8 decoding VP8 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) 6 VP9 decoding VP9 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) 7 AV1 decoding AV1 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) 8 H264 encoding H264 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) 9 HEVC encoding HEVC encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) 10 VP8 encoding VP8 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) 11 VP9 encoding VP9 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) 12 Debug fs support Debug fs to control the MFC functionalities 13 Debug log support Debug logs to get on the dmesg prompt for debug purpose 14 Debug SFR dump support MFC SFR dumps during failures 15 NAL Queue mode control NAL Queue mode support 16 Batch mode control Batch mode support 17 HW supported YUV formats YUV 420, 422, 444 (planar, semi-planar) formats support as per MFC HW specification 18 HW supported RGB formats RGB format support as per MFC HW specification 19 Multi instance decoding/encoding Multi instance decoding/encoding 20 Suspend and resume Suspend and resume support 21 Runtime suspend and resume Runtime suspend and resume support 22 Priority decoding (decoders) Priority decoding support 23 Frame delay configuration (decoders) Frame delay configuration support 24 Error handling and conceal control (decoders) HW/Platform limitations should be gracefully exited and, bit stream errors should be reported or concealed with warning indication 25 Reference frame control (encoders) Reference frame control support 26 SPS/PPS control (encoders) SPS/PPS control support 27 Loop filter control (encoders) Loop filter control support 28 B frame support (encoders) B frame support 29 GOP control (encoders) GOP control support 30 Frame rate control (encoders) Frame rate control support Features to be supported in 2026 +++++++++++++++++++++++++++++++++ 31 Bit rate control (encoders) Bit rate control support 32 QP control (encoders) QP control support 33 I/IDR control (encoders) I/IDR control support 34 Scalable control (encoders) Scalable control support 35 ROI control (encoders) ROI control support 36 Multi slice control (encoders) Multi slice control support 37 Profile/Level control (encoders) Profile/Level control support 38 Padding control (encoders) Padding control support 39 Aspect ratio control (encoders) Aspect ratio control support 40 Buffer full handling (encoders) Buffer full handling support 41 SBWC SBWC bandwidth compression support 42 10-bit support 10-bit support as per MFC HW specification 43 Secure signed FW support Security signed FW support 44 Secure playback DRM content playback for decoders 45 HDR Support (decoders) HDR metadata support 46 Dynamic resolution change Dynamic resolution change support Nagaraju Siddineni (29): dt-bindings: media: mfc: Add Exynos MFC devicetree binding arm64: dts: mfc: Add MFC device tree for Auto V920 SoC media: mfc: Add MFC driver data structures and debugging macros media: mfc: Add full register map and bit definitions for MFC hardware media: mfc: Add MFC driver header files and core utilities media: mfc: Add MFC core hardware register and debugfs APIs media: mfc: Add MFC core command, hwlock, ISR and run functionalities media: mfc: Add Exynos‑MFC driver probe support media: mfc: Add bus‑devfreq, QoS, multi‑view and control infrastructure media: mfc: Add buffer‑queue and IOVMM support media: mfc: Add rate‑calculation framework and memory utilities media: mfc: Introduce QoS support and instance context handling media: mfc: Add decoder core sync functions media: mfc: Add buffer‑control framework media: mfc: Add decoder resource‑management (RM) support and load‑balancing media: mfc: Enhance HW‑lock handling, scheduling and error recovery media: mfc: Add VB2 decoder support media: mfc: Add V4L2 decoder driver media: mfc: Add QoS, Butler workqueue, and priority‑based scheduling media: mfc: Add H264 decoder support media: mfc: Add multi‑codec support & QoS improvements media: mfc: Add H.264 encoder support with buffer and QoS improvements media: mfc: Add encoder parameters, ROI & QoS support media: mfc: Add encoder VB2 support to driver media: mfc: Add encoder v4l2 driver interface media: mfc: Add full encoder support media: mfc: Add H.264 encoder support media: mfc: Add AVC, VP8, VP9, and HEVC encoding support media: mfc: Hardware‑accelerated encoding support .../bindings/media/samsung,exynos-mfc.yaml | 77 + MAINTAINERS | 10 + .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 630 +++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 + drivers/media/platform/samsung/Kconfig | 7 + drivers/media/platform/samsung/Makefile | 1 + .../media/platform/samsung/exynos-mfc/Kconfig | 34 + .../platform/samsung/exynos-mfc/Makefile | 26 + .../samsung/exynos-mfc/base/mfc_buf.c | 765 +++ .../samsung/exynos-mfc/base/mfc_buf.h | 43 + .../samsung/exynos-mfc/base/mfc_common.h | 444 ++ .../samsung/exynos-mfc/base/mfc_data_struct.h | 2014 +++++++ .../samsung/exynos-mfc/base/mfc_debug.h | 247 + .../samsung/exynos-mfc/base/mfc_format.h | 316 ++ .../samsung/exynos-mfc/base/mfc_macros.h | 95 + .../samsung/exynos-mfc/base/mfc_media.h | 554 ++ .../samsung/exynos-mfc/base/mfc_mem.c | 995 ++++ .../samsung/exynos-mfc/base/mfc_mem.h | 155 + .../samsung/exynos-mfc/base/mfc_qos.c | 1070 ++++ .../samsung/exynos-mfc/base/mfc_qos.h | 99 + .../samsung/exynos-mfc/base/mfc_queue.c | 966 ++++ .../samsung/exynos-mfc/base/mfc_queue.h | 158 + .../exynos-mfc/base/mfc_rate_calculate.c | 640 +++ .../exynos-mfc/base/mfc_rate_calculate.h | 106 + .../samsung/exynos-mfc/base/mfc_regs.h | 58 + .../samsung/exynos-mfc/base/mfc_regs_mfc.h | 1002 ++++ .../samsung/exynos-mfc/base/mfc_sched.h | 30 + .../samsung/exynos-mfc/base/mfc_utils.c | 401 ++ .../samsung/exynos-mfc/base/mfc_utils.h | 481 ++ .../media/platform/samsung/exynos-mfc/mfc.c | 1366 +++++ .../platform/samsung/exynos-mfc/mfc_core.c | 703 +++ .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 543 ++ .../samsung/exynos-mfc/mfc_core_cmd.c | 576 ++ .../samsung/exynos-mfc/mfc_core_cmd.h | 41 + .../samsung/exynos-mfc/mfc_core_enc_param.c | 1463 ++++++ .../samsung/exynos-mfc/mfc_core_enc_param.h | 23 + .../samsung/exynos-mfc/mfc_core_hw_reg_api.c | 122 + .../samsung/exynos-mfc/mfc_core_hw_reg_api.h | 144 + .../samsung/exynos-mfc/mfc_core_hwlock.c | 761 +++ .../samsung/exynos-mfc/mfc_core_hwlock.h | 80 + .../samsung/exynos-mfc/mfc_core_intlock.c | 98 + .../samsung/exynos-mfc/mfc_core_intlock.h | 20 + .../samsung/exynos-mfc/mfc_core_isr.c | 2104 ++++++++ .../samsung/exynos-mfc/mfc_core_isr.h | 25 + .../samsung/exynos-mfc/mfc_core_ops.c | 813 +++ .../samsung/exynos-mfc/mfc_core_ops.h | 16 + .../platform/samsung/exynos-mfc/mfc_core_pm.c | 209 + .../platform/samsung/exynos-mfc/mfc_core_pm.h | 33 + .../samsung/exynos-mfc/mfc_core_reg_api.c | 597 +++ .../samsung/exynos-mfc/mfc_core_reg_api.h | 380 ++ .../samsung/exynos-mfc/mfc_core_run.c | 541 ++ .../samsung/exynos-mfc/mfc_core_run.h | 35 + .../samsung/exynos-mfc/mfc_core_sched_prio.c | 431 ++ .../samsung/exynos-mfc/mfc_core_sync.c | 423 ++ .../samsung/exynos-mfc/mfc_core_sync.h | 34 + .../samsung/exynos-mfc/mfc_ctx_ctrl.c | 1469 ++++++ .../platform/samsung/exynos-mfc/mfc_debugfs.c | 248 + .../platform/samsung/exynos-mfc/mfc_debugfs.h | 20 + .../samsung/exynos-mfc/mfc_dec_v4l2.c | 1739 +++++++ .../samsung/exynos-mfc/mfc_dec_v4l2.h | 20 + .../platform/samsung/exynos-mfc/mfc_dec_vb2.c | 394 ++ .../platform/samsung/exynos-mfc/mfc_dec_vb2.h | 19 + .../samsung/exynos-mfc/mfc_enc_v4l2.c | 4614 +++++++++++++++++ .../samsung/exynos-mfc/mfc_enc_v4l2.h | 20 + .../platform/samsung/exynos-mfc/mfc_enc_vb2.c | 443 ++ .../platform/samsung/exynos-mfc/mfc_enc_vb2.h | 19 + .../platform/samsung/exynos-mfc/mfc_rm.c | 2652 ++++++++++ .../platform/samsung/exynos-mfc/mfc_rm.h | 110 + 68 files changed, 34773 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi create mode 100644 drivers/media/platform/samsung/exynos-mfc/Kconfig create mode 100644 drivers/media/platform/samsung/exynos-mfc/Makefile create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.h -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035521epcas5p428367b20b9498eb8862d17f4bb75f663@epcas5p4.samsung.com>]
* [PATCH 01/29] dt-bindings: media: mfc: Add Exynos MFC devicetree binding [not found] ` <CGME20250930035521epcas5p428367b20b9498eb8862d17f4bb75f663@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 2025-09-30 6:01 ` Krzysztof Kozlowski 0 siblings, 1 reply; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce a new DT binding file for exynos-mfc Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml which describes the Exynos Multi‑Format Codec (MFC) IP. The schema covers the core node properties, required fields, and provides an example snippet. Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> --- .../bindings/media/samsung,exynos-mfc.yaml | 77 +++++++++++++++++++ MAINTAINERS | 10 +++ 2 files changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml diff --git a/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml new file mode 100644 index 000000000000..fbed987fb9cf --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,exynos-mfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Multi Format Codec (MFC) + +maintainers: + - Nagaraju Siddineni <nagaraju.s@samsung.com> + - Himanshu Dewangan <h.dewangan@samsung.com> + +description: + Multi Format Codec (MFC) is the IP present in Samsung SoCs which + supports high resolution decoding and encoding functionalities. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos-mfc # Exynos920 + - samsung,mfc_core0_mem # Reserved Memory + - samsung,mfc_core1_mem # Reserved Memory + + power-domains: + maximum: 1 + + memory-region: + minimum: 1 + maximum: 2 + +additionalProperties: true + +patternProperties: + "^mfc_core[0-9]$": + type: object + properties: + compatible: + enum: + - samsung,exynos-mfc-core + reg: + maximum: 1 + interrupts: + maximum: 1 + clocks: + minimum: 1 + maximum: 1 + clock-names: + items: + - const: aclk_mfc + + required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + mfc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "samsung,exynos-mfc"; + mfc_core0: MFC-0@19cd0000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "samsung,exynos-mfc-core"; + reg = <0x0 0x19ED0000 0x0 0x10000>; + interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_mfc>; + clocks = <&cmu_top 2000>; + clock-names = "aclk_mfc"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 156fa8eefa69..e47016804ac8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3374,6 +3374,16 @@ S: Maintained F: Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml F: drivers/media/platform/samsung/s5p-mfc/ +ARM/SAMSUNG EXYNOS SERIES Multi Format Codec (MFC) SUPPORT +M: Nagaraju Siddineni <nagaraju.s@samsung.com> +M: Himanshu Dewangan <h.dewangan@samsung.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml +F: drivers/media/platform/samsung/exynos-mfc/ +F: drivers/media/platform/samsung/exynos-mfc/base/ + ARM/SOCFPGA ARCHITECTURE M: Dinh Nguyen <dinguyen@kernel.org> S: Maintained -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 01/29] dt-bindings: media: mfc: Add Exynos MFC devicetree binding 2025-09-30 4:03 ` [PATCH 01/29] dt-bindings: media: mfc: Add Exynos MFC devicetree binding Himanshu Dewangan @ 2025-09-30 6:01 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2025-09-30 6:01 UTC (permalink / raw) To: Himanshu Dewangan Cc: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig On Tue, 30 Sept 2025 at 12:55, Himanshu Dewangan <h.dewangan@samsung.com> wrote: > > From: Nagaraju Siddineni <nagaraju.s@samsung.com> > > Introduce a new DT binding file for exynos-mfc > > Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > which describes the Exynos Multi‑Format Codec (MFC) IP. The schema > covers the core node properties, required fields, and provides an > example snippet. > > Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> > Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> > --- > .../bindings/media/samsung,exynos-mfc.yaml | 77 +++++++++++++++++++ > MAINTAINERS | 10 +++ > 2 files changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > > diff --git a/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > new file mode 100644 > index 000000000000..fbed987fb9cf > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/samsung,exynos-mfc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung Exynos Multi Format Codec (MFC) > + > +maintainers: > + - Nagaraju Siddineni <nagaraju.s@samsung.com> > + - Himanshu Dewangan <h.dewangan@samsung.com> > + > +description: > + Multi Format Codec (MFC) is the IP present in Samsung SoCs which > + supports high resolution decoding and encoding functionalities. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - samsung,exynos-mfc # Exynos920 > + - samsung,mfc_core0_mem # Reserved Memory > + - samsung,mfc_core1_mem # Reserved Memory NAK These bindings duplicate existing ones, do not follow any existing standards (wrong compatible) and are written completely different than any other binding, which means you probably created big AI slop. I'm not going to review this, it's quality is just beyond basic standards. Sending something like this from Samsung means you do not respect our time. You need to stay from scratch and read existing documentation and existing bindings I'll be organizing a mini meeting with Samsung on 13th Oct in Seoul, feel free to join if you are around. I can explain then more why wasting our time is making me very grumpy. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035525epcas5p3a1238a3a7bc6e52113838397187e36ba@epcas5p3.samsung.com>]
* [PATCH 02/29] arm64: dts: mfc: Add MFC device tree for Auto V920 SoC [not found] ` <CGME20250930035525epcas5p3a1238a3a7bc6e52113838397187e36ba@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 2025-09-30 6:40 ` Krzysztof Kozlowski 0 siblings, 1 reply; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce the device‑tree entries for the Samsung Exynos AUTO V920 multimedia‑function controller (MFC). The patch defines: - Reserved memory regions for firmware and CMA buffers. - Core0 and Core1 memory mappings. - The main MFC node with basic properties (compatible, reg, interrupts, clocks, DMA window, firmware name, debug mode, etc.). - Per‑core sub‑nodes (MFC‑0 and MFC‑1) with their own sysmmu, firmware region, and configuration parameters. - Resource table listing supported codecs and their capabilities. Adds full support for the V920 MFC hardware to the mainline kernel device‑tree, enabling proper memory allocation, interrupt handling and codec operation on this platform. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 187 ++++++++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 + 2 files changed, 188 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi new file mode 100644 index 000000000000..49c61958467e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAMSUNG EXYNOS AUTO V920 SoC MFC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#define MFC_CORE0_MEM_ADDR 0xE9C00000 +#define MFC_CORE1_MEM_ADDR 0xEFB00000 +#define MFC_CMA_MEM_ADDR 0xB0000000 +#define MFC_CMA_MEM_SIZE 0x040000000 /* 64MB */ +#define MFC_FW_MEM_ADDR 0x9F000000 +#define MFC_FW_MEM_SIZE 0x00800000 /* 8MB */ +#define MFC_MEM_SIZE 0x00100000 /* 1MB */ + +/ { +reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mfc_fw_rmem: mfc_fw_rmem@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 MFC_FW_MEM_ADDR 0x0 MFC_FW_MEM_SIZE>; + alignment = <0x0 0x00010000>; + reusable; + }; + + mfc_buf_rmem: mfc_buf_rmem { + compatible = "shared-dma-pool"; + reg = <0x0 MFC_CMA_MEM_ADDR 0x0 MFC_CMA_MEM_SIZE>; + alignment = <0x0 0x00010000>; + reusable; + linux,cma-default; + }; + + mfc_core0_mem: mfc_core0_mem@e9c00000 { + compatible = "samsung,mfc_core0_mem"; + reg = <0x0 MFC_CORE0_MEM_ADDR 0x0 MFC_MEM_SIZE>; + }; + + mfc_core1_mem: mfc_core1_mem@efb00000 { + compatible = "samsung,mfc_core1_mem"; + reg = <0x0 MFC_CORE1_MEM_ADDR 0x0 MFC_MEM_SIZE>; + }; +}; + + mfc: mfc@19cd0000 { + /* Basic setting */ + compatible = "samsung,exynos-mfc"; + + reg = <0x0 0x19CD0000 0x0 0x10000>; + interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_mfc"; + clocks = <&cmu_top 1900>; + + /* for vb2 device */ + samsung,tzmp; + + /* for F/W buffer to support 36bit-DMA */ + memory-region = <&mfc_fw_rmem &mfc_buf_rmem>; + + /* MFC DMA bit (32 or 36) */ + dma_bit_mask = <32>; + + /* MFC version */ + ip_ver = <0x1600010C>; + + /* MFC firmware name */ + fw_name = "mfc_fw_v16.0.bin"; + + /* Debug mode */ + debug_mode = <1>; + + /* Features <on/off version> */ + mem_clear = <1 0x0>; + /* Support from v11.0 (except 11.2) */ + wait_fw_status = <1 0x190122>; + + /* Scheduler 0: round-robin, 1: PBS */ + scheduler = <1>; + /* The number of priority in PBS */ + pbs_num_prio = <1>; + + /* MFC IOVA threshold (MB) */ + iova_threshold = <1700>; + + /* Sub nodes for MFC core */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * Resource of standard + * <codec num> MFC_REG_CODEC_XXX + * <op core type> 0: MFC only, 1: MFD only, 2: ALL + * <max Kbps> 245760: 240Mbps, 122880: 120Mbps, 81920: 80Mbps + */ + mfc_resource { + /* codec name { codec mode, op core type, max Kbps } */ + H264_dec { info = <0 2 245760>; }; + VP8_dec { info = <14 0 81920>; }; + HEVC_dec { info = <17 2 245760>; }; + VP9_dec { info = <18 0 81920>; }; + AV1_dec { info = <19 1 122880>; }; + H264_enc { info = <20 0 245760>; }; + VP8_enc { info = <25 0 81920>; }; + HEVC_enc { info = <26 0 245760>; }; + VP9_enc { info = <27 0 81920>; }; + }; + + /* MFC core device */ + mfc_core0: MFC-0@19cd0000 { + /* Basic setting */ + compatible = "samsung,exynos-mfc-core"; + id = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x19CD0000 0x0 0x10000>; + interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_mfc"; + clocks = <&cmu_top 1900>; + samsung,tzmp; + + /* MFC version */ + ip_ver = <0x1600010C>; + + /* for F/W buffer */ + fw-region = <&mfc_core0_mem>; + + /* Sysmmu check */ + share_sysmmu = <0>; + axid_mask = <0xFFFF>; + tsmux_axid = <0x1>; + + /* mem-log buffer size */ + memlog_size = <0x80000>; + memlog_sfr_size = <0x1000>; + + /* Device virtual address */ + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x0 0xF0000000>; + + /* Sub nodes for sysmmu, hwfc and mmcache */ + iommu@19c70000 { + reg = <0x0 0x19C70000 0x0 0x9000>; + }; + }; + + mfc_core1: MFC-1@19ed0000 { + /* Basic setting */ + compatible = "samsung,exynos-mfc-core"; + id = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x19ED0000 0x0 0x10000>; + interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_mfc"; + clocks = <&cmu_top 2000>; + samsung,tzmp; + + /* MFC version */ + ip_ver = <0x1600010D>; + + /* for F/W buffer */ + fw-region = <&mfc_core1_mem>; + + /* Sysmmu check */ + share_sysmmu = <0>; + axid_mask = <0xFFFF>; + + /* Device virtual address */ + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x0 0xF0000000>; + + /* Sub nodes for sysmmu, hwfc and mmcache */ + iommu@19e70000 { + reg = <0x0 0x19E70000 0x0 0x9000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..f35441d29cdd 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1507,3 +1507,4 @@ timer { }; #include "exynosautov920-pinctrl.dtsi" +#include "exynosautov920-evt2-mfc.dtsi" -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 02/29] arm64: dts: mfc: Add MFC device tree for Auto V920 SoC 2025-09-30 4:03 ` [PATCH 02/29] arm64: dts: mfc: Add MFC device tree for Auto V920 SoC Himanshu Dewangan @ 2025-09-30 6:40 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2025-09-30 6:40 UTC (permalink / raw) To: Himanshu Dewangan Cc: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig On Tue, 30 Sept 2025 at 12:55, Himanshu Dewangan <h.dewangan@samsung.com> wrote: > > From: Nagaraju Siddineni <nagaraju.s@samsung.com> > > Introduce the device‑tree entries for the Samsung Exynos AUTO V920 > multimedia‑function controller (MFC). The patch defines: > - Reserved memory regions for firmware and CMA buffers. > - Core0 and Core1 memory mappings. > - The main MFC node with basic properties (compatible, reg, interrupts, > clocks, DMA window, firmware name, debug mode, etc.). > - Per‑core sub‑nodes (MFC‑0 and MFC‑1) with their own sysmmu, > firmware region, and configuration parameters. > - Resource table listing supported codecs and their capabilities. > > Adds full support for the V920 MFC hardware to the mainline kernel > device‑tree, enabling proper memory allocation, interrupt handling and > codec operation on this platform. > > Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> > Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> > --- > .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 187 ++++++++++++++++++ No, there are no such files. Don't push your downstream here. > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 + > 2 files changed, 188 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi > This doesn't belong to media patchset, don't combine them. Anyway, you completely disregarded DTS coding style and how we were Samsung DTS. Please don't send us downstream code. I won't be reviewing this, you need to start from scratch looming at other recent code. Remember also about Samsung maintainer profile, although with such completely broken and non working bindings it's pointless now - this code couldn't even be reliably tested with them. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
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* [PATCH 03/29] media: mfc: Add MFC driver data structures and debugging macros [not found] ` <CGME20250930035527epcas5p3e6b8c8040341cd99e6e73c9db7a4d74e@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> This patch introduces the core data structures and debugging infrastructure for the Samsung Exynos MFC (Multi‑Format Codec) driver. mfc_data_struct.h Defines all driver‑wide constants, enums, and structures required for MFC core, contexts, buffers, QoS, and platform data. Includes definitions for codec types, instance states, buffer usage, logging options, feature flags, and hardware resources. Provides the main struct mfc_dev, struct mfc_core, struct mfc_ctx, and related helper structures. mfc_debug.h Implements a comprehensive set of debug macros (mfc_debug, mfc_ctx_debug, mfc_core_debug, etc.) with configurable logging levels. Adds error‑handling macros and trace utilities for device, core, and context tracing. Supports printing to the kernel log based on the driver’s debugfs.logging_option settings. These additions lay the groundwork for the MFC driver’s functionality, enabling detailed logging, state tracking, and proper management of codec resources. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_data_struct.h | 985 ++++++++++++++++++ .../samsung/exynos-mfc/base/mfc_debug.h | 247 +++++ 2 files changed, 1232 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h new file mode 100644 index 000000000000..59fef39095d2 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h @@ -0,0 +1,985 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_data_struct.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_DATA_STRUCT_H +#define __MFC_DATA_STRUCT_H __FILE__ + +#include <linux/videodev2.h> +#include <linux/cma.h> +#include <linux/genalloc.h> +#include <linux/pm_qos.h> + +#include <media/v4l2-device.h> +#include <media/v4l2-ioctl.h> +#include <media/videobuf2-v4l2.h> + +#include "mfc_media.h" + +/* DEBUGFS */ +#define MFC_DEFAULT_LOGGING_OPTION 0x7 + +#define MFC_NUM_CORE 2 +#define MFC_NUM_CONTEXTS 32 +#define MFC_MAX_PLANES 3 +#define MFC_MAX_DPBS 64 +#define MFC_MAX_BUFFERS 32 +#define MFC_MAX_EXTRA_BUF 10 +#define MFC_SFR_LOGGING_COUNT_SET0 10 +#define MFC_SFR_LOGGING_COUNT_SET1 28 +#define MFC_SFR_LOGGING_COUNT_SET2 32 +#define MFC_LOGGING_DATA_SIZE 950 +/* the number of priority is 2N(num of OPP) + 2 */ +#define MFC_MAX_PRIO 12 +/* The number of display DRC max frames that can occur continuously in NAL_Q */ +#define MFC_MAX_DRC_FRAME MFC_MAX_BUFFERS + +/* The last number of the standard(MFC_REG_CODEC_BPG_ENC) supported by MFC + 1 */ +#define MFC_MAX_CODEC_TYPE (33 + 1) + +/* Maximum number of temporal layers */ +#define VIDEO_MAX_TEMPORAL_LAYERS 7 + +/* Batch mode */ +#define MAX_NUM_IMAGES_IN_VB 8 + +/* QoS */ +#define MAX_TIME_INDEX 15 +#define MAX_NUM_CLUSTER 3 +#define MAX_NUM_MFC_BPS 2 +#define MAX_NUM_MFC_FREQ 10 +#define MAX_NUM_QOS_DYNAMIC 10 + +#define MFC_FMT_FLAG_MULTI_VIEW 0x0010 +#define MFC_FMT_FLAG_DEPTH_MAP 0x0020 + +#define MFC_NUM_SPECIAL_BUF_NAME 25 + +#define BANK_L_CTX 0 +#define BANK_R_CTX 1 +#define BANK_NUM 2 + +/** + * enum mfc_inst_type - The type of an MFC device node. + */ +enum mfc_node_type { + MFCNODE_INVALID = -1, + MFCNODE_DECODER = 0, + MFCNODE_ENCODER = 1, + MFCNODE_DECODER_DRM = 2, + MFCNODE_ENCODER_DRM = 3, + MFCNODE_ENCODER_OTF = 4, + MFCNODE_ENCODER_OTF_DRM = 5, +}; + +/** + * enum mfc_dev_state - The type of an MFC device. + */ +enum mfc_core_state { + MFCCORE_INIT = 0, + MFCCORE_ERROR = 1, +}; + +/** + * enum mfc_inst_type - The type of an MFC instance. + */ +enum mfc_inst_type { + MFCINST_INVALID = 0, + MFCINST_DECODER = 1, + MFCINST_ENCODER = 2, +}; + +/** + * enum mfc_inst_state - The state of an MFC instance. + */ +enum mfc_inst_state { + MFCINST_FREE = 0, + MFCINST_INIT = 100, + MFCINST_RUNNING, + MFCINST_RETURN_INST, + MFCINST_ERROR, + MFCINST_ABORT +}; + +enum mfc_buf_usage_type { + MFCBUF_INVALID = 0, + MFCBUF_NORMAL, + MFCBUF_DRM, + MFCBUF_NORMAL_FW, + MFCBUF_DRM_FW, +}; + +enum mfc_frame_error_type { + MFC_ERR_FRAME_NO_ERR = 0, + MFC_ERR_FRAME_CONCEALMENT = 1, + MFC_ERR_FRAME_SYNC_POINT = 2, + MFC_ERR_FRAME_BROKEN = 3, +}; + +enum mfc_do_cache_flush { + MFC_NO_CACHEFLUSH = 0, + MFC_CACHEFLUSH = 1, +}; + +enum mfc_idle_mode { + MFC_IDLE_MODE_NONE = 0, + MFC_IDLE_MODE_RUNNING = 1, + MFC_IDLE_MODE_IDLE = 2, + MFC_IDLE_MODE_CANCEL = 3, +}; + +enum mfc_debug_cause { + /* panic cause */ + MFC_CAUSE_0WRITE_PAGE_FAULT = 0, + MFC_CAUSE_0PAGE_FAULT = 1, + MFC_CAUSE_1WRITE_PAGE_FAULT = 2, + MFC_CAUSE_1PAGE_FAULT = 3, + MFC_CAUSE_NO_INTERRUPT = 4, + MFC_CAUSE_NO_SCHEDULING = 5, + MFC_CAUSE_FAIL_STOP_NAL_Q = 6, + MFC_CAUSE_FAIL_STOP_NAL_Q_FOR_OTHER = 7, + MFC_CAUSE_FAIL_CLOSE_INST = 8, + MFC_CAUSE_FAIL_SLEEP = 9, + MFC_CAUSE_FAIL_WAKEUP = 10, + MFC_CAUSE_FAIL_RISC_ON = 11, + MFC_CAUSE_FAIL_DPB_FLUSH = 12, + MFC_CAUSE_FAIL_CACHE_FLUSH = 13, + MFC_CAUSE_FAIL_MOVE_INST = 14, +}; + +enum mfc_core_type { + MFC_CORE_INVALID = -1, + MFC_CORE_MAIN = 0, + MFC_CORE_SUB = 1, + MFC_CORE_TYPE_NUM = 2, +}; + +enum mfc_op_core_type { + MFC_OP_CORE_NOT_FIXED = -1, + MFC_OP_CORE_FIXED_0 = 0, + MFC_OP_CORE_FIXED_1 = 1, + MFC_OP_CORE_ALL = 2, +}; + +enum mfc_op_mode { + MFC_OP_SINGLE = 0, + MFC_OP_TWO_MODE1 = 1, + MFC_OP_TWO_MODE2 = 2, + MFC_OP_SWITCHING = 3, + MFC_OP_SWITCH_TO_SINGLE = 4, + MFC_OP_SWITCH_BUT_MODE2 = 5, +}; + +enum mfc_enc_gdc_type { + MFC_GDC_VOTF = 1, + MFC_GDC_OTF = 2, +}; + +enum mfc_hwacg_type { + MFC_HWACG_NONE = 0, + MFC_HWACG_DRV_CTRL = 1, + MFC_HWACG_HWFW_CTRL = 2, +}; + +enum mfc_real_time { + /* real-time */ + MFC_RT = 0, + /* low-priority real-time */ + MFC_RT_LOW = 1, + /* constrained real-time */ + MFC_RT_CON = 2, + /* non real-time */ + MFC_NON_RT = 3, + MFC_RT_UNDEFINED = 4, +}; + +enum mfc_sched_type { + MFC_SCHED_RR = 0, + MFC_SCHED_PRIO = 1, +}; + +/* core driver */ +extern struct platform_driver mfc_core_driver; + +struct mfc_ctx; +struct mfc_core_ctx; +struct mfc_sched_class; + +struct mfc_debug { + u32 fw_version; + u32 cause; + u8 fault_status; + u32 fault_trans_info; + u64 fault_addr; + u32 sfrs_set0[MFC_SFR_LOGGING_COUNT_SET0]; + u32 sfrs_set1[MFC_SFR_LOGGING_COUNT_SET1]; + u32 sfrs_set2[MFC_SFR_LOGGING_COUNT_SET2]; + u8 curr_ctx; + u8 state; + u8 last_cmd; + u32 last_cmd_sec; + u32 last_cmd_nsec; + u8 last_int; + u32 last_int_sec; + u32 last_int_nsec; + u32 frame_cnt; + u8 hwlock_dev; + u32 hwlock_ctx; + u8 num_inst; + u8 power_cnt; + u8 clock_cnt; + /* for decoder only */ + u32 last_src_addr; + u32 last_dst_addr[MFC_MAX_PLANES]; + /* total logging data */ + char errorinfo[MFC_LOGGING_DATA_SIZE]; +}; + +enum mfc_view_id { + MFC_VIEW_ID_MAIN = 0, + MFC_VIEW_ID_SUB = 1, +}; + +/** + * struct mfc_buf - MFC buffer + * + */ +struct mfc_buf { + struct vb2_v4l2_buffer vb; + struct list_head list; + dma_addr_t addr[MAX_NUM_IMAGES_IN_VB][MFC_MAX_PLANES]; + phys_addr_t paddr; + struct dma_buf *dmabufs[MAX_NUM_IMAGES_IN_VB][MFC_MAX_PLANES]; + struct dma_buf_attachment *attachments[MAX_NUM_IMAGES_IN_VB][MFC_MAX_PLANES]; + size_t sg_size; + int src_index; + int dpb_index; + int next_index; + int done_index; + int used; + int num_valid_bufs; + unsigned char *vir_addr[MFC_MAX_PLANES]; + u32 flag; + unsigned long i_ino; +}; + +struct mfc_buf_queue { + struct list_head head; + unsigned int count; +}; + +struct mfc_hwlock { + struct list_head waiting_list; + unsigned int wl_count; + unsigned long bits; + unsigned long dev; + unsigned int owned_by_irq; + unsigned int transfer_owner; + /* protection */ + spinlock_t lock; +}; + +struct mfc_listable_wq { + struct list_head list; + wait_queue_head_t wait_queue; + /* protection */ + struct mutex wait_mutex; + struct mfc_dev *dev; + struct mfc_core *core; + struct mfc_ctx *ctx; + struct mfc_core_ctx *core_ctx; +}; + +struct mfc_core_intlock { + int lock; + unsigned long bits; + unsigned long pending; + /* protection */ + struct mutex core_mutex; +}; + +struct mfc_core_lock { + int cnt; + /* protection */ + spinlock_t lock; + wait_queue_head_t wq; +}; + +struct mfc_pm { + struct clk *clock; + atomic_t pwr_ref; + atomic_t protect_ref; + struct device *device; + /* protection */ + spinlock_t clklock; + + int clock_on_steps; + int clock_off_steps; + enum mfc_buf_usage_type base_type; +}; + +enum mfc_fw_status { + MFC_FW_NONE = 0, + MFC_FW_ALLOC = BIT(0), // 0x1 + MFC_CTX_ALLOC = BIT(1), // 0x2 + MFC_FW_LOADED = BIT(2), // 0x4 + MFC_FW_VERIFIED = BIT(3), // 0x8 + MFC_FW_PROTECTED = BIT(4), // 0x10 + MFC_FW_INITIALIZED = BIT(5), // 0x20 +}; + +struct mfc_fw { + int date; + int fimv_info; + size_t fw_size; + enum mfc_fw_status status; +}; + +struct mfc_ctx_buf_size { + size_t dev_ctx; + size_t dbg_info_buf; +}; + +struct mfc_buf_size { + size_t firmware_code; + unsigned int cpb_buf; + struct mfc_ctx_buf_size *ctx_buf; +}; + +struct mfc_variant { + struct mfc_buf_size *buf_size; + int num_entities; +}; + +enum mfc_sfr_dump_type { + MFC_DUMP_NONE = 0, + MFC_DUMP_DEC_SEQ_START = BIT(0), + MFC_DUMP_DEC_INIT_BUFS = BIT(1), + MFC_DUMP_DEC_FIRST_NAL_START = BIT(2), + MFC_DUMP_ENC_SEQ_START = BIT(3), + MFC_DUMP_ENC_INIT_BUFS = BIT(4), + MFC_DUMP_ENC_FIRST_NAL_START = BIT(5), + MFC_DUMP_ERR_INT = BIT(6), + MFC_DUMP_WARN_INT = BIT(7), + MFC_DUMP_DEC_NAL_START = BIT(8), + MFC_DUMP_DEC_FRAME_DONE = BIT(9), + MFC_DUMP_ENC_NAL_START = BIT(10), + MFC_DUMP_ENC_FRAME_DONE = BIT(11), + MFC_DUMP_MOVE_INSTANCE_RET = BIT(12), + MFC_DUMP_UNKNOWN_INT = BIT(13), + MFC_DUMP_DEC_SEQ_DONE = BIT(15), + MFC_DUMP_DEC_INIT_BUF_DONE = BIT(16), + MFC_DUMP_DEC_FIRST_FRAME_DONE = BIT(17), + MFC_DUMP_ENC_SEQ_DONE = BIT(18), + MFC_DUMP_ENC_INIT_BUF_DONE = BIT(19), + MFC_DUMP_ENC_FIRST_FRAME_DONE = BIT(20), + MFC_DUMP_DEC_CRC = BIT(29), + MFC_DUMP_FIRMWARE = BIT(30), + MFC_DUMP_ALL_INFO = BIT(31), +}; + +enum mfc_logging_option { + MFC_LOGGING_NONE = 0, + MFC_LOGGING_PRINTK = BIT(0), + MFC_LOGGING_MEMLOG_PRINTF = BIT(1), + MFC_LOGGING_MEMLOG_SFR_DUMP = BIT(2), + MFC_LOGGING_MEMLOG = (BIT(1) | BIT(2)), + MFC_LOGGING_ALL = 0x7, +}; + +enum mfc_feature_option { + MFC_OPTION_NONE = 0, + MFC_OPTION_RECON_SBWC_DISABLE = BIT(0), + MFC_OPTION_DECODING_ORDER = BIT(1), + MFC_OPTION_MEERKAT_DISABLE = BIT(2), + MFC_OPTION_OTF_PATH_TEST_ENABLE = BIT(3), + MFC_OPTION_MULTI_CORE_DISABLE = BIT(4), + MFC_OPTION_SET_MULTI_CORE_FORCE = BIT(5), + MFC_OPTION_BLACK_BAR_ENABLE = BIT(6), + MFC_OPTION_DEC_ENC_SBWC_ENABLE = BIT(7), + MFC_OPTION_DYNAMIC_QOS_DISABLE = BIT(8), + MFC_OPTION_USE_FIXED_WEIGHT = BIT(9), + MFC_OPTION_FPS_SBWC_ENABLE = BIT(10), + MFC_OPTION_FILMGRAIN_DISABLE = BIT(11), + MFC_OPTION_SW_MEMCPY_PLUGIN = BIT(12), + MFC_OPTION_INTER_SBWC_DISABLE = BIT(13), + MFC_OPTION_MSR_ENABLE = BIT(14), + MFC_OPTION_STREAM_COPY_DISABLE = BIT(15), +}; + +enum mfc_get_img_size { + MFC_GET_RESOL_SIZE = 0, + MFC_GET_RESOL_DPB_SIZE = 1, +}; + +enum mfc_color_space { + MFC_COLORSPACE_UNSPECIFICED = 0, + MFC_COLORSPACE_BT601 = 1, + MFC_COLORSPACE_BT709 = 2, + MFC_COLORSPACE_SMPTE_170 = 3, + MFC_COLORSPACE_SMPTE_240 = 4, + MFC_COLORSPACE_BT2020 = 5, + MFC_COLORSPACE_RESERVED = 6, + MFC_COLORSPACE_SRGB = 7, +}; + +enum mfc_color_primaries { + MFC_PRIMARIES_RESERVED = 0, + MFC_PRIMARIES_BT709_5 = 1, + MFC_PRIMARIES_UNSPECIFIED = 2, + MFC_PRIMARIES_BT470_6M = 4, + MFC_PRIMARIES_BT601_6_625 = 5, + MFC_PRIMARIES_BT601_6_525 = 6, + MFC_PRIMARIES_SMPTE_240M = 7, + MFC_PRIMARIES_GENERIC_FILM = 8, + MFC_PRIMARIES_BT2020 = 9, + MFC_PRIMARIES_EG432 = 12, +}; + +enum mfc_transfer_characteristics { + MFC_TRANSFER_RESERVED = 0, + MFC_TRANSFER_BT709 = 1, + MFC_TRANSFER_UNSPECIFIED = 2, + /* RESERVED = 3, */ + MFC_TRANSFER_GAMMA_22 = 4, + MFC_TRANSFER_GAMMA_28 = 5, + MFC_TRANSFER_SMPTE_170M = 6, + MFC_TRANSFER_SMPTE_240M = 7, + MFC_TRANSFER_LINEAR = 8, + MFC_TRANSFER_LOGARITHMIC = 9, + MFC_TRANSFER_LOGARITHMIC_S = 10, + MFC_TRANSFER_XvYCC = 11, + MFC_TRANSFER_BT1361 = 12, + MFC_TRANSFER_SRGB = 13, + MFC_TRANSFER_BT2020_1 = 14, + MFC_TRANSFER_BT2020_2 = 15, + MFC_TRANSFER_ST2084 = 16, + MFC_TRANSFER_ST428 = 17, + MFC_TRANSFER_HLG = 18, +}; + +enum mfc_matrix_coeff { + MFC_MATRIX_COEFF_IDENTITY = 0, + MFC_MATRIX_COEFF_REC709 = 1, + MFC_MATRIX_COEFF_UNSPECIFIED = 2, + MFC_MATRIX_COEFF_RESERVED = 3, + MFC_MATRIX_COEFF_470_SYSTEM_M = 4, + MFC_MATRIX_COEFF_470_SYSTEM_BG = 5, + MFC_MATRIX_COEFF_SMPTE170M = 6, + MFC_MATRIX_COEFF_SMPTE240M = 7, + MFC_MATRIX_COEFF_BT2020 = 9, + MFC_MATRIX_COEFF_BT2020_CONSTANT = 10, +}; + +struct mfc_debugfs { + struct dentry *root; + unsigned int debug_level; + unsigned int debug_ts; + unsigned int debug_mode_en; + unsigned int dbg_enable; + unsigned int sfr_dump; + unsigned int logging_option; + unsigned int feature_option; + unsigned int sched_perf_disable; + unsigned int sched_type; +}; + +/** + * struct mfc_special_buf - represents internal used buffer + * @daddr: device virtual address + * @iova: device virtual address allocated to the reserved address for F/W, + * it only used for specific internal buffer + * @virt: kernel virtual address, only valid when the + * buffer accessed by driver + * @priv_data: special purpose private data required for each buffer. + * - internal_dpb: timestamp + */ +struct mfc_special_buf { + enum mfc_buf_usage_type buftype; + struct dma_buf *dma_buf; + struct dma_buf_attachment *attachment; + struct sg_table *sgt; + dma_addr_t daddr; + dma_addr_t iova; + phys_addr_t paddr; + void *vaddr; + size_t size; + size_t map_size; + struct cma *cma_area; + char name[MFC_NUM_SPECIAL_BUF_NAME]; + u64 priv_data; + struct iosys_map map; +}; + +struct mfc_mem { + struct list_head list; + dma_addr_t addr; + size_t size; +}; + +struct mfc_feature { + unsigned int support; + unsigned int version; +}; + +struct mfc_resource { + enum mfc_op_core_type op_core_type; + int max_kbps; +}; + +struct mfc_platdata { + /* Debug mode */ + unsigned int debug_mode; + + /* Resource */ + struct mfc_resource mfc_resource[MFC_MAX_CODEC_TYPE]; + /* Features */ + struct mfc_feature mem_clear; + struct mfc_feature wait_fw_status; + + const char *fw_name; + unsigned int fw_mem_size; + unsigned int reserved_start; + unsigned int dma_bit_mask; + unsigned int ip_ver; + unsigned int iova_threshold; + + unsigned int memlog_size; + + unsigned int scheduler; + unsigned int pbs_num_prio; + enum mfc_hwacg_type support_hwacg; +}; + +struct mfc_core_platdata { + /* MFC version */ + unsigned int ip_ver; + /* Sysmmu check */ + unsigned int share_sysmmu; + unsigned int fault_status; + unsigned int fault_info1; + unsigned int axid_mask; + unsigned int mfc_axid; + unsigned int tsmux_axid; + unsigned int fault_info2; + unsigned int pmmuid_shift; + unsigned int pmmuid_mask; + unsigned int tsmux_pmmuid; + unsigned int masterid_shift; + unsigned int masterid_mask; + unsigned int tsmux_masterid; +}; + +struct mfc_dev_memlog { + unsigned int log_enable; +}; + +struct mfc_core_memlog { + unsigned int sfr_enable; +}; + +/** + * struct mfc_dev - The struct containing driver internal parameters. + */ +struct mfc_dev { + struct mfc_core *core[MFC_NUM_CORE]; + struct mfc_core *plugin; + int num_core; + int num_subsystem; + int fw_date; + int fw_changed_info; + size_t fw_rmem_offset; + + struct device *device; + struct device *mem_dev[BANK_NUM]; + struct device *cache_op_dev; + struct v4l2_device v4l2_dev; + struct video_device *vfd_dec; + struct video_device *vfd_enc; + + struct mfc_platdata *pdata; + struct mfc_variant *variant; + + struct iommu_domain *domain; + struct gen_pool *iova_pool; + + int num_inst; + int num_dec_inst; + int num_enc_inst; + + unsigned long multi_core_inst_bits; + + /* protection */ + struct mutex mfc_mutex; + + struct mfc_ctx *ctx[MFC_NUM_CONTEXTS]; + struct mfc_ctx *move_ctx[MFC_NUM_CONTEXTS]; + dma_addr_t dma_base[BANK_NUM]; + + struct list_head ctx_list; + /* protection */ + spinlock_t ctx_list_lock; + + atomic_t queued_bits; + /* protection */ + spinlock_t idle_bits_lock; + + /* Trace */ + atomic_t trace_ref; + struct _mfc_trace *mfc_trace; + atomic_t trace_ref_longterm; + struct _mfc_trace *mfc_trace_longterm; + atomic_t trace_ref_rm; + struct _mfc_trace *mfc_trace_rm; + + /* Debugfs and dump */ + struct mfc_debugfs debugfs; + + struct mfc_dev_memlog memlog; + +}; + +struct mfc_core_ops { + int (*instance_init)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_deinit)(struct mfc_core *core, struct mfc_ctx *ctx); +}; + +struct dump_info { + char *name; + void *addr; + u64 size; +}; + +struct mfc_core { + struct device *device; + struct iommu_domain *domain; + + const struct mfc_core_ops *core_ops; + + void __iomem *regs_base; + void __iomem *sysmmu0_base; + void __iomem *sysmmu1_base; + void __iomem *pmu_base; + void __iomem *cmu_busc_base; + void __iomem *cmu_mif0_base; + void __iomem *cmu_mif1_base; + void __iomem *cmu_mif2_base; + void __iomem *cmu_mif3_base; + + unsigned int id; + char name[10]; + int irq; + struct resource *mfc_mem; + + struct mfc_variant *variant; + struct mfc_core_platdata *core_pdata; + + struct mfc_sched_class *sched; + enum mfc_sched_type sched_type; + + enum mfc_core_state state; + + bool has_2sysmmu; + bool has_cmu; + bool has_pmu; + + /* Power and Clock */ + atomic_t clk_ref; + struct mfc_pm pm; + bool continue_clock_on; + bool sleep; + bool shutdown; + + /* Internal buffers */ + struct mfc_fw fw; + struct mfc_special_buf fw_buf; + struct mfc_special_buf common_ctx_buf; + struct mfc_special_buf dbg_info_buf; + + /* Context information */ + struct mfc_dev *dev; + struct mfc_core_ctx *core_ctx[MFC_NUM_CONTEXTS]; + int curr_core_ctx; + int preempt_core_ctx; + int num_inst; + + int int_condition; + int int_reason; + unsigned int int_err; + + /* PBS */ + int num_prio; + int total_num_prio; + unsigned long prio_work_bits[MFC_MAX_PRIO]; + /* protection */ + spinlock_t prio_work_lock; + int last_core_ctx[MFC_MAX_PRIO]; + int max_runtime; + int next_ctx_idx; + + /* HW lock */ + struct mfc_hwlock hwlock; + struct mfc_listable_wq hwlock_wq; + wait_queue_head_t cmd_wq; + + /* batch mode */ + int batch_enable; + int batch_index; + /* protection */ + spinlock_t batch_lock; + + /* QoS idle */ + atomic_t hw_run_bits; + /* protection */ + struct mutex idle_qos_mutex; + enum mfc_idle_mode idle_mode; + struct timer_list mfc_idle_timer; + struct workqueue_struct *mfc_idle_wq; + struct work_struct mfc_idle_work; + + /* for DRM */ + int cache_flush_flag; + int last_cmd_has_cache_flush; + + /* QoS */ + struct list_head qos_queue; + atomic_t qos_req_cur; + + /* protection */ + struct mutex qos_mutex; + int mfc_freq_by_bps; + int last_mfc_freq; + int last_table_type; + unsigned long total_mb; + unsigned int cpu_boost_enable; + + /* Logging trace data */ + atomic_t trace_ref_log; + struct _mfc_trace_logging *mfc_trace_logging; + struct mfc_debug *logging_data; + int last_cmd; + int last_int; + struct timespec64 last_cmd_time; + struct timespec64 last_int_time; + + /* debug info dump */ + struct dump_info dbg_info; + + /* Debug */ + struct mfc_core_memlog memlog; +}; + +struct mfc_ctx_ctrl_val { + int has_new; + int val; +}; + +struct mfc_ctx_ctrl { + struct list_head list; + unsigned int id; + unsigned int addr; + struct mfc_ctx_ctrl_val set; + struct mfc_ctx_ctrl_val get; +}; + +struct mfc_buf_ctrl { + struct list_head list; + unsigned int id; + int has_new; + int val; + unsigned int old_val; /* only for MFC_CTRL_TYPE_SET */ + unsigned int old_val2; /* only for MFC_CTRL_TYPE_SET */ + unsigned int is_volatile; /* only for MFC_CTRL_TYPE_SET */ + unsigned int updated; + unsigned int mode; + unsigned int addr; + unsigned int mask; + unsigned int shft; + unsigned int flag_mode; /* only for MFC_CTRL_TYPE_SET */ + unsigned int flag_addr; /* only for MFC_CTRL_TYPE_SET */ + unsigned int flag_shft; /* only for MFC_CTRL_TYPE_SET */ +}; + +struct mfc_ctrl_cfg { + unsigned int id; + unsigned int is_volatile; /* only for MFC_CTRL_TYPE_SET */ + unsigned int mode; + unsigned int addr; + unsigned int mask; + unsigned int shft; + unsigned int flag_mode; /* only for MFC_CTRL_TYPE_SET */ + unsigned int flag_addr; /* only for MFC_CTRL_TYPE_SET */ + unsigned int flag_shft; /* only for MFC_CTRL_TYPE_SET */ +}; + +struct mfc_user_shared_handle { + int fd; + struct dma_buf *dma_buf; + void *vaddr; + size_t data_size; +}; + +struct mfc_raw_info { + int num_planes; + int stride[3]; + int plane_size[3]; + int stride_2bits[3]; + int plane_size_2bits[3]; + unsigned int total_plane_size; +}; + +struct dpb_table { + dma_addr_t addr[MFC_MAX_PLANES]; + phys_addr_t paddr; + size_t size; + int fd[MFC_MAX_PLANES]; + int new_fd; /* it means first plane only */ + int mapcnt; + int ref; + int queued; + struct dma_buf *dmabufs[MFC_MAX_PLANES]; + struct dma_buf_attachment *attach[MFC_MAX_PLANES]; + struct sg_table *sgt[MFC_MAX_PLANES]; +}; + +struct mfc_fmt { + char *name; + u32 fourcc; + u32 codec_mode; + u32 type; + u32 num_planes; + u32 mem_planes; +}; + +enum mfc_multi_view_buf_idx { + MFC_MV_BUF_IDX_VIEW0 = 0, + MFC_MV_BUF_IDX_VIEW0_DEPTH, + MFC_MV_BUF_IDX_VIEW1, + MFC_MV_BUF_IDX_VIEW1_DEPTH, + MFC_MV_BUF_IDX_VIEW1_META, + /* the number of index */ + MFC_MV_BUF_IDX_MAX, +}; + +/** + * struct mfc_ctx - This struct contains the instance context + */ +struct mfc_ctx { + struct mfc_dev *dev; + + int num; + int prio; + int user_prio; + enum mfc_real_time rt; + + enum mfc_inst_type type; + + /* operation mode */ + int op_core_num[MFC_NUM_CORE]; + int move_core_num[MFC_NUM_CORE]; + enum mfc_op_mode stream_op_mode; + enum mfc_op_mode op_mode; + enum mfc_op_core_type op_core_type; + struct mfc_core_lock corelock; + + /* protection */ + struct mutex op_mode_mutex; + int last_op_core; + + /* interrupt lock */ + struct mfc_core_intlock intlock; + + /* Control values */ + int codec_mode; + __u32 pix_format; + + int is_heif_mode; + + int is_dpb_realloc; + /* protection */ + int clear_work_bit; + + /* Extra Buffers */ + int mv_buffer_allocated; + struct mfc_special_buf mv_buf; + + unsigned long framerate; + + /* bitrate control for QoS*/ + struct list_head bitrate_list; + int bitrate_index; + int bitrate_is_full; + int kbps; + int last_bps_section; + int load; + unsigned long weighted_mb; + struct list_head list; + + int disp_ratio; + + int buf_process_type; + + int frame_cnt; + dma_addr_t last_src_addr; + dma_addr_t last_dst_addr[MFC_MAX_PLANES]; + + bool mem_type_10bit; + + unsigned long gdc_ready_buf_ino; + /* protection */ + spinlock_t gdc_lock; + + /* QoS idle */ + enum mfc_idle_mode idle_mode; + + /* external structure */ + struct v4l2_fh fh; + struct vb2_queue vq_src; + struct vb2_queue vq_dst; + + u32 ready_to_be_multi_view_enable; + u32 multi_view_enable; + u32 left_view_id; + + /* DRC (Display Resolution Change) */ + u32 handle_drc_multi_mode; +}; + +struct mfc_core_ctx { + struct mfc_core *core; + struct mfc_ctx *ctx; + + int num; + int inst_no; + int int_condition; + int int_reason; + unsigned int int_err; + bool check_dump; + + enum mfc_inst_state state; + enum mfc_inst_state prev_state; + + /* Extra Buffers */ + struct mfc_special_buf instance_ctx_buf; + + /* wait queue */ + wait_queue_head_t cmd_wq; + + struct mfc_listable_wq hwlock_wq; +}; + +struct mfc_sched_class { + void (*create_work)(struct mfc_core *core); + void (*init_work)(struct mfc_core *core); + void (*clear_all_work)(struct mfc_core *core); + void (*set_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); + void (*clear_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); +}; +#endif /* __MFC_DATA_STRUCT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h new file mode 100644 index 000000000000..02a6a0bbbceb --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_debug.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_DEBUG_H +#define __MFC_DEBUG_H __FILE__ + +#define DEBUG + +#ifdef DEBUG + +#define mfc_debug(level, fmt, args...) \ + do { \ + if ((core_ctx->core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) && \ + core_ctx->core->dev->debugfs.debug_level >= (level)) \ + dev_info(core_ctx->core->device, "[c:%d] %s:%d: " fmt,\ + core_ctx->num, __func__, __LINE__, ##args); \ + } while (0) + +#define mfc_ctx_debug(level, fmt, args...) \ + do { \ + if ((ctx->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) && \ + ctx->dev->debugfs.debug_level >= (level)) \ + dev_info(ctx->dev->device, "[c:%d] %s:%d: " fmt, \ + ctx->num, __func__, __LINE__, ##args); \ + } while (0) + +#define mfc_core_debug(level, fmt, args...) \ + do { \ + if ((core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) && \ + core->dev->debugfs.debug_level >= (level)) \ + dev_info(core->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + } while (0) + +#define mfc_dev_debug(level, fmt, args...) \ + do { \ + if ((dev->debugfs.logging_option & MFC_LOGGING_PRINTK) && \ + dev->debugfs.debug_level >= (level)) \ + dev_info(dev->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + } while (0) + +#else +#define mfc_debug(fmt, args...) +#define mfc_ctx_debug(fmt, args...) +#define mfc_core_debug(fmt, args...) +#define mfc_dev_debug(fmt, args...) +#endif + +#define mfc_debug_enter() mfc_debug(5, "enter\n") +#define mfc_debug_leave() mfc_debug(5, "leave\n") +#define mfc_ctx_debug_enter() mfc_ctx_debug(5, "enter\n") +#define mfc_ctx_debug_leave() mfc_ctx_debug(5, "leave\n") +#define mfc_core_debug_enter() mfc_core_debug(5, "enter\n") +#define mfc_core_debug_leave() mfc_core_debug(5, "leave\n") +#define mfc_dev_debug_enter() mfc_dev_debug(5, "enter\n") +#define mfc_dev_debug_leave() mfc_dev_debug(5, "leave\n") + +/* ERROR */ +#define mfc_pr_err(fmt, args...) \ + pr_err("[Exynos][MFC][ ERROR]: %s:%d: " fmt, __func__, __LINE__, ##args) + +#define mfc_dev_err(fmt, args...) \ + do { \ + if (dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_err(dev->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_core_err(fmt, args...) \ + do { \ + if (core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_err(core->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_ctx_err(fmt, args...) \ + do { \ + if (ctx->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_err(ctx->dev->device, \ + "[c:%d] %s:%d: " fmt, \ + ctx->num, __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_err(fmt, args...) \ + do { \ + if (core_ctx->core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_err(core_ctx->core->device, \ + "[c:%d] %s:%d: " fmt, \ + core_ctx->num, __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_dev_info(fmt, args...) \ + do { \ + if (dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_info(dev->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_core_info(fmt, args...) \ + do { \ + if (core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_info(core->device, "%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + \ + } while (0) + +#define mfc_ctx_info(fmt, args...) \ + do { \ + if (ctx->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_info(ctx->dev->device, \ + "[c:%d] %s:%d: " fmt, \ + ctx->num, __func__, __LINE__, ##args); \ + } while (0) + +#define mfc_info(fmt, args...) \ + do { \ + if (core_ctx->core->dev->debugfs.logging_option & MFC_LOGGING_PRINTK) \ + dev_info(core_ctx->core->device, \ + "[c:%d] %s:%d: " fmt, \ + core_ctx->num, __func__, __LINE__, ##args); \ + } while (0) + +#define MFC_TRACE_STR_LEN 80 +#define MFC_TRACE_COUNT_MAX 1024 +#define MFC_TRACE_COUNT_PRINT 50 +#define MFC_TRACE_COUNT_PRINT_LONG 100 +#define MFC_TRACE_LOG_STR_LEN 25 +#define MFC_TRACE_LOG_COUNT_MAX 256 +#define MFC_TRACE_LOG_COUNT_PRINT 20 + +#define MFC_DUMP_BUF_SIZE SZ_6M + +struct _mfc_trace { + unsigned long long time; + char str[MFC_TRACE_STR_LEN]; +}; + +struct _mfc_trace_logging { + unsigned long long time; + char str[MFC_TRACE_LOG_STR_LEN]; +}; + +/* If there is no core structure */ +#define MFC_TRACE_DEV(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&dev->trace_ref) & (MFC_TRACE_COUNT_MAX - 1); \ + dev->mfc_trace[cnt].time = cpu_clock(cpu); \ + snprintf(dev->mfc_trace[cnt].str, MFC_TRACE_STR_LEN, \ + fmt, ##args); \ + } while (0) + +/* If there is core structure */ +#define MFC_TRACE_CORE(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&core->dev->trace_ref) & (MFC_TRACE_COUNT_MAX - 1); \ + core->dev->mfc_trace[cnt].time = cpu_clock(cpu); \ + snprintf(core->dev->mfc_trace[cnt].str, MFC_TRACE_STR_LEN, \ + "[MFC%d] "fmt, core->id, ##args); \ + } while (0) + +/* If there is ctx structure */ +#define MFC_TRACE_CTX(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&ctx->dev->trace_ref) & (MFC_TRACE_COUNT_MAX - 1); \ + ctx->dev->mfc_trace[cnt].time = cpu_clock(cpu); \ + snprintf(ctx->dev->mfc_trace[cnt].str, MFC_TRACE_STR_LEN, \ + "[c:%d] " fmt, ctx->num, ##args); \ + } while (0) + +/* If there is core_ctx structure */ +#define MFC_TRACE_CORE_CTX(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&core_ctx->core->dev->trace_ref) & \ + (MFC_TRACE_COUNT_MAX - 1); \ + core_ctx->core->dev->mfc_trace[cnt].time = cpu_clock(cpu); \ + snprintf(core_ctx->core->dev->mfc_trace[cnt].str, MFC_TRACE_STR_LEN, \ + "[MFC%d][c:%d] " fmt, core_ctx->core->id, \ + core_ctx->num, ##args); \ + } while (0) + +/* If there is no ctx structure */ +#define MFC_TRACE_DEV_LT(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&dev->trace_ref_longterm) & (MFC_TRACE_COUNT_MAX - 1); \ + dev->mfc_trace_longterm[cnt].time = cpu_clock(cpu); \ + snprintf(dev->mfc_trace_longterm[cnt].str, MFC_TRACE_STR_LEN, \ + fmt, ##args); \ + } while (0) + +/* If there is ctx structure */ +#define MFC_TRACE_CTX_LT(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&ctx->dev->trace_ref_longterm) & \ + (MFC_TRACE_COUNT_MAX - 1); \ + ctx->dev->mfc_trace_longterm[cnt].time = cpu_clock(cpu); \ + snprintf(ctx->dev->mfc_trace_longterm[cnt].str, MFC_TRACE_STR_LEN, \ + "[c:%d] " fmt, ctx->num, ##args); \ + } while (0) + +/* If there is core structure */ +#define MFC_TRACE_LOG_CORE(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&core->trace_ref_log) & (MFC_TRACE_LOG_COUNT_MAX - 1); \ + core->mfc_trace_logging[cnt].time = cpu_clock(cpu); \ + snprintf(core->mfc_trace_logging[cnt].str, MFC_TRACE_LOG_STR_LEN, \ + fmt, ##args); \ + } while (0) + +/* Resource manager dedicated */ +#define MFC_TRACE_RM(fmt, args...) \ + do { \ + int cpu = raw_smp_processor_id(); \ + int cnt; \ + cnt = atomic_inc_return(&dev->trace_ref_rm) & (MFC_TRACE_COUNT_MAX - 1); \ + dev->mfc_trace_rm[cnt].time = cpu_clock(cpu); \ + snprintf(dev->mfc_trace_rm[cnt].str, MFC_TRACE_STR_LEN, \ + fmt, ##args); \ + } while (0) +#endif /* __MFC_DEBUG_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035531epcas5p22f3bc84d7e1f3bce78459f4f159e3d1a@epcas5p2.samsung.com>]
* [PATCH 04/29] media: mfc: Add full register map and bit definitions for MFC hardware [not found] ` <CGME20250930035531epcas5p22f3bc84d7e1f3bce78459f4f159e3d1a@epcas5p2.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce mfc_regs_mfc.h header Define all MFC register addresses, including common, decoder, encoder, and NAL queue registers. Provide bit‑field masks and shifts for command/status registers, codec types, error codes, and feature flags. Add detailed comments for each register group and macro to improve readability and maintainability. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_regs_mfc.h | 1002 +++++++++++++++++ 1 file changed, 1002 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h new file mode 100644 index 000000000000..d10d3fb478ef --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h @@ -0,0 +1,1002 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_batch.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_REGS_MFC_H +#define __MFC_REGS_MFC_H __FILE__ + +#define MFC_MMU_INTERRUPT_STATUS 0x0060 +#define MFC_MMU_FAULT_TRANS_INFO 0x0078 +#define MFC_MMU_FAULT_TRANS_INFO_RW_MASK 0x100000 + +/* Codec Common Registers */ +#define MFC_REG_RISC_ON 0x0000 +#define MFC_REG_RISC2HOST_INT 0x003C +#define MFC_REG_RISC_STATUS 0x0040 +#define MFC_REG_HOST2RISC_INT 0x0044 +#define MFC_REG_RISC_BASE_ADDRESS 0x0054 +#define MFC_REG_RISC_NONSECURE_BASE_ADDR 0x0068 +#define MFC_REG_FW1_BASE_ADDR 0x1000 + +#define MFC_REG_MFC_FW_CLOCK 0x1060 +#define MFC_REG_MFC_RESET 0x1070 + +#define MFC_REG_HOST2RISC_CMD 0x1100 +#define MFC_REG_RISC2HOST_CMD 0x1104 + +#define MFC_REG_HWAPG_HOST_CTRL 0x11D8 + +#define MFC_REG_MFC_BUS_STATUS 0x7018 +#define MFC_REG_MFC_RPEND 0x7028 +#define MFC_REG_MFC_WPEND 0x702C +#define MFC_REG_MFC_BUS_RESET_CTRL 0x7110 +#define MFC_REG_MFC_OFF 0x7120 +#define MFC_REG_MFC_STATE 0x7124 + +#define MFC_REG_FW_VERSION 0xF000 +#define MFC_REG_INSTANCE_ID 0xF008 +#define MFC_REG_CODEC_TYPE 0xF00C +#define MFC_REG_CONTEXT_MEM_ADDR 0xF014 +#define MFC_REG_CONTEXT_MEM_SIZE 0xF018 +#define MFC_REG_SHARED_MEM_ADDR 0xF01C +#define MFC_REG_PIXEL_FORMAT 0xF020 + +#define MFC_REG_METADATA_ENABLE 0xF024 +#define MFC_REG_MFC_VERSION 0xF028 +#define MFC_REG_DBG_INFO_ENABLE 0xF02C +#define MFC_REG_DBG_BUFFER_ADDR 0xF030 +#define MFC_REG_DBG_BUFFER_SIZE 0xF034 + +#define MFC_REG_CODEC_CONTROL 0xF038 +#define MFC_REG_TIMEOUT_VALUE 0xF03C +#define MFC_REG_HED_SHARED_MEM_ADDR 0xF040 + +/* NAL QUEUE */ +#define MFC_REG_NAL_QUEUE_INPUT_ADDR 0xF044 +#define MFC_REG_NAL_QUEUE_INPUT_SIZE 0xF048 +#define MFC_REG_NAL_QUEUE_OUTPUT_ADDR 0xF04C +#define MFC_REG_NAL_QUEUE_OUTPUT_SIZE 0xF050 +#define MFC_REG_NAL_QUEUE_INPUT_COUNT 0xF054 + +#define MFC_REG_RET_INSTANCE_ID 0xF070 +#define MFC_REG_ERROR_CODE 0xF074 +#define MFC_REG_DBG_BUFFER_OUTPUT_SIZE 0xF078 +#define MFC_REG_METADATA_STATUS 0xF07C + +#define MFC_REG_DBG_INFO_STAGE_COUNTER 0xF088 + +/* NAL QUEUE */ +#define MFC_REG_NAL_QUEUE_OUTPUT_COUNT 0xF08C +#define MFC_REG_NAL_QUEUE_INPUT_EXE_COUNT 0xF090 +#define MFC_REG_NAL_QUEUE_INFO 0xF094 +#define MFC_REG_NAL_LL_IN_USE_BY_MFC 0xF098 +#define MFC_REG_NAL_LL_IN_USE_BY_DRV 0xF09C +#define MFC_REG_NAL_LL_TURN 0xF0A0 + +#define MFC_REG_FIRMWARE_STATUS_INFO 0xF0A4 +#define MFC_REG_PROCESSING_CYCLE 0xF0AC + +/* Decoder Registers */ +#define MFC_REG_D_CRC_CTRL 0xF0B0 +#define MFC_REG_D_DEC_OPTIONS 0xF0B4 + +#define MFC_REG_D_DISPLAY_DELAY 0xF0B8 + +#define MFC_REG_D_SET_FRAME_WIDTH 0xF0BC +#define MFC_REG_D_SET_FRAME_HEIGHT 0xF0C0 + +#define MFC_REG_D_SEI_ENABLE 0xF0C4 + +#define MFC_REG_D_FORCE_PIXEL_VAL 0xF0C8 + +/* Buffer setting registers */ +/* Session return */ +#define MFC_REG_D_MIN_NUM_DPB 0xF0F0 +#define MFC_REG_D_MIN_FIRST_PLANE_DPB_SIZE 0xF0F4 +#define MFC_REG_D_MIN_SECOND_PLANE_DPB_SIZE 0xF0F8 +#define MFC_REG_D_MIN_THIRD_PLANE_DPB_SIZE 0xF0FC +#define MFC_REG_D_MIN_NUM_MV 0xF100 +#define MFC_REG_D_MVC_NUM_VIEWS 0xF104 +#define MFC_REG_D_MIN_SCRATCH_BUFFER_SIZE 0xF108 +#define MFC_REG_D_MIN_FIRST_PLANE_2BIT_DPB_SIZE 0xF10C +#define MFC_REG_D_MIN_SECOND_PLANE_2BIT_DPB_SIZE 0xF110 +#define MFC_REG_D_POST_FILTER_LUMA_DPB0 0xF120 +#define MFC_REG_D_POST_FILTER_LUMA_DPB1 0xF124 +#define MFC_REG_D_POST_FILTER_CHROMA_DPB0 0xF128 +#define MFC_REG_D_POST_FILTER_CHROMA_DPB1 0xF12C + +/* Buffers */ +#define MFC_REG_D_NUM_DPB 0xF130 +#define MFC_REG_D_NUM_MV 0xF134 +#define MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE 0xF138 +#define MFC_REG_D_SECOND_PLANE_DPB_STRIDE_SIZE 0xF13C +#define MFC_REG_D_THIRD_PLANE_DPB_STRIDE_SIZE 0xF140 +#define MFC_REG_D_FIRST_PLANE_DPB_SIZE 0xF144 +#define MFC_REG_D_SECOND_PLANE_DPB_SIZE 0xF148 +#define MFC_REG_D_THIRD_PLANE_DPB_SIZE 0xF14C +#define MFC_REG_D_MV_BUFFER_SIZE 0xF150 +#define MFC_REG_D_INIT_BUFFER_OPTIONS 0xF154 +#define MFC_REG_D_FIRST_PLANE_DPB0 0xF160 +#define MFC_REG_D_SECOND_PLANE_DPB0 0xF260 +#define MFC_REG_D_THIRD_PLANE_DPB0 0xF360 +#define MFC_REG_D_MV_BUFFER0 0xF460 +#define MFC_REG_D_SCRATCH_BUFFER_ADDR 0xF560 +#define MFC_REG_D_SCRATCH_BUFFER_SIZE 0xF564 +#define MFC_REG_D_METADATA_BUFFER_ADDR 0xF568 +#define MFC_REG_D_METADATA_BUFFER_SIZE 0xF56C + +#define MFC_REG_D_STATIC_BUFFER_ADDR 0xF570 +#define MFC_REG_D_STATIC_BUFFER_SIZE 0xF574 +#define MFC_REG_D_FIRST_PLANE_2BIT_DPB_SIZE 0xF578 +#define MFC_REG_D_SECOND_PLANE_2BIT_DPB_SIZE 0xF57C +#define MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE 0xF580 +#define MFC_REG_D_SECOND_PLANE_2BIT_DPB_STRIDE_SIZE 0xF584 + +#define MFC_REG_D_NAL_START_OPTIONS 0xF5AC + +/* Nal cmd */ +#define MFC_REG_D_CPB_BUFFER_ADDR 0xF5B0 +#define MFC_REG_D_CPB_BUFFER_SIZE 0xF5B4 +#define MFC_REG_D_AVAILABLE_DPB_FLAG_UPPER 0xF5B8 +#define MFC_REG_D_AVAILABLE_DPB_FLAG_LOWER 0xF5BC +#define MFC_REG_D_CPB_BUFFER_OFFSET 0xF5C0 +#define MFC_REG_D_SLICE_IF_ENABLE 0xF5C4 +#define MFC_REG_D_PICTURE_TAG 0xF5C8 +#define MFC_REG_D_STREAM_DATA_SIZE 0xF5D0 +#define MFC_REG_D_DYNAMIC_DPB_FLAG_UPPER 0xF5D4 +#define MFC_REG_D_DYNAMIC_DPB_FLAG_LOWER 0xF5D8 + +/* Nal return */ +#define MFC_REG_D_DISPLAY_FRAME_WIDTH 0xF600 +#define MFC_REG_D_DISPLAY_FRAME_HEIGHT 0xF604 +#define MFC_REG_D_DISPLAY_STATUS 0xF608 +#define MFC_REG_D_DISPLAY_FIRST_PLANE_ADDR 0xF60C +#define MFC_REG_D_DISPLAY_SECOND_PLANE_ADDR 0xF610 +#define MFC_REG_D_DISPLAY_THIRD_PLANE_ADDR 0xF614 +#define MFC_REG_D_DISPLAY_FRAME_TYPE 0xF618 +#define MFC_REG_D_DISPLAY_CROP_INFO1 0xF61C +#define MFC_REG_D_DISPLAY_CROP_INFO2 0xF620 +#define MFC_REG_D_DISPLAY_PICTURE_PROFILE 0xF624 +#define MFC_REG_D_DISPLAY_FIRST_PLANE_CRC 0xF628 +#define MFC_REG_D_DISPLAY_SECOND_PLANE_CRC 0xF62C +#define MFC_REG_D_DISPLAY_THIRD_PLANE_CRC 0xF630 +#define MFC_REG_D_DISPLAY_ASPECT_RATIO 0xF634 +#define MFC_REG_D_DISPLAY_EXTENDED_AR 0xF638 +#define MFC_REG_D_DECODED_FRAME_WIDTH 0xF63C +#define MFC_REG_D_DECODED_FRAME_HEIGHT 0xF640 +#define MFC_REG_D_DECODED_STATUS 0xF644 +#define MFC_REG_D_DECODED_FIRST_PLANE_ADDR 0xF648 +#define MFC_REG_D_DECODED_SECOND_PLANE_ADDR 0xF64C +#define MFC_REG_D_DECODED_THIRD_PLANE_ADDR 0xF650 +#define MFC_REG_D_DECODED_FRAME_TYPE 0xF654 +#define MFC_REG_D_DECODED_CROP_INFO1 0xF658 +#define MFC_REG_D_DECODED_CROP_INFO2 0xF65C +#define MFC_REG_D_DECODED_PICTURE_PROFILE 0xF660 +#define MFC_REG_D_DECODED_NAL_SIZE 0xF664 +#define MFC_REG_D_DECODED_FIRST_PLANE_CRC 0xF668 +#define MFC_REG_D_DECODED_SECOND_PLANE_CRC 0xF66C +#define MFC_REG_D_DECODED_THIRD_PLANE_CRC 0xF670 +#define MFC_REG_D_RET_PICTURE_TAG_TOP 0xF674 +#define MFC_REG_D_RET_PICTURE_TAG_BOT 0xF678 +#define MFC_REG_D_RET_PICTURE_TIME_TOP 0xF67C +#define MFC_REG_D_RET_PICTURE_TIME_BOT 0xF680 +#define MFC_REG_D_CHROMA_FORMAT 0xF684 + +#define MFC_REG_D_VC1_INFO 0xF688 +#define MFC_REG_D_MPEG4_INFO 0xF68C +#define MFC_REG_D_H264_INFO 0xF690 +#define MFC_REG_D_HEVC_INFO 0xF6A0 +#define MFC_REG_D_VP9_INFO 0xF6A4 +#define MFC_REG_D_AV1_INFO 0xF6AC + +#define MFC_REG_D_METADATA_ADDR_CONCEALED_MB 0xF6B0 +#define MFC_REG_D_METADATA_SIZE_CONCEALED_MB 0xF6B4 +#define MFC_REG_D_METADATA_ADDR_VC1_PARAM 0xF6B8 +#define MFC_REG_D_METADATA_SIZE_VC1_PARAM 0xF6BC +#define MFC_REG_D_METADATA_ADDR_SEI_NAL 0xF6C0 +#define MFC_REG_D_METADATA_SIZE_SEI_NAL 0xF6C4 +#define MFC_REG_D_METADATA_ADDR_VUI 0xF6C8 +#define MFC_REG_D_METADATA_SIZE_VUI 0xF6CC +#define MFC_REG_D_METADATA_ADDR_MVCVUI 0xF6D0 +#define MFC_REG_D_METADATA_SIZE_MVCVUI 0xF6D4 + +#define MFC_REG_D_MVC_VIEW_ID 0xF6D8 + +#define MFC_REG_D_SEI_AVAIL 0xF6DC +#define MFC_REG_D_FRAME_PACK_ARRGMENT_ID 0xF6E0 +#define MFC_REG_D_FRAME_PACK_SEI_INFO 0xF6E4 +#define MFC_REG_D_FRAME_PACK_GRID_POS 0xF6E8 + +#define MFC_REG_D_DISPLAY_RECOVERY_SEI_INFO 0xF6EC +#define MFC_REG_D_DECODED_RECOVERY_SEI_INFO 0xF6F0 + +#define MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC 0xF6FC +#define MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC 0xF700 +#define MFC_REG_D_DECODED_FIRST_PLANE_2BIT_CRC 0xF704 +#define MFC_REG_D_DECODED_SECOND_PLANE_2BIT_CRC 0xF708 + +#define MFC_REG_D_VIDEO_SIGNAL_TYPE 0xF70C +#define MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI 0xF710 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xF714 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xF718 + +#define MFC_REG_D_USED_DPB_FLAG_UPPER 0xF720 +#define MFC_REG_D_USED_DPB_FLAG_LOWER 0xF724 + +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xF728 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xF72C +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xF730 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xF734 + +#define MFC_REG_D_BLACK_BAR_START_POS 0xF738 +#define MFC_REG_D_BLACK_BAR_IMAGE_SIZE 0xF73C + +#define MFC_REG_D_DECODED_FRAME_COUNT 0xF740 +#define MFC_REG_D_DISPLAY_FRAME_COUNT 0xF744 + +#define MFC_REG_D_DISPLAY_LUMA_ADDR 0xF60C +#define MFC_REG_D_DISPLAY_CHROMA_ADDR 0xF610 + +#define MFC_REG_D_DECODED_LUMA_ADDR 0xF648 +#define MFC_REG_D_DECODED_CHROMA_ADDR 0xF64C + +/* SEI NAL Metadata (reuse encoder register) */ +#define MFC_REG_D_PAYLOAD_TYPE 0xF770 +#define MFC_REG_D_PAYLOAD_SIZE 0xF774 +#define MFC_REG_D_PAYLOAD_DATA_0 0xF778 + +/* Encoder Registers */ +#define MFC_REG_E_CROPPED_FRAME_WIDTH 0xF778 +#define MFC_REG_E_CROPPED_FRAME_HEIGHT 0xF77C +#define MFC_REG_E_FRAME_CROP_OFFSET 0xF780 +#define MFC_REG_E_ENC_OPTIONS 0xF784 +#define MFC_REG_E_PICTURE_PROFILE 0xF788 +#define MFC_REG_E_VBV_BUFFER_SIZE 0xF78C +#define MFC_REG_E_VBV_INIT_DELAY 0xF790 +#define MFC_REG_E_FIXED_PICTURE_QP 0xF794 +#define MFC_REG_E_RC_CONFIG 0xF798 +#define MFC_REG_E_RC_QP_BOUND 0xF79C +#define MFC_REG_E_RC_QP_BOUND_PB 0xF7A0 +#define MFC_REG_E_RC_MODE 0xF7A4 + +#define MFC_REG_E_RC_OPTIONS 0xF7A8 +#define MFC_REG_E_PADDING_CTRL 0xF7AC +#define MFC_REG_E_AIR_THRESHOLD 0xF7B0 + +#define MFC_REG_E_MV_HOR_RANGE 0xF7B4 +#define MFC_REG_E_MV_VER_RANGE 0xF7B8 + +#define MFC_REG_E_HIGH_QUALITY_MODE 0xF7C0 +#define MFC_REG_E_VIDEO_SIGNAL_TYPE 0xF7C4 + +#define MFC_REG_E_SAO_WEIGHT0 0xF7C8 +#define MFC_REG_E_SAO_WEIGHT1 0xF7CC + +#define MFC_REG_E_NUM_DPB 0xF890 +#define MFC_REG_E_MIN_SCRATCH_BUFFER_SIZE 0xF894 +#define MFC_REG_E_MIN_LUMA_DPB_SIZE 0xF898 +#define MFC_REG_E_MIN_CHROMA_DPB_SIZE 0xF89C + +#define MFC_REG_E_LUMA_DPB 0xF8C0 +#define MFC_REG_E_CHROMA_DPB 0xF904 +#define MFC_REG_E_ME_BUFFER 0xF948 + +#define MFC_REG_E_SCRATCH_BUFFER_ADDR 0xF98C +#define MFC_REG_E_SCRATCH_BUFFER_SIZE 0xF990 +#define MFC_REG_E_TMV_BUFFER0 0xF994 +#define MFC_REG_E_TMV_BUFFER1 0xF998 +#define MFC_REG_E_IR_BUFFER_ADDR 0xF99C +#define MFC_REG_E_TILE1_STREAM_BUFFER_ADDR 0xF9A0 +#define MFC_REG_E_TILE1_STREAM_BUFFER_SIZE 0xF9A4 +#define MFC_REG_E_SOURCE_VOTF_BUF_INDEX 0xF9CC +#define MFC_REG_E_SOURCE_FIRST_2BIT_ADDR 0xF9D0 +#define MFC_REG_E_SOURCE_SECOND_2BIT_ADDR 0xF9D4 +#define MFC_REG_E_SOURCE_FIRST_2BIT_STRIDE 0xF9D8 +#define MFC_REG_E_SOURCE_SECOND_2BIT_STRIDE 0xF9DC +#define MFC_REG_E_SOURCE_FIRST_ADDR 0xF9E0 +#define MFC_REG_E_SOURCE_SECOND_ADDR 0xF9E4 +#define MFC_REG_E_SOURCE_THIRD_ADDR 0xF9E8 +#define MFC_REG_E_SOURCE_FIRST_STRIDE 0xF9EC +#define MFC_REG_E_SOURCE_SECOND_STRIDE 0xF9F0 +#define MFC_REG_E_SOURCE_THIRD_STRIDE 0xF9F4 +#define MFC_REG_E_STREAM_BUFFER_ADDR 0xF9F8 +#define MFC_REG_E_STREAM_BUFFER_SIZE 0xF9FC +#define MFC_REG_E_ROI_BUFFER_ADDR 0xFA00 + +#define MFC_REG_E_PARAM_CHANGE 0xFA04 +#define MFC_REG_E_IR_SIZE 0xFA08 +#define MFC_REG_E_GOP_CONFIG 0xFA0C +#define MFC_REG_E_MSLICE_MODE 0xFA10 +#define MFC_REG_E_MSLICE_SIZE_MB 0xFA14 +#define MFC_REG_E_MSLICE_SIZE_BITS 0xFA18 +#define MFC_REG_E_FRAME_INSERTION 0xFA1C + +#define MFC_REG_E_RC_FRAME_RATE 0xFA20 +#define MFC_REG_E_RC_BIT_RATE 0xFA24 +#define MFC_REG_E_RC_ROI_CTRL 0xFA2C +#define MFC_REG_E_PICTURE_TAG 0xFA30 +#define MFC_REG_E_BIT_COUNT_ENABLE 0xFA34 +#define MFC_REG_E_MAX_BIT_COUNT 0xFA38 +#define MFC_REG_E_MIN_BIT_COUNT 0xFA3C + +#define MFC_REG_E_METADATA_BUFFER_ADDR 0xFA40 +#define MFC_REG_E_METADATA_BUFFER_SIZE 0xFA44 + +#define MFC_REG_E_ENCODING_ORDER_TIME_INFO 0xFA50 +#define MFC_REG_E_ENCODING_ORDER_INFO 0xFA54 +#define MFC_REG_E_STREAM_BUFFER_OFFSET 0xFA58 +#define MFC_REG_E_GOP_CONFIG2 0xFA5C +#define MFC_REG_E_WEIGHT_FOR_WEIGHTED_PREDICTION 0xFA60 +#define MFC_REG_E_TIME_STAMP_DELTA 0xFA68 + +#define MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR 0xFA70 +#define MFC_REG_E_ENCODED_SOURCE_SECOND_ADDR 0xFA74 +#define MFC_REG_E_ENCODED_SOURCE_THIRD_ADDR 0xFA78 +#define MFC_REG_E_SOURCE_STAT_ADDR 0xFA7C +#define MFC_REG_E_STREAM_SIZE 0xFA80 +#define MFC_REG_E_SLICE_TYPE 0xFA84 +#define MFC_REG_E_PICTURE_COUNT 0xFA88 +#define MFC_REG_E_RET_PICTURE_TAG 0xFA8C +#define MFC_REG_E_TILE0_STREAM_SIZE 0xFA94 +#define MFC_REG_E_TILE1_STREAM_SIZE 0xFA98 + +#define MFC_REG_E_RECON_LUMA_DPB_ADDR 0xFA9C +#define MFC_REG_E_RECON_CHROMA_DPB_ADDR 0xFAA0 +#define MFC_REG_E_METADATA_ADDR_ENC_SLICE 0xFAA4 +#define MFC_REG_E_METADATA_SIZE_ENC_SLICE 0xFAA8 +#define MFC_REG_E_SUM_SKIP_MB 0xFAAC +#define MFC_REG_E_SUM_INTRA_MB 0xFAB0 +#define MFC_REG_E_SUM_ZERO_MV_MB 0xFAB4 + +#define MFC_REG_E_HDR10_PLUS_INFO 0xFAE8 +#define MFC_REG_E_NAL_DONE_INFO 0xFAEC + +#define MFC_REG_E_MPEG4_OPTIONS 0xFB10 +#define MFC_REG_E_MPEG4_HEC_PERIOD 0xFB14 + +#define MFC_REG_E_H264_HD_SVC_EXTENSION_0 0xFB44 +#define MFC_REG_E_H264_HD_SVC_EXTENSION_1 0xFB48 +#define MFC_REG_E_ASPECT_RATIO 0xFB4C +#define MFC_REG_E_EXTENDED_SAR 0xFB50 + +#define MFC_REG_E_H264_OPTIONS 0xFB54 +#define MFC_REG_E_H264_OPTIONS_2 0xFB58 +#define MFC_REG_E_H264_LF_ALPHA_OFFSET 0xFB5C +#define MFC_REG_E_H264_LF_BETA_OFFSET 0xFB60 +#define MFC_REG_E_H264_REFRESH_PERIOD 0xFB64 + +#define MFC_REG_E_H264_FMO_SLICE_GRP_MAP_TYPE 0xFB68 +#define MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1 0xFB6C +#define MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_DIR 0xFB70 +#define MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1 0xFB74 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_0 0xFB78 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_1 0xFB7C +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_2 0xFB80 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_3 0xFB84 + +#define MFC_REG_E_H264_ASO_SLICE_ORDER_0 0xFB88 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_1 0xFB8C +#define MFC_REG_E_H264_ASO_SLICE_ORDER_2 0xFB90 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_3 0xFB94 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_4 0xFB98 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_5 0xFB9C +#define MFC_REG_E_H264_ASO_SLICE_ORDER_6 0xFBA0 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_7 0xFBA4 +#define MFC_REG_E_H264_CHROMA_QP_OFFSET 0xFBA8 + +#define MFC_REG_E_NUM_T_LAYER 0xFBAC +#define MFC_REG_E_HIERARCHICAL_QP_LAYER0 0xFBB0 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER1 0xFBB4 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER2 0xFBB8 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER3 0xFBBC +#define MFC_REG_E_HIERARCHICAL_QP_LAYER4 0xFBC0 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER5 0xFBC4 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER6 0xFBC8 + +/* For backward compatibility */ +#define MFC_REG_E_H264_FRAME_PACKING_SEI_INFO 0xFC4C + +#define MFC_REG_E_H264_NAL_CONTROL 0xFD14 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 0xFD18 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER1 0xFD1C +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER2 0xFD20 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER3 0xFD24 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER4 0xFD28 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER5 0xFD2C +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER6 0xFD30 + +#define MFC_REG_E_MVC_FRAME_QP_VIEW1 0xFD40 +#define MFC_REG_E_MVC_RC_FRAME_RATE_VIEW1 0xFD44 +#define MFC_REG_E_MVC_RC_BIT_RATE_VIEW1 0xFD48 +#define MFC_REG_E_MVC_RC_QBOUND_VIEW1 0xFD4C +#define MFC_REG_E_MVC_RC_MODE_VIEW1 0xFD50 +#define MFC_REG_E_MVC_INTER_VIEW_PREDICTION_ON 0xFD80 + +#define MFC_REG_E_VP9_OPTION 0xFD90 +#define MFC_REG_E_VP9_FILTER_OPTION 0xFD94 +#define MFC_REG_E_VP9_GOLDEN_FRAME_OPTION 0xFD98 +#define MFC_REG_E_VP8_OPTION 0xFDB0 +#define MFC_REG_E_VP8_FILTER_OPTION 0xFDB4 +#define MFC_REG_E_VP8_GOLDEN_FRAME_OPTION 0xFDB8 + +#define MFC_REG_E_HEVC_OPTIONS_2 0xFDC4 + +#define MFC_REG_E_HEVC_OPTIONS 0xFDD4 +#define MFC_REG_E_HEVC_REFRESH_PERIOD 0xFDD8 +#define MFC_REG_E_HEVC_CHROMA_QP_OFFSET 0xFDDC +#define MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2 0xFDE0 +#define MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2 0xFDE4 +#define MFC_REG_E_HEVC_NAL_CONTROL 0xFDE8 + +#define MFC_REG_E_VP8_NAL_CONTROL 0xFDF0 +#define MFC_REG_E_VP9_NAL_CONTROL 0xFDF4 +#define MFC_REG_E_CONTENT_LIGHT_LEVEL_INFO_SEI 0xFDF8 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xFDFC +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xFE00 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xFE04 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xFE08 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xFE0C +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xFE10 + +#define MFC_REG_E_ST_2094_40_SEI_0 0xFE14 +#define MFC_REG_E_ST_2094_40_SEI_1 0xFE18 +#define MFC_REG_E_ST_2094_40_SEI_2 0xFE1C +#define MFC_REG_E_ST_2094_40_SEI_3 0xFE20 +#define MFC_REG_E_ST_2094_40_SEI_4 0xFE24 +#define MFC_REG_E_ST_2094_40_SEI_5 0xFE28 +#define MFC_REG_E_ST_2094_40_SEI_6 0xFE2C +#define MFC_REG_E_ST_2094_40_SEI_7 0xFE30 +#define MFC_REG_E_ST_2094_40_SEI_8 0xFE34 +#define MFC_REG_E_ST_2094_40_SEI_9 0xFE38 +#define MFC_REG_E_ST_2094_40_SEI_10 0xFE3C +#define MFC_REG_E_ST_2094_40_SEI_11 0xFE40 +#define MFC_REG_E_ST_2094_40_SEI_12 0xFE44 +#define MFC_REG_E_ST_2094_40_SEI_13 0xFE48 +#define MFC_REG_E_ST_2094_40_SEI_14 0xFE4C +#define MFC_REG_E_ST_2094_40_SEI_15 0xFE50 +#define MFC_REG_E_ST_2094_40_SEI_16 0xFE54 +#define MFC_REG_E_ST_2094_40_SEI_17 0xFE58 +#define MFC_REG_E_ST_2094_40_SEI_18 0xFE5C +#define MFC_REG_E_ST_2094_40_SEI_19 0xFE60 +#define MFC_REG_E_ST_2094_40_SEI_20 0xFE64 +#define MFC_REG_E_ST_2094_40_SEI_21 0xFE68 +#define MFC_REG_E_ST_2094_40_SEI_22 0xFE6C +#define MFC_REG_E_ST_2094_40_SEI_23 0xFE70 +#define MFC_REG_E_ST_2094_40_SEI_24 0xFE74 +#define MFC_REG_E_ST_2094_40_SEI_25 0xFE78 +#define MFC_REG_E_ST_2094_40_SEI_26 0xFE7C +#define MFC_REG_E_ST_2094_40_SEI_27 0xFE80 +#define MFC_REG_E_ST_2094_40_SEI_28 0xFE84 +#define MFC_REG_E_ST_2094_40_SEI_29 0xFE88 + +#define MFC_REG_D_ST_2094_40_SEI_0 0xFF00 +#define MFC_REG_D_ST_2094_40_SEI_1 0xFF04 +#define MFC_REG_D_ST_2094_40_SEI_2 0xFF08 +#define MFC_REG_D_ST_2094_40_SEI_3 0xFF0C +#define MFC_REG_D_ST_2094_40_SEI_4 0xFF10 +#define MFC_REG_D_ST_2094_40_SEI_5 0xFF14 +#define MFC_REG_D_ST_2094_40_SEI_6 0xFF18 +#define MFC_REG_D_ST_2094_40_SEI_7 0xFF1C +#define MFC_REG_D_ST_2094_40_SEI_8 0xFF20 +#define MFC_REG_D_ST_2094_40_SEI_9 0xFF24 +#define MFC_REG_D_ST_2094_40_SEI_10 0xFF28 +#define MFC_REG_D_ST_2094_40_SEI_11 0xFF2C +#define MFC_REG_D_ST_2094_40_SEI_12 0xFF30 +#define MFC_REG_D_ST_2094_40_SEI_13 0xFF34 +#define MFC_REG_D_ST_2094_40_SEI_14 0xFF38 +#define MFC_REG_D_ST_2094_40_SEI_15 0xFF3C +#define MFC_REG_D_ST_2094_40_SEI_16 0xFF40 +#define MFC_REG_D_ST_2094_40_SEI_17 0xFF44 +#define MFC_REG_D_ST_2094_40_SEI_18 0xFF48 +#define MFC_REG_D_ST_2094_40_SEI_19 0xFF4C +#define MFC_REG_D_ST_2094_40_SEI_20 0xFF50 +#define MFC_REG_D_ST_2094_40_SEI_21 0xFF54 +#define MFC_REG_D_ST_2094_40_SEI_22 0xFF58 +#define MFC_REG_D_ST_2094_40_SEI_23 0xFF5C +#define MFC_REG_D_ST_2094_40_SEI_24 0xFF60 +#define MFC_REG_D_ST_2094_40_SEI_25 0xFF64 +#define MFC_REG_D_ST_2094_40_SEI_26 0xFF68 +#define MFC_REG_D_ST_2094_40_SEI_27 0xFF6C +#define MFC_REG_D_ST_2094_40_SEI_28 0xFF70 +#define MFC_REG_D_ST_2094_40_SEI_29 0xFF74 + +/* + * Below It is valid only for AV1 + * when FILM_GRAIN_AVAIL of D_SEI_AVAIL is enabled + */ +#define MFC_REG_D_FILM_GRAIN_0 0xFE00 +#define MFC_REG_D_FILM_GRAIN_1 0xFE04 +#define MFC_REG_D_FILM_GRAIN_2 0xFE08 +#define MFC_REG_D_FILM_GRAIN_3 0xFE0C +#define MFC_REG_D_FILM_GRAIN_4 0xFE10 +#define MFC_REG_D_FILM_GRAIN_5 0xFE14 +#define MFC_REG_D_FILM_GRAIN_6 0xFE18 +#define MFC_REG_D_FILM_GRAIN_7 0xFE1C +#define MFC_REG_D_FILM_GRAIN_8 0xFE20 +#define MFC_REG_D_FILM_GRAIN_9 0xFE24 +#define MFC_REG_D_FILM_GRAIN_10 0xFE28 +#define MFC_REG_D_FILM_GRAIN_11 0xFE2C +#define MFC_REG_D_FILM_GRAIN_12 0xFE30 +#define MFC_REG_D_FILM_GRAIN_13 0xFE34 +#define MFC_REG_D_FILM_GRAIN_14 0xFE38 +#define MFC_REG_D_FILM_GRAIN_15 0xFE3C +#define MFC_REG_D_FILM_GRAIN_16 0xFE40 +#define MFC_REG_D_FILM_GRAIN_17 0xFE44 +#define MFC_REG_D_FILM_GRAIN_18 0xFE48 +#define MFC_REG_D_FILM_GRAIN_19 0xFE4C +#define MFC_REG_D_FILM_GRAIN_20 0xFE50 +#define MFC_REG_D_FILM_GRAIN_21 0xFE54 +#define MFC_REG_D_FILM_GRAIN_22 0xFE58 +#define MFC_REG_D_FILM_GRAIN_23 0xFE5C +#define MFC_REG_D_FILM_GRAIN_24 0xFE60 +#define MFC_REG_D_FILM_GRAIN_25 0xFE64 +#define MFC_REG_D_FILM_GRAIN_26 0xFE68 +#define MFC_REG_D_FILM_GRAIN_27 0xFE6C +#define MFC_REG_D_FILM_GRAIN_28 0xFE70 +#define MFC_REG_D_FILM_GRAIN_29 0xFE74 +#define MFC_REG_D_FILM_GRAIN_30 0xFE78 +#define MFC_REG_D_FILM_GRAIN_31 0xFE7C +#define MFC_REG_D_FILM_GRAIN_32 0xFE80 +#define MFC_REG_D_FILM_GRAIN_33 0xFE84 +#define MFC_REG_D_FILM_GRAIN_34 0xFE88 +#define MFC_REG_D_FILM_GRAIN_35 0xFE8C +#define MFC_REG_D_FILM_GRAIN_36 0xFE90 +#define MFC_REG_D_FILM_GRAIN_37 0xFE94 +#define MFC_REG_D_FILM_GRAIN_38 0xFE98 +#define MFC_REG_D_FILM_GRAIN_39 0xFE9C +#define MFC_REG_D_FILM_GRAIN_40 0xFEA0 +#define MFC_REG_D_FILM_GRAIN_41 0xFEA4 +#define MFC_REG_D_FILM_GRAIN_42 0xFEA8 +#define MFC_REG_D_FILM_GRAIN_43 0xFEAC + +#define MFC0_REG_COMMON_CONTEXT_MEM_ADDR 0xFF90 +#define MFC0_REG_RISC_BASE_ADDR 0xFF98 +#define MFC1_REG_COMMON_CONTEXT_MEM_ADDR 0xFFDC + +#define MFC_REG_CLEAR_BEGIN 0xf000 +#define MFC_REG_CLEAR_COUNT 1024 + +#define MFC0_REG_CONTEXT_FLUSH_DONE 0xFFA0 + +/* Bit Definitions */ +/* 0x1100: MFC_REG_HOST2RISC_CMD */ +#define MFC_REG_H2R_CMD_EMPTY 0 +#define MFC_REG_H2R_CMD_SYS_INIT 1 +#define MFC_REG_H2R_CMD_OPEN_INSTANCE 2 +#define MFC_REG_H2R_CMD_SEQ_HEADER 3 +#define MFC_REG_H2R_CMD_INIT_BUFFERS 4 +#define MFC_REG_H2R_CMD_NAL_START 5 +#define MFC_REG_H2R_CMD_CLOSE_INSTANCE 6 +#define MFC_REG_H2R_CMD_SLEEP 7 +#define MFC_REG_H2R_CMD_WAKEUP 8 +#define MFC_REG_H2R_CMD_LAST_FRAME 9 +#define MFC_REG_H2R_CMD_DPB_FLUSH 10 +#define MFC_REG_H2R_CMD_NAL_ABORT 11 +#define MFC_REG_H2R_CMD_CACHE_FLUSH 12 +#define MFC_REG_H2R_CMD_NAL_QUEUE 13 +#define MFC_REG_H2R_CMD_STOP_QUEUE 14 +#define MFC_REG_H2R_CMD_NAL_LL 15 +#define MFC_REG_H2R_CMD_MOVE_INSTANCE 19 + +#define MFC_REG_H2R_HWAPG_EN_FLAG 19 +#define MFC_REG_H2R_NAL_Q_OPT_FLAG 17 +#define MFC_REG_H2R_CACHE_FLUSH_FLAG 16 + +/* 0x1104: MFC_REG_RISC2HOST_CMD */ +#define MFC_REG_RISC2HOST_CMD_MASK 0x1FFFF +#define MFC_REG_R2H_CMD_EMPTY 0 +#define MFC_REG_R2H_CMD_SYS_INIT_RET 1 +#define MFC_REG_R2H_CMD_OPEN_INSTANCE_RET 2 +#define MFC_REG_R2H_CMD_SEQ_DONE_RET 3 +#define MFC_REG_R2H_CMD_INIT_BUFFERS_RET 4 +#define MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET 6 +#define MFC_REG_R2H_CMD_SLEEP_RET 7 +#define MFC_REG_R2H_CMD_WAKEUP_RET 8 +#define MFC_REG_R2H_CMD_COMPLETE_SEQ_RET 9 +#define MFC_REG_R2H_CMD_DPB_FLUSH_RET 10 +#define MFC_REG_R2H_CMD_NAL_ABORT_RET 11 +#define MFC_REG_R2H_CMD_FW_STATUS_RET 12 +#define MFC_REG_R2H_CMD_FRAME_DONE_RET 13 +#define MFC_REG_R2H_CMD_FIELD_DONE_RET 14 +#define MFC_REG_R2H_CMD_SLICE_DONE_RET 15 +#define MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET 16 +#define MFC_REG_R2H_CMD_QUEUE_DONE_RET 17 +#define MFC_REG_R2H_CMD_COMPLETE_QUEUE_RET 18 +#define MFC_REG_R2H_CMD_MOVE_INSTANCE_RET 19 +#define MFC_REG_R2H_CMD_CACHE_FLUSH_RET 20 +#define MFC_REG_R2H_CMD_ERR_RET 32 + +/* 0xF000: MFC_REG_FW_VERSION */ +#define MFC_REG_FW_VER_INFO_MASK 0xFF +#define MFC_REG_FW_VER_INFO_SHFT 24 +#define MFC_REG_FW_VER_YEAR_MASK 0xFF +#define MFC_REG_FW_VER_YEAR_SHFT 16 +#define MFC_REG_FW_VER_MONTH_MASK 0xFF +#define MFC_REG_FW_VER_MONTH_SHFT 8 +#define MFC_REG_FW_VER_DATE_MASK 0xFF +#define MFC_REG_FW_VER_DATE_SHFT 0 +#define MFC_REG_FW_VER_ALL_MASK 0xFFFFFF +#define MFC_REG_FW_VER_ALL_SHFT 0 + +/* 0xF00C: MFC_REG_CODEC_TYPE */ +#define MFC_FORMATS_NO_CODEC -1 +/* Decoder */ +#define MFC_REG_CODEC_H264_DEC 0 +#define MFC_REG_CODEC_H264_MVC_DEC 1 +#define MFC_REG_CODEC_MPEG4_DEC 3 +#define MFC_REG_CODEC_FIMV1_DEC 4 +#define MFC_REG_CODEC_FIMV2_DEC 5 +#define MFC_REG_CODEC_FIMV3_DEC 6 +#define MFC_REG_CODEC_FIMV4_DEC 7 +#define MFC_REG_CODEC_H263_DEC 8 +#define MFC_REG_CODEC_VC1_RCV_DEC 9 +#define MFC_REG_CODEC_VC1_DEC 10 +#define MFC_REG_CODEC_MPEG2_DEC 13 +#define MFC_REG_CODEC_VP8_DEC 14 +#define MFC_REG_CODEC_HEVC_DEC 17 +#define MFC_REG_CODEC_VP9_DEC 18 +#define MFC_REG_CODEC_AV1_DEC 19 +/* Encoder */ +#define MFC_REG_CODEC_H264_ENC 20 +#define MFC_REG_CODEC_H264_MVC_ENC 21 +#define MFC_REG_CODEC_MPEG4_ENC 23 +#define MFC_REG_CODEC_H263_ENC 24 +#define MFC_REG_CODEC_VP8_ENC 25 +#define MFC_REG_CODEC_HEVC_ENC 26 +#define MFC_REG_CODEC_VP9_ENC 27 + +#define MFC_REG_CODEC_BPG_DEC 32 +#define MFC_REG_CODEC_BPG_ENC 33 + +/* 0xF00C: MFC_REG_CODEC_TYPE */ +#define MFC_REG_CLEAR_CTX_MEM_SHIFT 16 +#define MFC_REG_CODEC_TYPE_MASK 0xFFFF + +/* 0xF024: MFC_REG_METADATA_ENABLE */ +#define MFC_REG_SEI_NAL_ENABLE_SHIFT 3 + +/* 0xF028: MFC_REG_MFC_VERSION */ +#define MFC_REG_MFC_VER_MASK 0xFFFFFFFF +#define MFC_REG_MFC_VER_SHFT 0 +/* bits of [8:4] can be changed if there is minor change between EVT0 and EVT1. */ +#define MFC_REG_MFC_VER_MAJOR_MASK 0xFFFFFF0F +#define MFC_REG_MFC_VER_MINOR_MASK 0x000000F0 + +/* 0xF02C: MFC_REG_DBG_INFO_ENABLE */ +#define MFC_REG_DBG_INFO_ENABLE_SHIFT 0 +#define MFC_REG_DBG_INFO_DPB_CLEAR_SHIFT 1 +#define MFC_REG_DBG_INFO_TWO_MFC_FORCING_SHIFT 2 + +/* 0xF070: MFC_REG_RET_INSTANCE_ID */ +#define MFC_REG_RET_INSTANCE_ID_OF_MFC1_MASK 0xFFFF +#define MFC_REG_RET_INSTANCE_ID_OF_MFC1_SHIFT 16 +#define MFC_REG_RET_INSTANCE_ID_MASK 0xFFFF + +/* 0xF074: MFC_REG_ERROR_CODE */ +#define MFC_REG_ERR_STATUS_MASK 0xFFFF +#define MFC_REG_ERR_STATUS_SHIFT 0 +#define MFC_REG_WARN_STATUS_MASK 0xFFFF +#define MFC_REG_WARN_STATUS_SHIFT 16 + +/* 0xF07C: MFC_METADATA_STATUS */ +#define MFC_REG_SEI_NAL_STATUS_MASK 0x1 +#define MFC_REG_SEI_NAL_STATUS_SHIFT 3 + +/* Error number */ +#define MFC_REG_ERR_INVALID 9 +#define MFC_REG_ERR_BUFFER_FULL 18 +#define MFC_REG_ERR_WARNINGS_END 222 +/* Dump debug error */ +#define MFC_REG_ERR_NO_AVAILABLE_DPB 33 +#define MFC_REG_ERR_INSUFFICIENT_DPB_SIZE 57 +#define MFC_REG_ERR_INSUFFICIENT_NUM_DPB 58 +#define MFC_REG_ERR_INSUFFICIENT_MV_BUF_SIZE 60 +#define MFC_REG_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE 62 +/* HEVC VPS header error */ +#define MFC_REG_ERR_VPS_ONLY_ERROR 42 +/* Input decoding error */ +#define MFC_REG_ERR_NO_KEY_FRAME 34 +#define MFC_REG_ERR_NO_VALID_SEQ_HDR 66 +#define MFC_REG_ERR_NO_VALID_PIC_HDR 67 +#define MFC_REG_ERR_MISSING_NON_BASE_VIEW_DETECTED 69 +#define MFC_REG_ERR_MISSING_BASE_VIEW_DETECTED 70 +#define MFC_REG_ERR_NO_VALID_REF_FOR_SKIP 72 +#define MFC_REG_ERR_UNSUPPORTED_FEATURE 100 +#define MFC_REG_ERR_UNSUPPORTED_RESOLUTION 101 +#define MFC_REG_ERR_HEADER_NOT_FOUND 102 +#define MFC_REG_ERR_INVALID_NAL_TYPE 103 +#define MFC_REG_ERR_SEQUENCE_HEADER_ERROR 104 +#define MFC_REG_ERR_PICTURE_HEADER_ERROR 105 +#define MFC_REG_ERR_SLICE_HEADER_ERROR 106 +#define MFC_REG_ERR_MISSING_FIRST_FIELD 108 +#define MFC_REG_ERR_SLICE_COUNT_IS_OVER_ASO 109 +#define MFC_REG_ERR_TILE_HEADER_ERROR 111 +#define MFC_REG_ERR_MAX_VIEW_NUM_OVER 112 +/* Timeout */ +#define MFC_REG_ERR_MFC_TIMEOUT 140 +#define MFC_REG_ERR_TS_MUX_TIMEOUT 141 +#define MFC_REG_ERR_G2D_TIMEOUT 142 +/* Exception */ +#define MFC_REG_ERR_UNDEFINED_EXCEPTION 145 +/* Frame concealment and warning */ +#define MFC_REG_ERR_FRAME_CONCEAL 150 +#define MFC_REG_ERR_BROKEN_LINK 161 +#define MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED 190 +#define MFC_REG_ERR_NON_PAIRED_FIELD 191 + +/* 0xF0B4: MFC_REG_D_DEC_OPTIONS */ +#define MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT 3 +#define MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK 0x1 +#define MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT 4 +#define MFC_REG_D_DEC_OPT_IDR_DECODING_MASK 0x1 +#define MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT 6 +#define MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT 7 +#define MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT 8 +#define MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT 11 +#define MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT 13 +#define MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT 15 +#define MFC_REG_D_DEC_OPT_THUMBNAIL_DECODING 16 +#define MFC_REG_D_DEC_OPT_DECODING_ORDER_ENABLE 17 +#define MFC_REG_D_DEC_OPT_AV1_ANNEX_B_FORMAT_SHIFT 18 + +/* 0xF094: MFC_REG_NAL_QUEUE_INFO*/ +#define MFC_REG_NAL_QUEUE_EXE_NAL_LL_SHIFT 8 +#define MFC_REG_NAL_QUEUE_EXE_NAL_LL_MASK 0x7F +#define MFC_REG_NAL_QUEUE_OUT_CMD_COUNT_SHIFT 0 +#define MFC_REG_NAL_QUEUE_OUT_CMD_COUNT_MASK 0xFF + +/* 0xF0C4: MFC_REG_D_SEI_ENABLE */ +#define MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT 1 +#define MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT 2 +#define MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT 4 +#define MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT 5 +#define MFC_REG_D_SEI_ENABLE_ST_2094_40_SEI_SHIFT 6 +#define MFC_REG_D_SEI_ENABLE_FILM_GRAIN_SHIFT 7 + +/* 0xF154: MFC_REG_D_INIT_BUFFER_OPTIONS */ +#define MFC_REG_D_INIT_BUF_OPT_LF_CTRL_MASK 0x3 +#define MFC_REG_D_INIT_BUF_OPT_LF_CTRL_SHIFT 1 +#define MFC_REG_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT 3 +#define MFC_REG_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT 4 +#define MFC_REG_D_INIT_BUF_OPT_DITHERING_EN_SHIFT 6 +#define MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN 7 +#define MFC_REG_D_INIT_BUF_OPT_TWO_MODE_ENABLE_SHIFT 9 +#define MFC_REG_D_INIT_BUF_OPT_ENABLE_DECODE_VIEW1 10 + +/* 0xF5AC: MFC_REG_D_NAL_START_OPTIONS */ +#define MFC_REG_D_NAL_START_OPT_DIS_COMPRESSOR_SHIFT 5 +#define MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT 4 +#define MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT 3 +#define MFC_REG_D_NAL_START_OPT_NEW_SCRATCH_SHIFT 2 +#define MFC_REG_D_NAL_START_OPT_NEW_DPB_SHIFT 1 + +/* 0xF608: MFC_REG_D_DISPLAY_STATUS */ +#define MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK 0x7 +#define MFC_REG_DISP_STATUS_INTERLACE_MASK 0x1 +#define MFC_REG_DISP_STATUS_INTERLACE_SHIFT 3 +#define MFC_REG_DISP_STATUS_RES_CHANGE_MASK 0x3 +#define MFC_REG_DISP_STATUS_RES_CHANGE_SHIFT 4 +#define MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_SHIFT 9 +#define MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT 10 +#define MFC_REG_DISP_STATUS_LAST_DISPLAY_FRAME_MASK 0x1 +#define MFC_REG_DISP_STATUS_LAST_DISPLAY_FRAME_SHIFT 11 +#define MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_SHIFT 12 +#define MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_MASK 0x3 +#define MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_SHIFT 13 +#define MFC_REG_DISP_STATUS_NOT_DETECTED 0x0 +#define MFC_REG_DISP_STATUS_BLACK_BAR 0x1 +#define MFC_REG_DISP_STATUS_BLACK_SCREEN 0x2 +#define MFC_REG_DISP_STATUS_COMP_SHIFT 19 +#define MFC_REG_DISP_STATUS_COMP_MASK 0x1 +#define MFC_REG_DISP_STATUS_UNCOMP_SHIFT 21 +#define MFC_REG_DISP_STATUS_UNCOMP_MASK 0x1 +#define MFC_REG_DISP_STATUS_FIELD_SHIFT 22 +#define MFC_REG_DISP_STATUS_FIELD_MASK 0x1 + +/* 0xF618: MFC_REG_D_DISPLAY_FRAME_TYPE */ +#define MFC_REG_DISPLAY_TEMP_INFO_MASK 0x1 +#define MFC_REG_DISPLAY_TEMP_INFO_SHIFT 7 +#define MFC_REG_DISPLAY_IDR_FLAG_MASK 0x1 +#define MFC_REG_DISPLAY_IDR_FLAG_SHIFT 6 +#define MFC_REG_DISPLAY_FRAME_MASK 0x7 +#define MFC_REG_DISPLAY_FRAME_NOT_CODED 0 +#define MFC_REG_DISPLAY_FRAME_I 1 +#define MFC_REG_DISPLAY_FRAME_P 2 +#define MFC_REG_DISPLAY_FRAME_B 3 + +/* 0xF61C: MFC_REG_D_DISPLAY_CROP_INFO1 */ +#define MFC_REG_D_SHARED_CROP_LEFT_MASK 0xFFFF +#define MFC_REG_D_SHARED_CROP_RIGHT_SHIFT 16 + +/* 0xF620: MFC_REG_D_DISPLAY_CROP_INFO2 */ +#define MFC_REG_D_SHARED_CROP_TOP_MASK 0xFFFF +#define MFC_REG_D_SHARED_CROP_BOTTOM_SHIFT 16 + +/* 0xF644: MFC_REG_D_DECODED_STATUS */ +#define MFC_REG_DEC_STATUS_DECODED_STATUS_MASK 0x7 +#define MFC_REG_DEC_STATUS_DECODING_ONLY 0 +#define MFC_REG_DEC_STATUS_DECODING_DISPLAY 1 +#define MFC_REG_DEC_STATUS_DISPLAY_ONLY 2 +#define MFC_REG_DEC_STATUS_DECODING_EMPTY 3 +#define MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK 0xF +#define MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT 15 +#define MFC_REG_DEC_STATUS_INTERLACE_MASK 0x1 +#define MFC_REG_DEC_STATUS_INTERLACE_SHIFT 3 +#define MFC_REG_DEC_STATUS_UNCOMP_SHIFT 21 +#define MFC_REG_DEC_STATUS_UNCOMP_MASK 0x1 + +/* 0xF654: MFC_REG_D_DECODED_FRAME_TYPE */ +#define MFC_REG_DECODED_IDR_FLAG_MASK 0x1 +#define MFC_REG_DECODED_IDR_FLAG_SHIFT 3 +#define MFC_REG_DECODED_FRAME_MASK 0x7 +#define MFC_REG_DECODED_FRAME_NOT_CODED 0 +#define MFC_REG_DECODED_FRAME_I 1 +#define MFC_REG_DECODED_FRAME_P 2 +#define MFC_REG_DECODED_FRAME_B 3 + +/* 0xF660: MFC_REG_D_DECODED_PICTURE_PROFILE */ +#define MFC_REG_D_TWO_MFC_MODE_MASK 0x3 +#define MFC_REG_D_TWO_MFC_MODE_SHIFT 28 +#define MFC_REG_D_DISPLAY_DELAY_MASK 0x1F +#define MFC_REG_D_DISPLAY_DELAY_SHIFT 23 +#define MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_MASK 0x7 +#define MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT 19 +#define MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_MASK 0x7 +#define MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_SHIFT 16 +#define MFC_REG_D_PIC_LEVEL_MASK 0xFF +#define MFC_REG_D_PIC_LEVEL_SHIFT 8 +#define MFC_REG_D_DECODED_PIC_PROFILE_MASK 0x1F +#define MFC_REG_D_PROFILE_HEVC_MAIN 1 +#define MFC_REG_D_PROFILE_HEVC_MAIN_10 2 +#define MFC_REG_D_PROFILE_MULTIVIEW_HEVC_MAIN 5 +#define MFC_REG_D_PROFILE_MULTIVIEW_HEVC_MAIN_10 6 +#define MFC_REG_D_PROFILE_HEVC_RANGE_EXT 4 + +/* 0xF684: MFC_REG_D_CHROMA_FORMAT */ +#define MFC_REG_D_CHROMA_FORMAT_MASK 0x3 +#define MFC_REG_D_COLOR_RANGE_MASK 0x1 +#define MFC_REG_D_COLOR_RANGE_SHIFT 3 +#define MFC_REG_D_COLOR_SPACE_MASK 0xF +#define MFC_REG_D_COLOR_SPACE_SHIFT 4 +#define MFC_REG_D_COLOR_UNKNOWN 0 +#define MFC_REG_D_CHROMA_400 0 +#define MFC_REG_D_CHROMA_420 1 +#define MFC_REG_D_CHROMA_422 2 +#define MFC_REG_D_CHROMA_444 3 + +/* 0xF690: MFC_REG_D_H264_INFO */ +#define MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT 9 +#define MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_MASK 0x1 +#define MFC_REG_D_H264_INFO_TEMPORAL_ID_SHIFT 6 +#define MFC_REG_D_H264_INFO_TEMPORAL_ID_MASK 0x7 + +/* 0xF6A0: MFC_REG_D_HEVC_INFO */ +#define MFC_REG_D_HEVC_INFO_PIC_OUTPUT_FLAG_SHIFT 11 +#define MFC_REG_D_HEVC_INFO_PIC_OUTPUT_FLAG_MASK 0x1 +#define MFC_REG_D_HEVC_INFO_LCU_SIZE_MASK 0x3 + +/* 0xF6A4: MFC_REG_D_VP9_INFO */ +#define MFC_REG_D_VP9_INFO_DISP_RES_SHIFT 14 +#define MFC_REG_D_VP9_INFO_DISP_RES_MASK 0x1 + +/* 0xF6AC: MFC_REG_D_AV1_INFO */ +#define MFC_REG_D_AV1_INFO_FILMGRAIN_PRESENT_SHIFT 18 +#define MFC_REG_D_AV1_INFO_FILMGRAIN_PRESENT_MASK 0x1 +#define MFC_REG_D_AV1_INFO_MULTIPLE_SHOW_SHIFT 17 +#define MFC_REG_D_AV1_INFO_MULTIPLE_SHOW_MASK 0x1 +#define MFC_REG_D_AV1_INFO_DISP_RES_SHIFT 14 +#define MFC_REG_D_AV1_INFO_DISP_RES_MASK 0x1 +#define MFC_REG_D_AV1_INFO_SHOWABLE_FRAME_SHIFT 5 +#define MFC_REG_D_AV1_INFO_SHOWABLE_FRAME_MASK 0x1 + +/* 0xF6D8: MFC_REG_D_MVC_VIEW_ID */ +#define MFC_REG_D_MVC_VIEW_ID_DEC_SHIFT 16 +#define MFC_REG_D_MVC_VIEW_ID_DEC_MASK 0xFFFF +#define MFC_REG_D_MVC_VIEW_ID_DISP_MASK 0xFFFF +#define MFC_REG_D_MVC_LEFT_VIEW_ID_SHIFT 28 +#define MFC_REG_D_MVC_LEFT_VIEW_ID_MASK 0x3 +#define MFC_REG_D_MVC_RIGHT_VIEW_ID_SHIFT 30 +#define MFC_REG_D_MVC_RIGHT_VIEW_ID_MASK 0x3 + +/* 0xF6DC: MFC_REG_D_SEI_AVAIL */ +#define MFC_REG_D_SEI_AVAIL_FRAME_PACK_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT 1 +#define MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT 2 +#define MFC_REG_D_SEI_AVAIL_ST_2094_40_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_ST_2094_40_SHIFT 3 +#define MFC_REG_D_SEI_AVAIL_FILM_GRAIN_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_FILM_GRAIN_SHIFT 4 + +/* 0xF70C: MFC_REG_D_VIDEO_SIGNAL_TYPE */ +#define MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK 0x1 +#define MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT 29 +#define MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK 0x1 +#define MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT 24 +#define MFC_REG_D_COLOUR_PRIMARIES_MASK 0xFF +#define MFC_REG_D_COLOUR_PRIMARIES_SHIFT 16 +#define MFC_REG_D_TRANSFER_CHARACTERISTICS_MASK 0xFF +#define MFC_REG_D_TRANSFER_CHARACTERISTICS_SHIFT 8 +#define MFC_REG_D_MATRIX_COEFFICIENTS_MASK 0xFF +#define MFC_REG_D_MATRIX_COEFFICIENTS_SHIFT 0 + +/* 0xF738: MFC_REG_D_BLACK_BAR_START_POS */ +#define MFC_REG_D_BLACK_BAR_START_X_SHIFT 0 +#define MFC_REG_D_BLACK_BAR_START_X_MASK 0xFFFF +#define MFC_REG_D_BLACK_BAR_START_Y_SHIFT 16 +#define MFC_REG_D_BLACK_BAR_START_Y_MASK 0xFFFF + +/* 0xF73C: MFC_REG_D_BLACK_BAR_IMAGE_SIZE */ +#define MFC_REG_D_BLACK_BAR_IMAGE_W_SHIFT 0 +#define MFC_REG_D_BLACK_BAR_IMAGE_W_MASK 0xFFFF +#define MFC_REG_D_BLACK_BAR_IMAGE_H_SHIFT 16 +#define MFC_REG_D_BLACK_BAR_IMAGE_H_MASK 0xFFFF + +/* 0xF780: MFC_REG_E_FRAME_CROP_OFFSET */ +#define MFC_REG_E_FRAME_CROP_OFFSET_TOP 16 +#define MFC_REG_E_FRAME_CROP_OFFSET_LEFT 0 +#define MFC_REG_E_FRAME_CROP_OFFSET_MASK 0x3FFF + +/* 0xF788: MFC_REG_E_PICTURE_PROFILE */ +#define MFC_REG_E_PROFILE_H264_BASELINE 0 +#define MFC_REG_E_PROFILE_H264_MAIN 1 +#define MFC_REG_E_PROFILE_H264_HIGH 2 +#define MFC_REG_E_PROFILE_H264_CONSTRAINED_BASELINE 3 +#define MFC_REG_E_PROFILE_H264_CONSTRAINED_HIGH 5 +#define MFC_REG_E_PROFILE_MPEG4_SIMPLE 0 +#define MFC_REG_E_PROFILE_MPEG4_ADVANCED_SIMPLE 1 +#define MFC_REG_E_PROFILE_HEVC_MAIN 0 +#define MFC_REG_E_PROFILE_HEVC_MAIN_422_10_INTRA 2 +#define MFC_REG_E_PROFILE_HEVC_MAIN_10 3 +#define MFC_REG_E_PROFILE_HEVC_MAIN_422_10 4 +#define MFC_REG_E_PROFILE_VP9_PROFILE0 0 +#define MFC_REG_E_PROFILE_VP9_PROFILE1 1 +#define MFC_REG_E_PROFILE_VP9_PROFILE2 2 +#define MFC_REG_E_PROFILE_VP9_PROFILE3 3 + +/* 0xF7A4: MFC_REG_E_RC_MODE */ +#define MFC_REG_E_RC_CBR_FIX 0 +#define MFC_REG_E_RC_CBR_VAR 1 +#define MFC_REG_E_RC_VBR 2 +#define MFC_REG_E_RC_CBR_I_LIMIT_VT 3 +#define MFC_REG_E_RC_VBR_BS 4 +#define MFC_REG_E_RC_CBR_I_LIMIT_WFD 5 + +/* 0xFA84: MFC_REG_E_SLICE_TYPE */ +#define MFC_REG_E_SLICE_TYPE_NOT_CODED 0 +#define MFC_REG_E_SLICE_TYPE_MASK 0xF +#define MFC_REG_E_SLICE_TYPE_I 1 +#define MFC_REG_E_SLICE_TYPE_P 2 +#define MFC_REG_E_SLICE_TYPE_B 3 +#define MFC_REG_E_SLICE_TYPE_SKIPPED 4 + +/* 0xFAE8: MFC_REG_E_HDR10_PLUS_INFO */ +#define MFC_REG_E_HDR10_PLUS_INFO_STAT_DONE_MASK 1 +#define MFC_REG_E_HDR10_PLUS_INFO_STAT_DONE_SHIFT 31 +#define MFC_REG_E_HDR10_PLUS_INFO_SEI_SIZE_MASK 0x1FF +#define MFC_REG_E_HDR10_PLUS_INFO_SEI_SIZE_SHIFT 8 +#define MFC_REG_E_HDR10_PLUS_INFO_OFFSET_MASK 0xFF +#define MFC_REG_E_HDR10_PLUS_INFO_OFFSET_SHIFT 0 + +/* 0xFAEC: MFC_REG_E_NAL_DONE_INFO */ +#define MFC_REG_E_NAL_DONE_INFO_COMP_ERR_MASK 0x3 +#define MFC_REG_E_NAL_DONE_INFO_COMP_ERR_SHIFT 7 +#define MFC_REG_E_NAL_DONE_INFO_IDR_MASK 0x1 +#define MFC_REG_E_NAL_DONE_INFO_IDR_SHIFT 20 + +/* SEI Metadata format */ +#define MFC_META_SEI_NAL_SIZE_OFFSET 0x4 +#define MFC_META_SEI_NAL_PAYLOAD_OFFSET 0x8 + +#endif /* __MFC_REGS_MFC_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035535epcas5p3def6efaf88b04542ab6c27ecaa8e86fd@epcas5p3.samsung.com>]
* [PATCH 05/29] media: mfc: Add MFC driver header files and core utilities [not found] ` <CGME20250930035535epcas5p3def6efaf88b04542ab6c27ecaa8e86fd@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce new driver headers: mfc_buf.h, mfc_common.h, mfc_media.h, mfc_mem.h, mfc_regs.h, mfc_sched.h, and mfc_utils.h. mfc_buf.h Define buffer allocation/release APIs, common driver constants, video node identifiers, and feature‑specific V4L2 control IDs. mfc_common.h Define driver metadata, node IDs, timeout values, format flags, error/warning macros, and helper macros for buffer/context conversion mfc_media.h Expand V4L2 control IDs for a wide range of codec features (HEVC, VP8/9, AV1, HDR, ROI, etc.) mfc_mem.h Implement memory management helpers for DMA buffers, IOVA pool handling, and firmware mapping. mfc_regs.h Add register access macros for core, MMU, and PMU registers, handling both 32‑bit and 64‑bit DMA address spaces. mfc_sched.h Supply scheduler helper for priority calculation and core initialization. Supply utility inline functions for state changes, interrupt flag handling, idle checking, and tracing. mfc_utils.h Provide inline utility functions for clearing interrupt flags, state changes, operation‑mode updates, node‑type detection, and idle‑checker management. These changes collectively lay the groundwork for the Samsung MFC (Multi‑Format Codec) driver, enabling buffer handling, register access, and core scheduling functionalities. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_buf.c | 289 ++++++++ .../samsung/exynos-mfc/base/mfc_buf.h | 32 + .../samsung/exynos-mfc/base/mfc_common.h | 198 ++++++ .../samsung/exynos-mfc/base/mfc_media.h | 554 ++++++++++++++++ .../samsung/exynos-mfc/base/mfc_mem.c | 618 ++++++++++++++++++ .../samsung/exynos-mfc/base/mfc_mem.h | 80 +++ .../samsung/exynos-mfc/base/mfc_regs.h | 58 ++ .../samsung/exynos-mfc/base/mfc_sched.h | 30 + .../samsung/exynos-mfc/base/mfc_utils.h | 168 +++++ 9 files changed, 2027 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c new file mode 100644 index 000000000000..b8b140824aab --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2010-2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_buf.c file + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * nagaraju siddineni, <nagaraju.s@samsung.com> + */ +#include <linux/firmware.h> +#include <linux/iommu.h> + +#include "mfc_buf.h" + +#include "mfc_mem.h" + +#include "mfc_utils.h" + +/* Release context buffers for SYS_INIT */ +static void __mfc_release_common_context(struct mfc_core *core) +{ + struct mfc_special_buf *ctx_buf; + + ctx_buf = &core->common_ctx_buf; + + mfc_iova_pool_free(core->dev, ctx_buf); + + mfc_mem_special_buf_free(core->dev, ctx_buf); + + ctx_buf->dma_buf = NULL; + ctx_buf->vaddr = NULL; + ctx_buf->daddr = 0; +} + +/* Release context buffers for SYS_INIT */ +void mfc_release_common_context(struct mfc_core *core) +{ + if (core->fw.status & MFC_CTX_ALLOC) { + __mfc_release_common_context(core); + mfc_core_change_fw_state(core, MFC_CTX_ALLOC, 0); + } +} + +static int __mfc_alloc_common_context(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + struct mfc_special_buf *ctx_buf; + struct mfc_ctx_buf_size *buf_size; + + mfc_core_debug_enter(); + + ctx_buf = &core->common_ctx_buf; + ctx_buf->buftype = MFCBUF_NORMAL; + + buf_size = dev->variant->buf_size->ctx_buf; + ctx_buf->size = buf_size->dev_ctx; + + snprintf(ctx_buf->name, MFC_NUM_SPECIAL_BUF_NAME, "MFC%d common context", core->id); + if (mfc_mem_special_buf_alloc(dev, ctx_buf)) { + mfc_core_err("Allocating context buffer failed\n"); + return -ENOMEM; + } + + if (mfc_iova_pool_alloc(dev, ctx_buf)) { + mfc_core_err("[POOL] failed to get iova\n"); + __mfc_release_common_context(core); + return -ENOMEM; + } + + mfc_core_debug_leave(); + + return 0; +} + +/* Wrapper : allocate context buffers for SYS_INIT */ +int mfc_alloc_common_context(struct mfc_core *core) +{ + int ret = 0; + + ret = __mfc_alloc_common_context(core); + if (ret) + return ret; + mfc_core_change_fw_state(core, MFC_CTX_ALLOC, 1); + + return ret; +} + +/* Allocation buffer of debug infor memory for FW debugging */ +int mfc_alloc_dbg_info_buffer(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + struct mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; + + mfc_core_debug(2, "Allocate a debug-info buffer\n"); + + core->dbg_info_buf.buftype = MFCBUF_NORMAL; + core->dbg_info_buf.size = buf_size->dbg_info_buf; + snprintf(core->dbg_info_buf.name, MFC_NUM_SPECIAL_BUF_NAME, "MFC%d debug", core->id); + if (mfc_mem_special_buf_alloc(dev, &core->dbg_info_buf)) { + mfc_core_err("Allocating debug info buffer failed\n"); + return -ENOMEM; + } + + if (mfc_iova_pool_alloc(dev, &core->dbg_info_buf)) { + mfc_core_err("[POOL] failed to get iova\n"); + mfc_release_dbg_info_buffer(core); + return -ENOMEM; + } + + return 0; +} + +/* Release buffer of debug infor memory for FW debugging */ +void mfc_release_dbg_info_buffer(struct mfc_core *core) +{ + if (!core->dbg_info_buf.dma_buf) + mfc_core_debug(2, "debug info buffer is already freed\n"); + + mfc_iova_pool_free(core->dev, &core->dbg_info_buf); + + mfc_mem_special_buf_free(core->dev, &core->dbg_info_buf); +} + +/* Allocate firmware */ +int mfc_alloc_firmware(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + + mfc_core_debug_enter(); + + if (core->fw_buf.sgt) + return 0; + + mfc_core_debug(4, "[F/W] Allocating memory for firmware\n"); + + if (dev->pdata->fw_mem_size) + core->fw_buf.size = dev->pdata->fw_mem_size; + else + core->fw_buf.size = dev->variant->buf_size->firmware_code; + core->fw_buf.buftype = MFCBUF_NORMAL_FW; + + strscpy(core->fw_buf.name, core->name, sizeof(core->fw_buf.name)); + if (mfc_mem_special_buf_alloc(dev, &core->fw_buf)) { + mfc_core_err("[F/W] Allocating normal firmware buffer failed\n"); + return -ENOMEM; + } + +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + if (mfc_iommu_map_firmware(core, &core->fw_buf)) + goto err_reserve_iova; +#endif + mfc_core_change_fw_state(core, MFC_FW_ALLOC, 1); + + mfc_core_debug_leave(); + + return 0; + +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) +err_reserve_iova: + mfc_core_change_fw_state(core, MFC_FW_ALLOC, 0); + iommu_unmap(core->domain, fw_buf->daddr, fw_buf->map_size); + mfc_mem_special_buf_free(dev, &core->fw_buf); + return -ENOMEM; +#endif +} + +/* Load firmware to MFC */ +int mfc_load_firmware(struct mfc_core *core, + struct mfc_special_buf *fw_buf, + const u8 *fw_data, + size_t fw_size) +{ + mfc_core_debug(2, + "[MEMINFO][F/W] loaded %s F/W Size: %zu\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure", + fw_size); + + if (fw_size > fw_buf->size) { + mfc_core_err + ("[MEMINFO][F/W] MFC firmware(%zu) is too big to be loaded in memory(%zu)\n", + fw_size, + fw_buf->size); + return -ENOMEM; + } + + core->fw.fw_size = fw_size; + + if (fw_buf->daddr == 0) { + mfc_core_err("[F/W] MFC firmware is not allocated\n"); + return -EINVAL; + } +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + if (!fw_buf->sgt) { + mfc_core_err("[F/W] MFC firmware was not mapped correctly\n"); + return -EINVAL; + } +#endif + /* This adds to clear with '0' for firmware memory except code region. */ + mfc_core_debug(4, + "[F/W] memset before memcpy for %s fw\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); + memset((fw_buf->vaddr + fw_size), 0, (fw_buf->size - fw_size)); + memcpy(fw_buf->vaddr, fw_data, fw_size); + + /* cache flush for memcpy by CPU */ +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + dma_sync_sgtable_for_device(core->device, fw_buf->sgt, DMA_TO_DEVICE); +#else + dma_sync_single_for_device(core->device, fw_buf->paddr, fw_buf->size, DMA_TO_DEVICE); +#endif + mfc_core_debug(4, + "[F/W] cache flush for %s FW region\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); + + mfc_core_change_fw_state(core, MFC_FW_LOADED, 1); + + if (core->dev->debugfs.sfr_dump & MFC_DUMP_FIRMWARE) { + print_hex_dump(KERN_ERR, + "FW dump ", + DUMP_PREFIX_OFFSET, + 32, + 1, + fw_buf->vaddr, + 0x200, + false); + mfc_core_info("......\n"); + print_hex_dump(KERN_ERR, + "FW dump + 0xffe00 ", + DUMP_PREFIX_OFFSET, + 32, + 1, + fw_buf->vaddr + 0xffe00, + 0x200, + false); + } + + return 0; +} + +/* Request and load firmware to MFC */ +int mfc_request_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf) +{ + const struct firmware *fw_blob; + int ret; + + mfc_core_debug_enter(); + + mfc_core_debug(4, + "[F/W] Requesting %s F/W\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); + + ret = request_firmware(&fw_blob, core->dev->pdata->fw_name, core->dev->v4l2_dev.dev); + if (ret != 0) { + mfc_core_err("[F/W] Couldn't find the F/W invalid path\n"); + return ret; + } + + ret = mfc_load_firmware(core, fw_buf, fw_blob->data, fw_blob->size); + if (ret) { + mfc_core_err("[F/W] Failed to load the MFC F/W\n"); + release_firmware(fw_blob); + return ret; + } + + release_firmware(fw_blob); + + mfc_core_debug_leave(); + + return 0; +} + +/* Release firmware memory */ +int mfc_release_firmware(struct mfc_core *core) +{ +/* Before calling this function one has to make sure + * that MFC is no longer processing + */ +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + if (core->fw_buf.daddr) + iommu_unmap(core->domain, core->fw_buf.daddr, core->fw_buf.map_size); +#endif + + mfc_mem_special_buf_free(core->dev, &core->fw_buf); + + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h new file mode 100644 index 000000000000..8291e043b81a --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_buf.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_BUF_H +#define __MFC_BUF_H __FILE__ + +#include "mfc_common.h" + +/* Memory allocation */ +void mfc_release_common_context(struct mfc_core *core); +int mfc_alloc_common_context(struct mfc_core *core); + +int mfc_alloc_firmware(struct mfc_core *core); +int mfc_load_firmware(struct mfc_core *core, + struct mfc_special_buf *fw_buf, + const u8 *fw_data, + size_t fw_size); +int mfc_request_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf); +int mfc_release_firmware(struct mfc_core *core); + +int mfc_alloc_dbg_info_buffer(struct mfc_core *core); +void mfc_release_dbg_info_buffer(struct mfc_core *core); + +#endif /* __MFC_BUF_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h new file mode 100644 index 000000000000..4a1ec714fbb5 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_common.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_COMMON_H +#define __MFC_COMMON_H __FILE__ + +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/sched/clock.h> +#include <linux/vmalloc.h> +#include <media/videobuf2-dma-sg.h> +#include <linux/cacheflush.h> +#include "mfc_data_struct.h" +#include "mfc_regs.h" +#include "mfc_debug.h" +#include "mfc_media.h" + +#define MFC_DRIVER_INFO 230330 + +#define MFC_MAX_REF_BUFS 2 +#define MFC_FRAME_PLANES 2 +#define MFC_INFO_INIT_FD -1 +#define MFC_FW_MEM_SIZE SZ_1M /* 1MB */ + +/* MFC video node */ +#define EXYNOS_VIDEONODE_MFC_DEC 6 +#define EXYNOS_VIDEONODE_MFC_ENC 7 +#define EXYNOS_VIDEONODE_MFC_DEC_DRM 8 +#define EXYNOS_VIDEONODE_MFC_ENC_DRM 9 +#define EXYNOS_VIDEONODE_MFC_ENC_OTF 10 +#define EXYNOS_VIDEONODE_MFC_ENC_OTF_DRM 11 + +/* Core information */ +#define MFC_DEC_DEFAULT_CORE 0 +#define MFC_ENC_DEFAULT_CORE 0 +#define MFC_SURPLUS_CORE 1 + +/* Interrupt timeout */ +#define MFC_INT_TIMEOUT 4000 +/* Interrupt short timeout */ +#define MFC_INT_SHORT_TIMEOUT 800 +/* hwlock timeout */ +#define MFC_HWLOCK_TIMEOUT 12000 +/* Busy wait timeout */ +#define MFC_BW_TIMEOUT 500 + +/* Interrupt timeout count*/ +#define MFC_INT_TIMEOUT_CNT 3 + +/* + * This value guarantees 299.4msec ~ 2.25sec according to MFC clock (668MHz ~ 89MHz) + * related with MFC_REG_TIMEOUT_VALUE + */ +#define MFC_TIMEOUT_VALUE 200000000 +/* 250ms is the mfc firmware timeout value*/ +#define MFC_TIMEOUT_VALUE_IN_MSEC 250 + +#define DEFAULT_TAG (0xE05) +#define IGNORE_TAG (0xD5C) /* ex) encoder DRC */ +#define HEADER_TAG (0xC5D) +#define UNUSED_TAG (-1) + +#define MFC_NO_INSTANCE_SET -1 + +#define STUFF_BYTE 4 +#define MFC_EXTRA_DPB 5 +#define MFC_ALL_AVAILABLE_DPB 0xffffffffffffffff + +#define MFC_BASE_MASK (BIT(17) - 1) + +/* Error & Warning */ +#define mfc_get_err(x) (((x) >> MFC_REG_ERR_STATUS_SHIFT) \ + & MFC_REG_ERR_STATUS_MASK) +#define mfc_get_warn(x) (((x) >> MFC_REG_WARN_STATUS_SHIFT) \ + & MFC_REG_WARN_STATUS_MASK) + +#define vb_to_mfc_buf(x) \ + container_of(x, struct mfc_buf, vb.vb2_buf) + +#define fh_to_mfc_ctx(x) \ + container_of(x, struct mfc_ctx, fh) + +#define MFC_FMT_STREAM BIT(0) +#define MFC_FMT_FRAME BIT(1) +#define MFC_FMT_10BIT BIT(2) +#define MFC_FMT_422 BIT(3) +#define MFC_FMT_RGB BIT(4) +#define MFC_FMT_SBWC BIT(5) +#define MFC_FMT_SBWCL BIT(6) +#define MFC_FMT_DEC BIT(7) +#define MFC_FMT_ENC BIT(8) +#define MFC_FMT_SBWCLH BIT(9) +#define MFC_FMT_SBWCLHFR BIT(10) + +/* node check */ +#define IS_DEC_NODE(n) ({ \ + typeof(n) _n = (n); \ + ((_n == EXYNOS_VIDEONODE_MFC_DEC) || (_n == EXYNOS_VIDEONODE_MFC_DEC_DRM)); \ +}) +#define IS_ENC_NODE(n) ({ \ + typeof(n) _n = (n); \ + ((_n == EXYNOS_VIDEONODE_MFC_ENC) || (_n == EXYNOS_VIDEONODE_MFC_ENC_DRM) || \ + (_n == EXYNOS_VIDEONODE_MFC_ENC_OTF) || \ + (_n == EXYNOS_VIDEONODE_MFC_ENC_OTF_DRM)); \ +}) + +#define IS_MULTI_CORE_DEVICE(dev) ((dev)->num_core > 1) +#define IS_SINGLE_MODE(ctx) ((ctx)->op_mode == MFC_OP_SINGLE) +#define IS_TWO_MODE1(ctx) ((ctx)->op_mode == MFC_OP_TWO_MODE1) +#define IS_TWO_MODE2(ctx) ((ctx)->op_mode == MFC_OP_TWO_MODE2) +#define IS_MULTI_MODE(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->op_mode == MFC_OP_TWO_MODE1) || \ + (_ctx->op_mode == MFC_OP_TWO_MODE2)); \ +}) + +#define IS_SWITCH_SINGLE_MODE(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->op_mode == MFC_OP_SWITCH_TO_SINGLE) || \ + (_ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2)); \ +}) + +#define IS_SWITCH_SINGLE_MODE(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->op_mode == MFC_OP_SWITCH_TO_SINGLE) || \ + (_ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2)); \ +}) + +/* Extra information for Decoder */ +#define DEC_SET_DUAL_DPB BIT(0) +#define DEC_SET_DYNAMIC_DPB BIT(1) +#define DEC_SET_LAST_FRAME_INFO BIT(2) +#define DEC_SET_SKYPE_FLAG BIT(3) +#define DEC_SET_HDR10_PLUS BIT(4) +/* new C2_INTERFACE: DISPLAY_DELAY, FRAME_POC */ +#define DEC_SET_C2_INTERFACE BIT(6) +#define DEC_SET_FRAME_ERR_TYPE BIT(7) +#define DEC_SET_OPERATING_FPS BIT(8) +#define DEC_SET_HDR10_PLUS_FULL BIT(9) +#define DEC_SET_BUF_FLAG_CTRL BIT(16) +#define DEC_SET_PRIORITY BIT(23) + +/* Extra information for Encoder */ +#define ENC_SET_RGB_INPUT BIT(0) +#define ENC_SET_SPARE_SIZE BIT(1) +#define ENC_SET_TEMP_SVC_CH BIT(2) +#define ENC_SET_SKYPE_FLAG BIT(3) +#define ENC_SET_ROI_CONTROL BIT(4) +#define ENC_SET_QP_BOUND_PB BIT(5) +#define ENC_SET_FIXED_SLICE BIT(6) +#define ENC_SET_PVC_MODE BIT(7) +#define ENC_SET_RATIO_OF_INTRA BIT(8) +#define ENC_SET_COLOR_ASPECT BIT(9) +#define ENC_SET_HP_BITRATE_CONTROL BIT(10) +#define ENC_SET_STATIC_INFO BIT(11) +#define ENC_SET_HDR10_PLUS BIT(12) +#define ENC_SET_VP9_PROFILE_LEVEL BIT(13) +#define ENC_SET_DROP_CONTROL BIT(14) +#define ENC_SET_CHROMA_QP_CONTROL BIT(15) +#define ENC_SET_BUF_FLAG_CTRL BIT(16) +#define ENC_SET_GDC_VOTF BIT(17) +#define ENC_SET_OPERATING_FPS BIT(18) +#define ENC_SET_AVERAGE_QP BIT(19) +#define ENC_SET_MV_SEARCH_MODE BIT(20) +#define ENC_SET_GOP_CTRL BIT(21) +#define ENC_SET_HDR10_PLUS_STAT_INFO BIT(22) +#define ENC_SET_PRIORITY BIT(23) +#define ENC_SET_CAPABILITY BIT(24) +#define ENC_SET_IFRAME_SIZE BIT(25) +#define ENC_SET_TIMING_INFO_ENABLE BIT(26) + +#define MFC_FEATURE_SUPPORT(dev, f) ({ \ + typeof(f) _f = (f); \ + (_f).support && ((dev)->fw_date >= (_f).version); \ +}) + +/* Low memory check */ +#define IS_LOW_MEM (totalram_pages() <= ((SZ_1G + SZ_512M) >> PAGE_SHIFT)) + +static inline int mfc_core_get_pwr_ref_cnt(struct mfc_core *core) +{ + return atomic_read(&core->pm.pwr_ref); +} + +static inline int mfc_core_get_clk_ref_cnt(struct mfc_core *core) +{ + return atomic_read(&core->clk_ref); +} + +#endif /* __MFC_COMMON_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h new file mode 100644 index 000000000000..cf37700d78a0 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h @@ -0,0 +1,554 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_media.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_MEDIA_H +#define __MFC_MEDIA_H __FILE__ + +/* RGB formats */ +#define V4L2_PIX_FMT_RGB32X v4l2_fourcc('R', 'G', 'B', 'X') /* 32 RGB-8-8-8-8 */ + +/* compressed formats */ +#define V4L2_PIX_FMT_FIMV v4l2_fourcc('F', 'I', 'M', 'V') /* FIMV */ +#define V4L2_PIX_FMT_FIMV1 v4l2_fourcc('F', 'I', 'M', '1') /* FIMV1 */ +#define V4L2_PIX_FMT_FIMV2 v4l2_fourcc('F', 'I', 'M', '2') /* FIMV2 */ +#define V4L2_PIX_FMT_FIMV3 v4l2_fourcc('F', 'I', 'M', '3') /* FIMV3 */ +#define V4L2_PIX_FMT_FIMV4 v4l2_fourcc('F', 'I', 'M', '4') /* FIMV4 */ +#define V4L2_PIX_FMT_AV1 v4l2_fourcc('A', 'V', '0', '1') /* AV1 */ + +enum v4l2_mpeg_mfc51_video_frame_type { + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_NOT_CODED = 0, + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_I_FRAME = 1, + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_P_FRAME = 2, + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_B_FRAME = 3, + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_SKIPPED = 4, + V4L2_MPEG_MFC51_VIDEO_FRAME_TYPE_OTHERS = 5, +}; + +/* new entry for enum v4l2_mpeg_video_mpeg4_level */ +#define V4L2_MPEG_VIDEO_MPEG4_LEVEL_6 8 + +/* new entry for enum v4l2_mpeg_video_header_mode */ +#define V4L2_MPEG_VIDEO_HEADER_MODE_AT_THE_READY 2 + +/* new entry for enum v4l2_mpeg_video_multi_slice_mode */ +#define V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW 3 +#define V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES 4 + +/* new entry for enum v4l2_mpeg_video_h264_profile */ +#define V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH 17 + +#define V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_S_B \ + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY + +#define V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH V4L2_CID_MPEG_VIDEO_GOP_SIZE +#define V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH V4L2_CID_MPEG_VIDEO_BITRATE +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH \ + V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE + +/* CID base for MFC controls (MPEG_CLASS) */ +#define V4L2_CID_MPEG_MFC_BASE (V4L2_CTRL_CLASS_CODEC | 0x2000) + +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_AVAIL \ + (V4L2_CID_MPEG_MFC_BASE + 1) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRGMENT_ID \ + (V4L2_CID_MPEG_MFC_BASE + 2) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_INFO \ + (V4L2_CID_MPEG_MFC_BASE + 3) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_GRID_POS \ + (V4L2_CID_MPEG_MFC_BASE + 4) +#define V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB \ + (V4L2_CID_MPEG_MFC_BASE + 5) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG \ + (V4L2_CID_MPEG_MFC_BASE + 6) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 7) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA \ + (V4L2_CID_MPEG_MFC_BASE + 8) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA \ + (V4L2_CID_MPEG_MFC_BASE + 9) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA_BOT \ + (V4L2_CID_MPEG_MFC_BASE + 10) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA_BOT \ + (V4L2_CID_MPEG_MFC_BASE + 11) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_GENERATED \ + (V4L2_CID_MPEG_MFC_BASE + 12) +#define V4L2_CID_MPEG_MFC51_VIDEO_CHECK_STATE \ + (V4L2_CID_MPEG_MFC_BASE + 13) +#define V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS \ + (V4L2_CID_MPEG_MFC_BASE + 14) +#define V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR \ + (V4L2_CID_MPEG_MFC_BASE + 15) +#define V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR \ + (V4L2_CID_MPEG_MFC_BASE + 16) +#define V4L2_CID_MPEG_MFC51_VIDEO_STREAM_SIZE \ + (V4L2_CID_MPEG_MFC_BASE + 17) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_COUNT \ + (V4L2_CID_MPEG_MFC_BASE + 18) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 19) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE \ + (V4L2_CID_MPEG_MFC_BASE + 20) +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 21) +#define V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_TIME_RES \ + (V4L2_CID_MPEG_MFC_BASE + 22) +#define V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_FRM_DELTA \ + (V4L2_CID_MPEG_MFC_BASE + 23) +#define V4L2_CID_MPEG_MFC51_VIDEO_H263_RC_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 24) +#define V4L2_CID_MPEG_MFC6X_VIDEO_FRAME_DELTA \ + (V4L2_CID_MPEG_MFC_BASE + 25) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA1 \ + (V4L2_CID_MPEG_MFC_BASE + 26) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_LUMA \ + (V4L2_CID_MPEG_MFC_BASE + 27) +#define V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_CHROMA \ + (V4L2_CID_MPEG_MFC_BASE + 28) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_POC \ + (V4L2_CID_MPEG_MFC_BASE + 29) +#define V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG \ + (V4L2_CID_MPEG_MFC_BASE + 30) +#define V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG \ + (V4L2_CID_MPEG_MFC_BASE + 31) +#define V4L2_CID_MPEG_VIDEO_GDC_VOTF \ + (V4L2_CID_MPEG_MFC_BASE + 32) +#define V4L2_CID_MPEG_VIDEO_FRAME_ERROR_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 33) +#define V4L2_CID_MPEG_VIDEO_GOP_CTRL \ + (V4L2_CID_MPEG_MFC_BASE + 35) +#define V4L2_CID_MPEG_VIDEO_PRIORITY \ + (V4L2_CID_MPEG_MFC_BASE + 36) +#define V4L2_CID_MPEG_VIDEO_MAX_IFRAME_SIZE \ + (V4L2_CID_MPEG_MFC_BASE + 37) +#define V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CB \ + (V4L2_CID_MPEG_MFC_BASE + 38) +#define V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CR \ + (V4L2_CID_MPEG_MFC_BASE + 39) +#define V4L2_CID_MPEG_VIDEO_GET_DISPLAY_DELAY \ + (V4L2_CID_MPEG_MFC_BASE + 40) +#define V4L2_CID_MPEG_VIDEO_DROP_CONTROL \ + (V4L2_CID_MPEG_MFC_BASE + 41) +#define V4L2_CID_MPEG_VIDEO_H264_MVC_VIEW_ID \ + (V4L2_CID_MPEG_MFC_BASE + 42) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS \ + (V4L2_CID_MPEG_MFC_BASE + 43) +#define V4L2_CID_MPEG_MFC51_VIDEO_I_FRAME_DECODING \ + (V4L2_CID_MPEG_MFC_BASE + 44) +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 45) +#define V4L2_CID_MPEG_VIDEO_H264_PREPEND_SPSPPS_TO_IDR \ + (V4L2_CID_MPEG_MFC_BASE + 46) +#define V4L2_CID_MPEG_VIDEO_DECODER_IMMEDIATE_DISPLAY \ + (V4L2_CID_MPEG_MFC_BASE + 47) +#define V4L2_CID_MPEG_VIDEO_DECODER_DECODING_TIMESTAMP_MODE \ + (V4L2_CID_MPEG_MFC_BASE + 48) +#define V4L2_CID_MPEG_VIDEO_DECODER_WAIT_DECODING_START \ + (V4L2_CID_MPEG_MFC_BASE + 49) +#define V4L2_CID_MPEG_VIDEO_QOS_RATIO \ + (V4L2_CID_MPEG_MFC_BASE + 50) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT \ + (V4L2_CID_MPEG_MFC_BASE + 51) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH \ + (V4L2_CID_MPEG_MFC_BASE + 52) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT0 \ + (V4L2_CID_MPEG_MFC_BASE + 53) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT1 \ + (V4L2_CID_MPEG_MFC_BASE + 54) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT2 \ + (V4L2_CID_MPEG_MFC_BASE + 55) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT3 \ + (V4L2_CID_MPEG_MFC_BASE + 56) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT4 \ + (V4L2_CID_MPEG_MFC_BASE + 57) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT5 \ + (V4L2_CID_MPEG_MFC_BASE + 58) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT6 \ + (V4L2_CID_MPEG_MFC_BASE + 59) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_VERSION \ + (V4L2_CID_MPEG_MFC_BASE + 60) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_RC_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 61) +#define V4L2_CID_MPEG_VIDEO_VP8_MIN_QP \ + (V4L2_CID_MPEG_MFC_BASE + 62) +#define V4L2_CID_MPEG_VIDEO_VP8_MAX_QP \ + (V4L2_CID_MPEG_MFC_BASE + 63) +#define V4L2_CID_MPEG_VIDEO_VP8_I_FRAME_QP \ + (V4L2_CID_MPEG_MFC_BASE + 64) +#define V4L2_CID_MPEG_VIDEO_VP8_P_FRAME_QP \ + (V4L2_CID_MPEG_MFC_BASE + 65) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_OF_PARTITIONS \ + (V4L2_CID_MPEG_MFC_BASE + 66) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_LEVEL \ + (V4L2_CID_MPEG_MFC_BASE + 67) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_SHARPNESS \ + (V4L2_CID_MPEG_MFC_BASE + 68) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_GOLDEN_FRAMESEL \ + (V4L2_CID_MPEG_MFC_BASE + 69) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_GF_REFRESH_PERIOD \ + (V4L2_CID_MPEG_MFC_BASE + 70) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 71) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER0 \ + (V4L2_CID_MPEG_MFC_BASE + 72) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER1 \ + (V4L2_CID_MPEG_MFC_BASE + 73) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER2 \ + (V4L2_CID_MPEG_MFC_BASE + 74) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_REF_NUMBER_FOR_PFRAMES \ + (V4L2_CID_MPEG_MFC_BASE + 75) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_DISABLE_INTRA_MD4X4 \ + (V4L2_CID_MPEG_MFC_BASE + 76) +#define V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_TEMPORAL_LAYER \ + (V4L2_CID_MPEG_MFC_BASE + 77) +#define V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT \ + (V4L2_CID_MPEG_MFC_BASE + 78) +#define V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH \ + (V4L2_CID_MPEG_MFC_BASE + 79) +#define V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT0 \ + (V4L2_CID_MPEG_MFC_BASE + 80) +#define V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT1 \ + (V4L2_CID_MPEG_MFC_BASE + 81) +#define V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT2 \ + (V4L2_CID_MPEG_MFC_BASE + 82) + +/* ~ 90 : Reserved for using later */ + +#define V4L2_CID_MPEG_MFC_GET_VERSION_INFO \ + (V4L2_CID_MPEG_MFC_BASE + 91) +#define V4L2_CID_MPEG_MFC_GET_EXTRA_BUFFER_SIZE \ + (V4L2_CID_MPEG_MFC_BASE + 92) +#define V4L2_CID_MPEG_MFC_SET_DUAL_DPB_MODE \ + (V4L2_CID_MPEG_MFC_BASE + 93) +#define V4L2_CID_MPEG_MFC_SET_DYNAMIC_DPB_MODE \ + (V4L2_CID_MPEG_MFC_BASE + 95) +#define V4L2_CID_MPEG_MFC_SET_USER_SHARED_HANDLE \ + (V4L2_CID_MPEG_MFC_BASE + 96) +#define V4L2_CID_MPEG_MFC_GET_EXT_INFO \ + (V4L2_CID_MPEG_MFC_BASE + 97) +#define V4L2_CID_MPEG_MFC_SET_BUF_PROCESS_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 98) +#define V4L2_CID_MPEG_MFC_GET_10BIT_INFO \ + (V4L2_CID_MPEG_MFC_BASE + 99) +#define V4L2_CID_MPEG_MFC_H264_ENABLE_LTR \ + (V4L2_CID_MPEG_MFC_BASE + 100) +#define V4L2_CID_MPEG_MFC_H264_MARK_LTR \ + (V4L2_CID_MPEG_MFC_BASE + 101) +#define V4L2_CID_MPEG_MFC_H264_USE_LTR \ + (V4L2_CID_MPEG_MFC_BASE + 102) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB_ROW \ + (V4L2_CID_MPEG_MFC_BASE + 103) +#define V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY \ + (V4L2_CID_MPEG_MFC_BASE + 104) +#define V4L2_CID_MPEG_MFC_CONFIG_QP \ + (V4L2_CID_MPEG_MFC_BASE + 105) +#define V4L2_CID_MPEG_MFC_H264_VUI_RESTRICTION_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 106) +#define V4L2_CID_MPEG_MFC_GET_DRIVER_INFO \ + (V4L2_CID_MPEG_MFC_BASE + 107) +#define V4L2_CID_MPEG_MFC_CONFIG_QP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 108) +#define V4L2_CID_MPEG_MFC_HDR_USER_SHARED_HANDLE \ + (V4L2_CID_MPEG_MFC_BASE + 109) + +/* + * CIDs for HEVC encoding. + * Even though it was merged to mainline, do not use it for HAL code compatibility. + * V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (V4L2_CID_MPEG_MFC_BASE + 110) + * V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (V4L2_CID_MPEG_MFC_BASE + 111) + * V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (V4L2_CID_MPEG_MFC_BASE + 112) + * V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP (V4L2_CID_MPEG_MFC_BASE + 113) + * V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP (V4L2_CID_MPEG_MFC_BASE + 114) + */ +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 115) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 116) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER \ + (V4L2_CID_MPEG_MFC_BASE + 117) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP \ + (V4L2_CID_MPEG_MFC_BASE + 118) +/* empty number */ +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_RC_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 122) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TIER_FLAG \ + (V4L2_CID_MPEG_MFC_BASE + 123) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_PARTITION_DEPTH \ + (V4L2_CID_MPEG_MFC_BASE + 124) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES \ + (V4L2_CID_MPEG_MFC_BASE + 125) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_DISABLE \ + (V4L2_CID_MPEG_MFC_BASE + 126) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_SLICE_BOUNDARY \ + (V4L2_CID_MPEG_MFC_BASE + 127) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_BETA_OFFSET_DIV2 \ + (V4L2_CID_MPEG_MFC_BASE + 128) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_TC_OFFSET_DIV2 \ + (V4L2_CID_MPEG_MFC_BASE + 129) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 130) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_PERIOD \ + (V4L2_CID_MPEG_MFC_BASE + 131) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LOSSLESS_CU_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 132) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 133) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WAVEFRONT_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 134) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LTR_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 135) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_USER_REF \ + (V4L2_CID_MPEG_MFC_BASE + 136) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STORE_REF \ + (V4L2_CID_MPEG_MFC_BASE + 137) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIGN_DATA_HIDING \ + (V4L2_CID_MPEG_MFC_BASE + 138) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_GENERAL_PB_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 139) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TEMPORAL_ID_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 140) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STRONG_SMOTHING_FLAG \ + (V4L2_CID_MPEG_MFC_BASE + 141) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1 \ + (V4L2_CID_MPEG_MFC_BASE + 142) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_DARK \ + (V4L2_CID_MPEG_MFC_BASE + 143) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH \ + (V4L2_CID_MPEG_MFC_BASE + 144) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_STATIC \ + (V4L2_CID_MPEG_MFC_BASE + 145) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY \ + (V4L2_CID_MPEG_MFC_BASE + 146) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT \ + (V4L2_CID_MPEG_MFC_BASE + 147) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_TMV_PREDICTION \ + (V4L2_CID_MPEG_MFC_BASE + 148) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 149) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_QP_INDEX_CR \ + (V4L2_CID_MPEG_MFC_BASE + 150) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_QP_INDEX_CB \ + (V4L2_CID_MPEG_MFC_BASE + 151) +#define V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD \ + (V4L2_CID_MPEG_MFC_BASE + 152) +#define V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR \ + (V4L2_CID_MPEG_MFC_BASE + 153) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH \ + (V4L2_CID_MPEG_MFC_BASE + 154) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0 \ + (V4L2_CID_MPEG_MFC_BASE + 155) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1 \ + (V4L2_CID_MPEG_MFC_BASE + 156) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2 \ + (V4L2_CID_MPEG_MFC_BASE + 157) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3 \ + (V4L2_CID_MPEG_MFC_BASE + 158) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4 \ + (V4L2_CID_MPEG_MFC_BASE + 159) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5 \ + (V4L2_CID_MPEG_MFC_BASE + 160) +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6 \ + (V4L2_CID_MPEG_MFC_BASE + 161) +#define V4L2_CID_MPEG_MFC_HEIF_MODE \ + (V4L2_CID_MPEG_MFC_BASE + 162) + +/* CIDs for VP9 encoding. Number gaps are for compatibility */ +#define V4L2_CID_MPEG_VIDEO_VP9_VERSION \ + (V4L2_CID_MPEG_MFC_BASE + 163) +#define V4L2_CID_MPEG_VIDEO_VP9_RC_FRAME_RATE \ + (V4L2_CID_MPEG_MFC_BASE + 164) +#define V4L2_CID_MPEG_VIDEO_VP9_MIN_QP \ + (V4L2_CID_MPEG_MFC_BASE + 165) +#define V4L2_CID_MPEG_VIDEO_VP9_MAX_QP \ + (V4L2_CID_MPEG_MFC_BASE + 166) +#define V4L2_CID_MPEG_VIDEO_VP9_I_FRAME_QP \ + (V4L2_CID_MPEG_MFC_BASE + 167) +#define V4L2_CID_MPEG_VIDEO_VP9_P_FRAME_QP \ + (V4L2_CID_MPEG_MFC_BASE + 168) +#define V4L2_CID_MPEG_VIDEO_VP9_GOLDEN_FRAMESEL \ + (V4L2_CID_MPEG_MFC_BASE + 169) +#define V4L2_CID_MPEG_VIDEO_VP9_GF_REFRESH_PERIOD \ + (V4L2_CID_MPEG_MFC_BASE + 170) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHY_QP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 171) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_QP \ + (V4L2_CID_MPEG_MFC_BASE + 172) +#define V4L2_CID_MPEG_VIDEO_VP9_REF_NUMBER_FOR_PFRAMES \ + (V4L2_CID_MPEG_MFC_BASE + 173) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER \ + (V4L2_CID_MPEG_MFC_BASE + 174) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH \ + (V4L2_CID_MPEG_MFC_BASE + 175) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT0 \ + (V4L2_CID_MPEG_MFC_BASE + 176) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT1 \ + (V4L2_CID_MPEG_MFC_BASE + 177) +#define V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT2 \ + (V4L2_CID_MPEG_MFC_BASE + 178) +#define V4L2_CID_MPEG_VIDEO_VP9_MAX_PARTITION_DEPTH \ + (V4L2_CID_MPEG_MFC_BASE + 179) +#define V4L2_CID_MPEG_VIDEO_VP9_DISABLE_INTRA_PU_SPLIT \ + (V4L2_CID_MPEG_MFC_BASE + 180) +#define V4L2_CID_MPEG_VIDEO_DISABLE_IVF_HEADER \ + (V4L2_CID_MPEG_MFC_BASE + 181) +/* + * Even though it was merged to mainline, do not use it for HAL code compatibility. + * V4L2_CID_MPEG_VIDEO_VP9_LEVEL (V4L2_CID_MPEG_MFC_BASE + 183) + */ +#define V4L2_CID_MPEG_VIDEO_UNCOMP_FMT \ + (V4L2_CID_MPEG_MFC_BASE + 184) +#define V4L2_CID_MPEG_VIDEO_SKIP_LAZY_UNMAP \ + (V4L2_CID_MPEG_MFC_BASE + 185) +#define V4L2_CID_MPEG_VIDEO_MIN_QUALITY \ + (V4L2_CID_MPEG_MFC_BASE + 186) + +/* CIDs for new common interface */ +#define V4L2_CID_MPEG_VIDEO_ROI_CONTROL \ + (V4L2_CID_MPEG_MFC_BASE + 190) +#define V4L2_CID_MPEG_VIDEO_ROI_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 191) +#define V4L2_CID_MPEG_VIDEO_RC_PVC_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 192) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_SHORTTERM_MAX_LAYER \ + (V4L2_CID_MPEG_MFC_BASE + 193) +#define V4L2_CID_MPEG_VIDEO_BLACK_BAR_DETECT \ + (V4L2_CID_MPEG_MFC_BASE + 194) +#define V4L2_CID_MPEG_MFC_H264_NUM_OF_LTR \ + (V4L2_CID_MPEG_MFC_BASE + 195) +#define V4L2_CID_MPEG_VIDEO_WEIGHTED_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 196) +#define V4L2_CID_MPEG_VIDEO_YSUM \ + (V4L2_CID_MPEG_MFC_BASE + 197) +#define V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA \ + (V4L2_CID_MPEG_MFC_BASE + 198) +#define V4L2_CID_MPEG_VIDEO_HIERARCHICAL_BITRATE_CTRL \ + (V4L2_CID_MPEG_MFC_BASE + 199) +#define V4L2_CID_MPEG_VIDEO_DECODING_ORDER \ + (V4L2_CID_MPEG_MFC_BASE + 200) + +/* QP BOUND interface */ +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 201) +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 202) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 203) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 204) +#define V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 205) +#define V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 206) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 207) +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 208) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 209) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 210) +#define V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 211) +#define V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P \ + (V4L2_CID_MPEG_MFC_BASE + 212) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 213) +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 214) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 215) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 216) +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 217) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B \ + (V4L2_CID_MPEG_MFC_BASE + 218) + +/* SEI & VUI PARSING FOR HDR DISPLAY */ +#define V4L2_CID_MPEG_VIDEO_SEI_MAX_PIC_AVERAGE_LIGHT \ + (V4L2_CID_MPEG_MFC_BASE + 219) +#define V4L2_CID_MPEG_VIDEO_SEI_MAX_CONTENT_LIGHT \ + (V4L2_CID_MPEG_MFC_BASE + 220) +#define V4L2_CID_MPEG_VIDEO_SEI_MAX_DISPLAY_LUMINANCE \ + (V4L2_CID_MPEG_MFC_BASE + 221) +#define V4L2_CID_MPEG_VIDEO_SEI_MIN_DISPLAY_LUMINANCE \ + (V4L2_CID_MPEG_MFC_BASE + 222) +#define V4L2_CID_MPEG_VIDEO_MATRIX_COEFFICIENTS \ + (V4L2_CID_MPEG_MFC_BASE + 223) +#define V4L2_CID_MPEG_VIDEO_FORMAT \ + (V4L2_CID_MPEG_MFC_BASE + 224) +#define V4L2_CID_MPEG_VIDEO_SEI_WHITE_POINT \ + (V4L2_CID_MPEG_MFC_BASE + 225) +#define V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_0 \ + (V4L2_CID_MPEG_MFC_BASE + 226) +#define V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_1 \ + (V4L2_CID_MPEG_MFC_BASE + 227) +#define V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_2 \ + (V4L2_CID_MPEG_MFC_BASE + 228) +#define V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG \ + (V4L2_CID_MPEG_MFC_BASE + 229) +#define V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES \ + (V4L2_CID_MPEG_MFC_BASE + 230) +#define V4L2_CID_MPEG_VIDEO_TRANSFER_CHARACTERISTICS \ + (V4L2_CID_MPEG_MFC_BASE + 231) +#define V4L2_CID_MPEG_VIDEO_STATIC_INFO_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 232) +#define V4L2_CID_MPEG_VIDEO_MV_SEARCH_MODE \ + (V4L2_CID_MPEG_MFC_BASE + 233) +#define V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L0 \ + (V4L2_CID_MPEG_MFC_BASE + 234) +#define V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L1 \ + (V4L2_CID_MPEG_MFC_BASE + 235) +#define V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L0 \ + (V4L2_CID_MPEG_MFC_BASE + 236) +#define V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L1 \ + (V4L2_CID_MPEG_MFC_BASE + 237) + +/* CID for AV1 decoding interface */ +#define V4L2_CID_MPEG_MFC_AV1_FILM_GRAIN_USER_SHARED_HANDLE \ + (V4L2_CID_MPEG_MFC_BASE + 240) +#define V4L2_CID_MPEG_MFC_AV1_FILM_GRAIN_PRESENT \ + (V4L2_CID_MPEG_MFC_BASE + 241) + +#define V4L2_CID_MPEG_MFC_HDR10_PLUS_STAT_USER_SHARED_HANDLE \ + (V4L2_CID_MPEG_MFC_BASE + 242) +#define V4L2_CID_MPEG_MFC_HDR10_PLUS_STAT_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 243) + +/* CID for encoding info interface */ +#define V4L2_CID_MPEG_VIDEO_WP_TWO_PASS_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 260) +#define V4L2_CID_MPEG_VIDEO_ADAPTIVE_GOP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 261) +#define V4L2_CID_MPEG_VIDEO_SUM_SKIP_MB \ + (V4L2_CID_MPEG_MFC_BASE + 262) +#define V4L2_CID_MPEG_VIDEO_SUM_INTRA_MB \ + (V4L2_CID_MPEG_MFC_BASE + 263) +#define V4L2_CID_MPEG_VIDEO_SUM_ZERO_MV_MB \ + (V4L2_CID_MPEG_MFC_BASE + 264) +#define V4L2_CID_MPEG_VIDEO_MV_HOR_RANGE \ + (V4L2_CID_MPEG_MFC_BASE + 265) +#define V4L2_CID_MPEG_VIDEO_MV_VER_RANGE \ + (V4L2_CID_MPEG_MFC_BASE + 266) +#define V4L2_CID_MPEG_MFC_H264_SUB_GOP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 267) +#define V4L2_CID_MPEG_MFC_H264_SUB_GOP_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 268) +#define V4L2_CID_MPEG_MFC_HEVC_SUB_GOP_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 269) +#define V4L2_CID_MPEG_MFC_HEVC_SUB_GOP_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 270) +#define V4L2_CID_MPEG_MFC_TIMING_INFO_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 271) +#define V4L2_CID_MPEG_MFC_MULTI_VIEW_ENABLE \ + (V4L2_CID_MPEG_MFC_BASE + 272) +#define V4L2_CID_MPEG_MFC_MULTI_VIEW_MAIN_TYPE \ + (V4L2_CID_MPEG_MFC_BASE + 273) +#endif /* __MFC_MEDIA_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c new file mode 100644 index 000000000000..dfb58ddcbd5d --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_mem.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/property.h> +#include <linux/dma-buf.h> +#include <linux/iosys-map.h> +#include <linux/iommu.h> +#include <linux/dma-heap.h> +#include <linux/of_device.h> + +#include "mfc_mem.h" + +static int mfc_mem_fw_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf) +{ +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + struct page *fw_pages; + unsigned long nr_pages = special_buf->size >> PAGE_SHIFT; + int ret; + + special_buf->cma_area = dev->device->cma_area; + fw_pages = cma_alloc(special_buf->cma_area, nr_pages, 0, false); + if (!fw_pages) + return -ENOMEM; + + special_buf->sgt = kmalloc((*special_buf->sgt), GFP_KERNEL); + if (!special_buf->sgt) + goto err_cma_alloc; + + ret = sg_alloc_table(special_buf->sgt, 1, GFP_KERNEL); + if (ret) { + mfc_dev_err("Failed to allocate sg_table\n"); + goto err_sg_alloc; + } + + sg_set_page(special_buf->sgt->sgl, fw_pages, special_buf->size, 0); + + special_buf->paddr = page_to_phys(fw_pages); + special_buf->vaddr = phys_to_virt(special_buf->paddr); + + return 0; + +err_sg_alloc: + kfree(special_buf->sgt); + special_buf->sgt = NULL; +err_cma_alloc: + cma_release(special_buf->cma_area, fw_pages, nr_pages); + return -ENOMEM; +#else + special_buf->vaddr = dma_alloc_coherent(dev->mem_dev[BANK_L_CTX], + MFC_FW_MEM_SIZE, + &special_buf->daddr, + GFP_KERNEL); + if (!special_buf->vaddr) + return -ENOMEM; + special_buf->paddr = dma_to_phys(dev->device, special_buf->daddr); + mfc_dev_info("mapped on 0x%lx with size of 0x%lx paddr 0x%lx daddr 0x%lx\n", + (unsigned long)special_buf->vaddr, + special_buf->size, + (unsigned long)special_buf->paddr, + (unsigned long)special_buf->daddr); + return 0; +#endif +} + +static void mfc_mem_fw_free(struct mfc_special_buf *special_buf) +{ +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + if (special_buf->sgt) { + cma_release(special_buf->cma_area, phys_to_page(special_buf->paddr), + (special_buf->size >> PAGE_SHIFT)); + sg_free_table(special_buf->sgt); + kfree(special_buf->sgt); + } +#endif + special_buf->sgt = NULL; + special_buf->dma_buf = NULL; + special_buf->attachment = NULL; + special_buf->daddr = 0; + special_buf->vaddr = NULL; + special_buf->name[0] = 0; +} + +static void dma_release(struct dma_buf *dmabuf) +{ + struct dma_priv *priv = dmabuf->priv; + + dma_free_coherent(priv->dev, priv->size, priv->vaddr, priv->dma_addr); +} + +static struct sg_table *dma_map(struct dma_buf_attachment *attach, enum dma_data_direction dir) +{ + struct dma_priv *priv = attach->dmabuf->priv; + struct sg_table *sgt; + int ret; + + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) + return ERR_PTR(-ENOMEM); + + ret = sg_alloc_table(sgt, 1, GFP_KERNEL); + if (ret) { + kfree(sgt); + return ERR_PTR(ret); + } + + sg_set_page(sgt->sgl, virt_to_page(priv->vaddr), priv->size, + offset_in_page(priv->vaddr)); + sg_dma_address(sgt->sgl) = priv->dma_addr; + sg_dma_len(sgt->sgl) = priv->size; + + return sgt; +} + +static void dma_unmap(struct dma_buf_attachment *attach, + struct sg_table *sgt, enum dma_data_direction dir) +{ + sg_free_table(sgt); + kfree(sgt); +} + +static int dma_vmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ + struct dma_priv *priv = dmabuf->priv; + + if (!priv || !priv->vaddr) + return -EINVAL; + + map->vaddr = priv->vaddr; + return 0; +} + +static void dma_vunmap(struct dma_buf *dmabuf, struct iosys_map *map) +{ +} + +static const struct dma_buf_ops dma_ops = { + .release = dma_release, + .map_dma_buf = dma_map, + .unmap_dma_buf = dma_unmap, + .vmap = dma_vmap, + .vunmap = dma_vunmap, +}; + +static struct dma_buf *create_dma_buf(struct mfc_dev *dev, struct mfc_special_buf *special_buf) +{ + struct dma_priv *priv; + struct dma_buf_export_info exp_info; + + priv = devm_kzalloc(dev->mem_dev[BANK_R_CTX], sizeof(*priv), GFP_KERNEL); + if (!priv) + goto err_alloc; + + priv->dev = dev->mem_dev[BANK_R_CTX]; + priv->size = special_buf->size; + + priv->vaddr = dma_alloc_coherent(dev->mem_dev[BANK_R_CTX], + priv->size, &priv->dma_addr, GFP_KERNEL); + if (!priv->vaddr) { + kfree(priv); + goto err_alloc; + } + + exp_info.ops = &dma_ops; + exp_info.size = priv->size; + exp_info.flags = O_RDWR; + exp_info.exp_name = "ctx_buf"; + exp_info.priv = priv; + exp_info.owner = THIS_MODULE; + + return dma_buf_export(&exp_info); + +err_alloc: + return ERR_PTR(-ENOMEM); +} + +static int mfc_mem_dma_heap_alloc(struct mfc_dev *dev, + struct mfc_special_buf *special_buf) +{ + int ret = 0; + + /* control by DMA heap API */ + special_buf->dma_buf = create_dma_buf(dev, special_buf); + if (IS_ERR(special_buf->dma_buf)) { + mfc_dev_err("Failed to allocate buffer (err %ld)\n", + PTR_ERR(special_buf->dma_buf)); + return -EINVAL; + } + + /* control by DMA buf API */ + special_buf->attachment = dma_buf_attach(special_buf->dma_buf, + dev->device); + if (IS_ERR(special_buf->attachment)) { + mfc_dev_err("Failed to get dma_buf_attach (err %ld)\n", + PTR_ERR(special_buf->attachment)); + goto err_put_dma_buf; + } + + special_buf->sgt = dma_buf_map_attachment_unlocked(special_buf->attachment, + DMA_BIDIRECTIONAL); + if (IS_ERR(special_buf->sgt)) { + mfc_dev_err("Failed to get sgt (err %ld)\n", + PTR_ERR(special_buf->sgt)); + goto err_detach_dma_buf; + } + + special_buf->daddr = sg_dma_address(special_buf->sgt->sgl); + if (IS_ERR_VALUE(special_buf->daddr)) { + mfc_dev_err("Failed to get iova (err 0x%p)\n", + &special_buf->daddr); + goto err_unmap_attachment; + } + + special_buf->map_size = mfc_mem_get_sg_length(dev, special_buf->sgt); + if (!special_buf->map_size || special_buf->map_size < special_buf->size) { + mfc_dev_err("Failed to get iova map size (sg length: %zu / buf size: %zu)\n", + special_buf->map_size, special_buf->size); + goto err_unmap_attachment; + } + + if (special_buf->buftype == MFCBUF_NORMAL) { + ret = dma_buf_vmap_unlocked(special_buf->dma_buf, &special_buf->map); + if (ret) { + mfc_dev_err("Failed to get vaddr\n"); + goto err_unmap_attachment; + } + + if (!special_buf->map.vaddr) { + mfc_dev_err("[ERROR]: special_buf->vaddr = map.vaddr: %pa\n", + special_buf->vaddr); + goto err_unmap_attachment; + } + special_buf->vaddr = special_buf->map.vaddr; + } + + special_buf->paddr = page_to_phys(sg_page(special_buf->sgt->sgl)); + + return 0; +err_unmap_attachment: + if (special_buf->vaddr) { + dma_buf_vunmap_unlocked(special_buf->dma_buf, &special_buf->map); + special_buf->vaddr = NULL; + } + dma_buf_unmap_attachment_unlocked(special_buf->attachment, special_buf->sgt, + DMA_BIDIRECTIONAL); + special_buf->sgt = NULL; + special_buf->map_size = 0; + special_buf->daddr = 0; +err_detach_dma_buf: + dma_buf_detach(special_buf->dma_buf, special_buf->attachment); + special_buf->attachment = NULL; +err_put_dma_buf: + dma_buf_put(special_buf->dma_buf); + special_buf->dma_buf = NULL; + return -ENOMEM; +} + +static void mfc_mem_dma_heap_free(struct mfc_special_buf *special_buf) +{ + struct iosys_map map = IOSYS_MAP_INIT_VADDR(special_buf->vaddr); + + if (special_buf->vaddr) + dma_buf_vunmap_unlocked(special_buf->dma_buf, &map); + if (special_buf->sgt) + dma_buf_unmap_attachment_unlocked(special_buf->attachment, + special_buf->sgt, DMA_BIDIRECTIONAL); + if (special_buf->attachment) + dma_buf_detach(special_buf->dma_buf, special_buf->attachment); + if (special_buf->dma_buf) + dma_buf_put(special_buf->dma_buf); + + special_buf->dma_buf = NULL; + special_buf->attachment = NULL; + special_buf->sgt = NULL; + special_buf->daddr = 0; + special_buf->vaddr = NULL; + special_buf->map_size = 0; + special_buf->name[0] = 0; +} + +int mfc_mem_special_buf_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf) +{ + int ret; + + mfc_dev_debug(2, "[MEMINFO] REQUEST:%s buf\n", + special_buf->name); + + switch (special_buf->buftype) { + case MFCBUF_NORMAL_FW: + ret = mfc_mem_fw_alloc(dev, special_buf); + break; + case MFCBUF_NORMAL: + ret = mfc_mem_dma_heap_alloc(dev, special_buf); + break; + default: + mfc_dev_err("not supported mfc mem type: %d\n", special_buf->buftype); + return -EINVAL; + } + + mfc_dev_debug(2, "[MEMINFO] ALLOC: %s buf size: %zu, map size: %zu, daddr: 0x%08llx\n", + special_buf->name, + special_buf->size, special_buf->map_size, special_buf->daddr); + + if (ret) + mfc_dev_err("[MEMINFO] Allocating %s failed\n", + special_buf->name); + + return ret; +} + +void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *special_buf) +{ + mfc_dev_debug(2, "[MEMINFO] RELEASE:%s buf\n", + special_buf->name); + + switch (special_buf->buftype) { + case MFCBUF_NORMAL_FW: + dma_free_coherent(dev->device, special_buf->size, + special_buf->vaddr, special_buf->daddr); + mfc_mem_fw_free(special_buf); + break; + case MFCBUF_NORMAL: + mfc_mem_dma_heap_free(special_buf); + break; + default: + break; + } +} + +void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf) +{ + /* Project that do not support iova reservation */ + if (!dev->pdata->reserved_start) + return; + + if (!buf->iova) { + mfc_dev_debug(2, "[POOL] There is no reserved iova for %s\n", buf->name); + return; + } + +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + if (buf->map_size) + iommu_unmap(dev->domain, buf->daddr, buf->map_size); +#endif + + gen_pool_free(dev->iova_pool, buf->daddr, buf->map_size); + + mfc_dev_debug(2, "[POOL] FREE: %s iova: %#llx ++ %#zx, %zu/%zu (avail/total KB)\n", + buf->name, buf->daddr, buf->map_size, + gen_pool_avail(dev->iova_pool) / SZ_1K, + gen_pool_size(dev->iova_pool) / SZ_1K); + + buf->daddr = buf->iova; + buf->iova = 0; +} + +/* + * This iova is allocated for special FW only memory. + * These memories deliver to F/W without 4bit shift even if 36bit DMA is supported, + * because it is already less than 1GB(0x4000_0000) address. + * Therefore, it should be noted that the memory below should use + * MFC_CORE_READL(WRITEL) rather than MFC_CORE_DMA_READL(WRITEL). + * - MFC_REG_CONTEXT_MEM_ADDR, MFC0_REG_COMMON_CONTEXT_MEM_ADDR, MFC1_REG_COMMON_CONTEXT_MEM_ADDR + * - MFC_REG_DBG_BUFFER_ADDR + * - MFC_REG_D_METADATA_BUFFER_ADDR, MFC_REG_E_METADATA_BUFFER_ADDR + * - MFC_REG_SHARED_MEM_ADDR (not used) + */ +int mfc_iova_pool_alloc(struct mfc_dev *dev, struct mfc_special_buf *buf) +{ + size_t size; + + /* Project that do not support iova reservation */ + if (!dev->pdata->reserved_start) + return 0; + + if (!dev->iova_pool) { + mfc_dev_err("there is no iova pool\n"); + return -ENOMEM; + } + + buf->iova = buf->daddr; + buf->daddr = gen_pool_alloc(dev->iova_pool, buf->map_size); + if (buf->daddr == 0) { + buf->daddr = buf->iova; + buf->iova = 0; + mfc_dev_err("[POOL] failed alloc %s iova. %zu/%zu (avail/total KB)\n", + buf->name, + gen_pool_avail(dev->iova_pool) / SZ_1K, + gen_pool_size(dev->iova_pool) / SZ_1K); + return -ENOMEM; + } + + mfc_dev_debug(2, "[POOL] ALLOC: %s iova: %#llx ++ %#zx, %zu/%zu (avail/total KB)\n", + buf->name, buf->daddr, buf->map_size, + gen_pool_avail(dev->iova_pool) / SZ_1K, + gen_pool_size(dev->iova_pool) / SZ_1K); + + size = iommu_map_sg(dev->domain, buf->daddr, buf->sgt->sgl, + buf->sgt->orig_nents, IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + if (!size || size != buf->map_size) { + mfc_dev_err("[POOL] Failed to map %s iova %#llx (map size: %zu)\n", + buf->name, buf->daddr, size); + mfc_iova_pool_free(dev, buf); + return -ENOMEM; + } + + mfc_dev_debug(2, "[POOL] MAP: %s iova size: %zu(%#zx)\n", + buf->name, buf->map_size, buf->map_size); + + return 0; +} + +int mfc_iova_pool_init(struct mfc_dev *dev) +{ + struct device_node *node = dev->device->of_node; + dma_addr_t reserved_base; + const __be32 *prop; + size_t reserved_size; + int n_addr_cells = of_n_addr_cells(node); + int n_size_cells = of_n_size_cells(node); + int n_all_cells = n_addr_cells + n_size_cells; + int i, cnt, ret, found = 0; + char name[10]; + + snprintf(name, sizeof(name), "MFC"); + dev->iova_pool = devm_gen_pool_create(dev->device, PAGE_SHIFT, -1, name); + if (IS_ERR(dev->iova_pool)) { + mfc_dev_err("failed to create MFC IOVA gen pool\n"); + goto err_init; + } + + prop = of_get_property(node, "samsung,iommu-reserved-map", &cnt); + if (!prop) { + mfc_dev_err("No reserved F/W dma area\n"); + goto err_init; + } + + cnt /= sizeof(unsigned int); + if (cnt % n_all_cells != 0) { + mfc_dev_err("Invalid number(%d) of values\n", cnt); + goto err_init; + } + + for (i = 0; i < cnt; i += n_all_cells) { + reserved_base = of_read_number(prop + i, n_addr_cells); + reserved_size = of_read_number(prop + i + n_addr_cells, n_size_cells); + if (reserved_base == dev->pdata->reserved_start) { + found = 1; + break; + } + } + + if (!found) { + mfc_dev_err("failed to search for reserved address %#x\n", + dev->pdata->reserved_start); + goto err_init; + } + + ret = gen_pool_add(dev->iova_pool, reserved_base, reserved_size, -1); + if (ret) { + mfc_dev_err("failed to set address range of MFC IOVA pool (ret: %d)\n", ret); + goto err_init; + } + mfc_dev_info("[POOL] Add MFC iova ranges %#llx ++ %#zx\n", + reserved_base, reserved_size); + + return 0; + +err_init: + dev->iova_pool = NULL; + return -ENOMEM; +} + +int mfc_iommu_map_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf) +{ + struct mfc_dev *dev = core->dev; + struct device_node *node = core->device->of_node; + dma_addr_t reserved_base; + const __be32 *prop; + + prop = of_get_property(node, "samsung,iommu-reserved-map", NULL); + if (!prop) { + mfc_dev_err("No reserved F/W dma area\n"); + return -ENOENT; + } + + if (fw_buf->buftype == MFCBUF_NORMAL_FW) { + reserved_base = of_read_number(prop, of_n_addr_cells(node)); + mfc_core_info("[F/W] %s: reserved_base is %#llx\n", + fw_buf->name, reserved_base); + } else { + mfc_core_err("Wrong firmware buftype %d\n", fw_buf->buftype); + return -EINVAL; + } + + if (!reserved_base) { + mfc_core_err("There is no %s firmware reserved_base\n", + (fw_buf->buftype == MFCBUF_NORMAL_FW) ? "normal" : "drm"); + return -ENOMEM; + } + + fw_buf->map_size = iommu_map_sg(core->domain, reserved_base, + fw_buf->sgt->sgl, fw_buf->sgt->orig_nents, + IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + if (!fw_buf->map_size) { + mfc_core_err("Failed to map iova (err VA: %#llx, PA: %#llx)\n", + reserved_base, fw_buf->paddr); + return -ENOMEM; + } + + fw_buf->daddr = reserved_base; + mfc_core_debug(2, "[MEMINFO] FW mapped iova: %#llx (pa: %#llx)\n", + fw_buf->daddr, fw_buf->paddr); + + return 0; +} + +/* DMA memory related helper functions */ +static void mfc_memdev_release(struct device *dev) +{ + of_reserved_mem_device_release(dev); +} + +static struct device *mfc_alloc_memdev(struct device *dev, + const char *name, unsigned int idx) +{ + struct device *child; + int ret; + + child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL); + if (!child) + return NULL; + + device_initialize(child); + dev_set_name(child, "%s:%s", dev_name(dev), name); + child->parent = dev; + child->coherent_dma_mask = dev->coherent_dma_mask; + child->dma_mask = dev->dma_mask; + child->release = mfc_memdev_release; + child->dma_parms = devm_kzalloc(dev, sizeof(*child->dma_parms), + GFP_KERNEL); + if (!child->dma_parms) + goto err; + /* + * The memdevs are not proper OF platform devices, so in order for them + * to be treated as valid DMA masters we need a bit of a hack to force + * them to inherit the MFC node's DMA configuration. + */ + of_dma_configure(child, dev->of_node, true); + + if (!device_add(child)) { + ret = of_reserved_mem_device_init_by_idx(child, dev->of_node, + idx); + if (!ret) + return child; + device_del(child); + } +err: + put_device(child); + return NULL; +} + +int mfc_configure_dma_memory(struct mfc_dev *mfc_dev) +{ + struct device *dev = mfc_dev->device; + void *bank2_virt; + dma_addr_t bank2_dma_addr; + unsigned long align_size = BIT(17); // MFC_BASE_ALIGN_ORDER; + + /* + * Create and initialize virtual devices for accessing + * reserved memory regions. + */ + mfc_dev->mem_dev[BANK_L_CTX] = mfc_alloc_memdev(dev, "left", + BANK_L_CTX); + if (!mfc_dev->mem_dev[BANK_L_CTX]) + return -ENODEV; + + mfc_dev->mem_dev[BANK_R_CTX] = mfc_alloc_memdev(dev, "right", + BANK_R_CTX); + if (!mfc_dev->mem_dev[BANK_R_CTX]) { + device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); + return -ENODEV; + } + + /* Allocate memory for firmware and initialize both banks addresses */ + bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX], + align_size, &bank2_dma_addr, GFP_KERNEL); + if (!bank2_virt) { + // mfc_release_firmware(mfc_dev); + device_unregister(mfc_dev->mem_dev[BANK_R_CTX]); + device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); + return -ENOMEM; + } + + dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt, + bank2_dma_addr); + + dma_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX], DMA_BIT_MASK(32)); + dma_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX], DMA_BIT_MASK(32)); + + return 0; +} + +void mfc_unconfigure_dma_memory(struct mfc_dev *mfc_dev) +{ + device_unregister(mfc_dev->mem_dev[BANK_L_CTX]); + device_unregister(mfc_dev->mem_dev[BANK_R_CTX]); +} + +MODULE_IMPORT_NS("DMA_BUF"); diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h new file mode 100644 index 000000000000..7b37e5fedbf2 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_mem.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_MEM_H +#define __MFC_MEM_H __FILE__ + +#include <linux/dma-buf.h> +#include <linux/dma-direct.h> +#include <linux/of_reserved_mem.h> + +#include "mfc_common.h" + +/* Offset base used to differentiate between CAPTURE and OUTPUT + * while mmaping + */ +#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) + +struct dma_priv { + void *vaddr; + dma_addr_t dma_addr; + struct device *dev; + size_t size; +}; + +static inline dma_addr_t mfc_mem_get_daddr_vb(struct vb2_buffer *vb, unsigned int n) +{ + struct sg_table *sgt; + dma_addr_t addr = 0; + + sgt = vb2_dma_sg_plane_desc(vb, n); + addr = sg_dma_address(sgt->sgl); + WARN_ON((addr == 0) || IS_ERR_VALUE(addr)); + + return addr; +} + +static inline phys_addr_t mfc_mem_get_paddr_vb(struct vb2_buffer *vb) +{ + struct sg_table *sgt; + + sgt = vb2_dma_sg_plane_desc(vb, 0); + + return page_to_phys(sg_page(sgt->sgl)); +} + +static inline size_t mfc_mem_get_sg_length(struct mfc_dev *dev, struct sg_table *sgt) +{ + struct scatterlist *sg; + size_t size = 0; + int i; + + for_each_sg(sgt->sgl, sg, sgt->orig_nents, i) { + size += sg->length; + mfc_dev_debug(6, "[MEMINFO] [%d] sg length %u, sum %zu\n", + i, sg->length, size); + } + + return size; +} + +int mfc_mem_special_buf_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf); +void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *special_buf); + +void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf); +int mfc_iova_pool_alloc(struct mfc_dev *dev, struct mfc_special_buf *buf); +int mfc_iova_pool_init(struct mfc_dev *dev); + +int mfc_iommu_map_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf); + +int mfc_configure_dma_memory(struct mfc_dev *mfc_dev); +void mfc_unconfigure_dma_memory(struct mfc_dev *mfc_dev); +#endif /* __MFC_MEM_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h new file mode 100644 index 000000000000..39f20e5c8877 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * mfc_regs.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_REGS_H +#define __MFC_REGS_H __FILE__ + +#include "mfc_regs_mfc.h" +#include "mfc_data_struct.h" + +#define MFC_MIN_BITMASK 32 + +#define MFC_CORE_READL(offset) \ + readl(core->regs_base + (offset)) +#define MFC_CORE_WRITEL(data, offset) \ + writel((data), core->regs_base + (offset)) + +#define MFC_CORE_RAW_READL(offset) \ + __raw_readl(core->regs_base + (offset)) +#define MFC_CORE_RAW_WRITEL(data, offset) \ + __raw_writel((data), core->regs_base + (offset)) + +#define MFC_CORE_DMA_READL(offset) \ +({ \ + dma_addr_t data; \ + typeof(offset) off = offset; \ + if (core->dev->pdata->dma_bit_mask == MFC_MIN_BITMASK) \ + data = readl(core->regs_base + (off)); \ + else \ + data = (dma_addr_t)readl(core->regs_base + (off)) << 4; \ + data; \ +}) + +#define MFC_CORE_DMA_WRITEL(data, offset) \ +({ \ + typeof(offset) off = offset; \ + typeof(data) dat = data; \ + if (core->dev->pdata->dma_bit_mask == MFC_MIN_BITMASK) \ + writel((dat), core->regs_base + (off)); \ + else \ + writel((dat >> 4), core->regs_base + (off)); \ +}) + +#define MFC_MMU0_READL(offset) readl(core->sysmmu0_base + (offset)) +#define MFC_MMU1_READL(offset) readl(core->sysmmu1_base + (offset)) +#define mfc_get_mmu0_value(offset, shift, mask) ((MFC_MMU0_READL(offset) >> (shift)) & (mask)) +#define mfc_get_mmu1_value(offset, shift, mask) ((MFC_MMU1_READL(offset) >> (shift)) & (mask)) + +#define PMU_READL(offset) readl(core->pmu_base + (offset)) +#define PMU_WRITEL(data, offset) writel((data), core->pmu_base + (offset)) + +#endif /* __MFC_REGS_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h new file mode 100644 index 000000000000..5048bf6c1d78 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_sched.h File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_SCHED_H +#define __MFC_SCHED_H __FILE__ + +#include "mfc_common.h" + +extern struct mfc_sched_class mfc_sched_prio; + +static inline int mfc_get_prio(struct mfc_core *core, int rt, int prio) +{ + return (rt == MFC_NON_RT) ? (core->num_prio + prio) : prio; +} + +static inline void mfc_sched_init_core(struct mfc_core *core) +{ + core->sched = &mfc_sched_prio; + core->sched->create_work(core); + core->sched->init_work(core); +} +#endif /* __MFC_SCHED_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h new file mode 100644 index 000000000000..f965a2e440c0 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_utils.h + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_UTILS_H +#define __MFC_UTILS_H __FILE__ + +#include "mfc_common.h" + +static inline void mfc_core_clean_dev_int_flags(struct mfc_core *core) +{ + core->int_condition = 0; + core->int_reason = 0; + core->int_err = 0; +} + +static inline void mfc_clean_core_ctx_int_flags(struct mfc_core_ctx *core_ctx) +{ + core_ctx->int_condition = 0; + core_ctx->int_reason = 0; + core_ctx->int_err = 0; +} + +static inline void mfc_change_state(struct mfc_core_ctx *core_ctx, enum mfc_inst_state state) +{ + MFC_TRACE_CORE_CTX("** state : %d -> %d\n", core_ctx->state, state); + mfc_debug(3, "state %d -> %d\n", core_ctx->state, state); + core_ctx->state = state; +} + +static inline void mfc_change_op_mode(struct mfc_ctx *ctx, enum mfc_op_mode op_mode) +{ + struct mfc_dev *dev = ctx->dev; + + MFC_TRACE_RM("** op_mode : %d -> %d\n", ctx->op_mode, op_mode); + MFC_TRACE_CTX("** op_mode : %d -> %d\n", ctx->op_mode, op_mode); + mfc_ctx_debug(3, "op_mode %d -> %d\n", ctx->op_mode, op_mode); + ctx->op_mode = op_mode; +} + +static inline void mfc_core_change_state(struct mfc_core *core, enum mfc_core_state state) +{ + MFC_TRACE_CORE("** core state : %d\n", state); + core->state = state; +} + +static inline void mfc_core_change_fw_state(struct mfc_core *core, + enum mfc_fw_status state, int set) +{ + enum mfc_fw_status prev_stat; + + prev_stat = core->fw.status; + if (set) + core->fw.status |= state; + else + core->fw.status &= ~state; + MFC_TRACE_CORE("** normal FW status %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.status, set ? "set" : "clear", state); + mfc_core_debug(2, "[F/W] normal status: %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.status, set ? "set" : "clear", state); +} + +static inline enum mfc_node_type mfc_get_node_type(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct mfc_dev *dev; + enum mfc_node_type node_type; + + if (!vdev) { + mfc_pr_err("mfc failed to get video_device\n"); + return MFCNODE_INVALID; + } + dev = video_drvdata(file); + + mfc_dev_debug(2, "video_device index: %d\n", vdev->index); + + switch (vdev->index) { + case 0: + node_type = MFCNODE_DECODER; + break; + case 1: + node_type = MFCNODE_ENCODER; + break; + case 2: + node_type = MFCNODE_DECODER_DRM; + break; + case 3: + node_type = MFCNODE_ENCODER_DRM; + break; + case 4: + node_type = MFCNODE_ENCODER_OTF; + break; + case 5: + node_type = MFCNODE_ENCODER_OTF_DRM; + break; + default: + node_type = MFCNODE_INVALID; + break; + } + + return node_type; +} + +static inline int mfc_is_decoder_node(enum mfc_node_type node) +{ + if (node == MFCNODE_DECODER) + return 1; + + return 0; +} + +/* Meerkat interval */ +#define MEERKAT_TICK_INTERVAL 1000 +/* After how many executions meerkat should assume lock up */ +#define MEERKAT_TICK_CNT_TO_START_MEERKAT 10 + +/* MFC idle checker interval */ +#define MFCIDLE_TICK_INTERVAL 1500 + +void mfc_core_idle_checker(struct timer_list *t); + +static inline void mfc_core_idle_checker_start_tick(struct mfc_core *core) +{ + mod_timer(&core->mfc_idle_timer, jiffies + + msecs_to_jiffies(MFCIDLE_TICK_INTERVAL)); + + atomic_set(&core->hw_run_bits, 0); + atomic_set(&core->dev->queued_bits, 0); +} + +static inline void mfc_core_idle_update_hw_run(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + unsigned long flags; + int bits; + + spin_lock_irqsave(&core->dev->idle_bits_lock, flags); + + bits = atomic_read(&core->hw_run_bits); + atomic_set(&core->hw_run_bits, (bits | BIT(ctx->num))); + + spin_unlock_irqrestore(&core->dev->idle_bits_lock, flags); +} + +static inline void mfc_core_change_idle_mode(struct mfc_core *core, + enum mfc_idle_mode idle_mode) +{ + MFC_TRACE_CORE("** idle mode : %d\n", idle_mode); + core->idle_mode = idle_mode; + + if (core->idle_mode == MFC_IDLE_MODE_NONE) + mfc_core_idle_checker_start_tick(core); +} + +static inline void mfc_ctx_change_idle_mode(struct mfc_ctx *ctx, + enum mfc_idle_mode idle_mode) +{ + MFC_TRACE_CTX("**[c:%d] idle mode : %d\n", ctx->num, idle_mode); + ctx->idle_mode = idle_mode; +} +#endif /* __MFC_UTILS_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035540epcas5p356f8403ee4d973701a74cf96f6e9c19b@epcas5p3.samsung.com>]
* [PATCH 06/29] media: mfc: Add MFC core hardware register and debugfs APIs [not found] ` <CGME20250930035540epcas5p356f8403ee4d973701a74cf96f6e9c19b@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce mfc_core_hw_reg_api.h with inline helpers for interrupt handling, firmware status polling, pending checks, power control (MFC on/off), and RISC start/stop. Add mfc_debugfs.h exposing mfc_init_debugfs / mfc_deinit_debugfs for kernel debugfs integration. Provide mfc_core_reg_api.h containing version‑query macros and interrupt‑status getters, plus debug‑control stubs. Include necessary header dependencies. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/mfc_core_hw_reg_api.c | 122 +++++++++++ .../samsung/exynos-mfc/mfc_core_hw_reg_api.h | 144 +++++++++++++ .../platform/samsung/exynos-mfc/mfc_core_pm.c | 184 +++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_core_pm.h | 33 +++ .../samsung/exynos-mfc/mfc_core_reg_api.c | 44 ++++ .../samsung/exynos-mfc/mfc_core_reg_api.h | 46 +++++ .../samsung/exynos-mfc/mfc_core_sync.c | 190 ++++++++++++++++++ .../samsung/exynos-mfc/mfc_core_sync.h | 25 +++ .../platform/samsung/exynos-mfc/mfc_debugfs.c | 189 +++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_debugfs.h | 20 ++ 10 files changed, 997 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c new file mode 100644 index 000000000000..b4401ea2b476 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_hw_reg_api.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_hw_reg_api.h" + +/* Reset the device */ +void mfc_core_reg_clear(struct mfc_core *core) +{ + int i; + + /* Zero Initialization of MFC registers */ + MFC_CORE_WRITEL(0, MFC_REG_RISC2HOST_CMD); + MFC_CORE_WRITEL(0, MFC_REG_HOST2RISC_CMD); + MFC_CORE_WRITEL(0, MFC_REG_FW_VERSION); + + for (i = 0; i < MFC_REG_CLEAR_COUNT; i++) + MFC_CORE_WRITEL(0, MFC_REG_CLEAR_BEGIN + (i * 4)); +} + +void mfc_core_reset_mfc(struct mfc_core *core) +{ + mfc_core_debug_enter(); + + MFC_CORE_WRITEL(0x1FFF, MFC_REG_MFC_RESET); + MFC_CORE_WRITEL(0, MFC_REG_MFC_RESET); + + mfc_core_debug_leave(); +} + +void mfc_core_set_risc_base_addr(struct mfc_core *core) +{ + struct mfc_special_buf *fw_buf; + + fw_buf = &core->fw_buf; + + MFC_CORE_DMA_WRITEL(fw_buf->daddr, + MFC_REG_RISC_NONSECURE_BASE_ADDR); + + mfc_core_debug(2, "[MEMINFO][F/W] Base Address : %#x\n", + (u32)fw_buf->daddr); + MFC_TRACE_CORE("F/W Base Address : %#x\n", + (u32)fw_buf->daddr); +} + +void mfc_core_cmd_host2risc(struct mfc_core *core, int cmd) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[core->curr_core_ctx]; + struct mfc_ctx *ctx = core_ctx->ctx; + int ret = 0; + + mfc_debug(1, "[c:%d] Issue the command: %d%s\n", core->curr_core_ctx, + cmd, core->cache_flush_flag ? " with cache flush" : ""); + MFC_TRACE_CORE_CTX("%s %d, (dev:0x%lx, bits:%lx, owned:%d, wl:%d, trans:%d, opmode: %d)\n", + ">> CMD :", cmd, + core->hwlock.dev, core->hwlock.bits, + core->hwlock.owned_by_irq, core->hwlock.wl_count, + core->hwlock.transfer_owner, ctx->op_mode); + MFC_TRACE_LOG_CORE("C%d", cmd); + + if (core->cache_flush_flag) { + MFC_TRACE_CORE_CTX(">> CMD : 12 in FW\n"); + MFC_TRACE_LOG_CORE("C12FW"); + } + + /* Reset RISC2HOST command except nal q stop command */ + if (cmd != MFC_REG_H2R_CMD_STOP_QUEUE) + MFC_CORE_WRITEL(0x0, MFC_REG_RISC2HOST_CMD); + + if (cmd != MFC_REG_H2R_CMD_NAL_QUEUE && + cmd != MFC_REG_H2R_CMD_NAL_LL && + cmd != MFC_REG_H2R_CMD_STOP_QUEUE) { + /* TODO: change to core */ + if (cmd != MFC_REG_H2R_CMD_NAL_ABORT) { + /* Check the fw status */ + ret = mfc_core_wait_fw_status(core); + if (ret != 0) + mfc_err("Failed to wait firmware status\n"); + } + } + + if (core->dev->debugfs.dbg_enable && core->dbg_info_buf.dma_buf) { + /* For FW debugging */ + mfc_core_dbg_set_addr(core); + mfc_core_dbg_enable(core); + } + + core->last_cmd = cmd; + core->last_cmd_time = ktime_to_timespec64(ktime_get()); + + /* Record if the command incurs cache flush */ + core->last_cmd_has_cache_flush = + (cmd == MFC_REG_H2R_CMD_CACHE_FLUSH || core->cache_flush_flag) ? 1 : 0; + + if (core->cache_flush_flag) + cmd |= BIT(MFC_REG_H2R_CACHE_FLUSH_FLAG); + core->cache_flush_flag = 0; + + /* Issue the command */ + MFC_CORE_WRITEL(cmd, MFC_REG_HOST2RISC_CMD); + MFC_CORE_WRITEL(0x1, MFC_REG_HOST2RISC_INT); +} + +/* Check whether HW interrupt has occurred or not */ +int mfc_core_check_risc2host(struct mfc_core *core) +{ + if (mfc_core_get_pwr_ref_cnt(core) && mfc_core_get_clk_ref_cnt(core)) { + if (MFC_CORE_READL(MFC_REG_RISC2HOST_INT)) + return MFC_CORE_READL(MFC_REG_RISC2HOST_CMD); + else + return 0; + } + + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h new file mode 100644 index 000000000000..5a7bba8f54c3 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_hw_reg_api.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_HW_REG_API_H +#define __MFC_CORE_HW_REG_API_H __FILE__ + +#include "mfc_core_reg_api.h" + +#define mfc_core_get_int_reason() (MFC_CORE_READL(MFC_REG_RISC2HOST_CMD) \ + & MFC_REG_RISC2HOST_CMD_MASK) + +#define mfc_core_clear_int() \ + do { \ + MFC_CORE_WRITEL(0, MFC_REG_RISC2HOST_CMD); \ + MFC_CORE_WRITEL(0, MFC_REG_RISC2HOST_INT); \ + } while (0) + +#define mfc_core_clear_int_only() MFC_CORE_WRITEL(0, MFC_REG_RISC2HOST_INT) + +static inline int mfc_core_wait_fw_status(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + unsigned int status; + unsigned long timeout; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->wait_fw_status)) { + status = MFC_CORE_READL(MFC_REG_FIRMWARE_STATUS_INFO); + if (status & 0x1) + return 0; + + timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); + do { + if (time_after(jiffies, timeout)) { + mfc_core_err("Timeout while waiting MFC F/W done\n"); + return -EIO; + } + status = MFC_CORE_READL(MFC_REG_FIRMWARE_STATUS_INFO); + } while ((status & 0x1) == 0); + } + + return 0; +} + +static inline int mfc_core_wait_pending(struct mfc_core *core) +{ + unsigned int status; + unsigned long timeout; + + /* Check F/W wait status */ + timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); + do { + if (time_after(jiffies, timeout)) { + mfc_core_err("Timeout while waiting MFC F/W done\n"); + return -EIO; + } + status = MFC_CORE_READL(MFC_REG_FIRMWARE_STATUS_INFO); + } while ((status & 0x1) == 0); + + /* Check H/W pending status */ + timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); + do { + if (time_after(jiffies, timeout)) { + mfc_core_err("Timeout while pendng clear\n"); + mfc_core_err("MFC access pending R: %#x, BUS: %#x\n", + MFC_CORE_READL(MFC_REG_MFC_RPEND), + MFC_CORE_READL(MFC_REG_MFC_BUS_STATUS)); + return -EIO; + } + status = MFC_CORE_READL(MFC_REG_MFC_RPEND); + } while (status != 0); + + MFC_TRACE_CORE("** pending wait done\n"); + + return 0; +} + +static inline void mfc_core_mfc_off(struct mfc_core *core) +{ + if (core->dev->pdata->support_hwacg == MFC_HWACG_DRV_CTRL) { + mfc_core_debug(2, "MFC_OFF 1(off)\n"); + MFC_TRACE_CORE(">> MFC OFF 1(off)\n"); + MFC_CORE_WRITEL(0x1, MFC_REG_MFC_OFF); + } +} + +static inline void mfc_core_mfc_always_off(struct mfc_core *core) +{ + mfc_core_debug(2, "MFC_OFF 1(off)\n"); + MFC_TRACE_CORE(">> MFC OFF 1(off)\n"); + MFC_CORE_WRITEL(0x1, MFC_REG_MFC_OFF); +} + +static inline void mfc_core_mfc_on(struct mfc_core *core) +{ + MFC_CORE_WRITEL(0x0, MFC_REG_MFC_OFF); + mfc_core_debug(2, "MFC_OFF 0(on)\n"); + MFC_TRACE_CORE(">> MFC OFF 0(on)\n"); +} + +static inline void mfc_core_risc_on(struct mfc_core *core) +{ + mfc_core_clean_dev_int_flags(core); + mfc_core_mfc_on(core); + + MFC_CORE_WRITEL(0x1, MFC_REG_RISC_ON); + mfc_core_debug(1, "RISC_ON\n"); + MFC_TRACE_CORE(">> RISC ON\n"); +} + +static inline void mfc_core_risc_off(struct mfc_core *core) +{ + unsigned int status; + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); + /* Check pending status */ + do { + if (time_after(jiffies, timeout)) { + mfc_core_err("Timeout while pendng clear\n"); + mfc_core_err("MFC access pending state: %#x\n", status); + mfc_core_err("MFC access pending R: %#x, W: %#x\n", + MFC_CORE_READL(MFC_REG_MFC_RPEND), + MFC_CORE_READL(MFC_REG_MFC_WPEND)); + break; + } + status = MFC_CORE_READL(MFC_REG_MFC_BUS_STATUS); + } while (status != 0); + + MFC_CORE_WRITEL(0x0, MFC_REG_RISC_ON); +} + +void mfc_core_reg_clear(struct mfc_core *core); +void mfc_core_reset_mfc(struct mfc_core *core); +void mfc_core_set_risc_base_addr(struct mfc_core *core); +void mfc_core_cmd_host2risc(struct mfc_core *core, int cmd); +int mfc_core_check_risc2host(struct mfc_core *core); +#endif /* __MFC_CORE_HW_REG_API_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c new file mode 100644 index 000000000000..def7ac2a2007 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_pm.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/pm_runtime.h> + +#include "mfc_core_pm.h" +#include "mfc_core_sync.h" + +#include "mfc_core_hw_reg_api.h" + +void mfc_core_pm_init(struct mfc_core *core) +{ + spin_lock_init(&core->pm.clklock); + atomic_set(&core->pm.pwr_ref, 0); + atomic_set(&core->pm.protect_ref, 0); + atomic_set(&core->clk_ref, 0); + + core->pm.device = core->device; + core->pm.clock_on_steps = 0; + core->pm.clock_off_steps = 0; + pm_runtime_enable(core->pm.device); +} + +void mfc_core_pm_final(struct mfc_core *core) +{ + pm_runtime_disable(core->pm.device); +} + +int mfc_core_pm_clock_on(struct mfc_core *core, bool qos_update) +{ + int ret = 0; + int state; + + if (core->dev->pdata->support_hwacg == MFC_HWACG_HWFW_CTRL) + return ret; + + core->pm.clock_on_steps = 1; + state = mfc_core_get_clk_ref_cnt(core); + + core->pm.clock_on_steps |= BIT(1); + if (core->pm.base_type != MFCBUF_INVALID) { + /* + * There is no place to set core->pm.base_type, + * so it is always MFCBUF_INVALID now. + * When necessary later, you can set the bse_type. + */ + core->pm.clock_on_steps |= BIT(2); + ret = mfc_core_wait_pending(core); + if (ret != 0) { + mfc_core_err("pending wait failed (%d)\n", ret); + return ret; + } + core->pm.clock_on_steps |= BIT(3); + mfc_core_set_risc_base_addr(core); + } + + core->pm.clock_on_steps |= BIT(4); + if (!IS_ERR(core->pm.clock)) { + ret = clk_enable(core->pm.clock); + if (ret < 0) + mfc_core_err("clk_enable failed (%d)\n", ret); + } + + core->pm.clock_on_steps |= BIT(5); + state = atomic_inc_return(&core->clk_ref); + + if (!core->dev->multi_core_inst_bits) + mfc_core_mfc_on(core); + + mfc_core_debug(2, "clk_ref = %d\n", state); + MFC_TRACE_LOG_CORE("clk_ref = %d", state); + + return 0; +} + +void mfc_core_pm_clock_off(struct mfc_core *core, bool qos_update) +{ + int state; + + if (core->dev->pdata->support_hwacg == MFC_HWACG_HWFW_CTRL) + return; + + core->pm.clock_off_steps = 1; + state = atomic_dec_return(&core->clk_ref); + if (state < 0) { + mfc_core_info("MFC clock is already disabled (%d)\n", state); + atomic_set(&core->clk_ref, 0); + core->pm.clock_off_steps |= BIT(2); + MFC_TRACE_CORE("** clock_off already: ref state(%d)\n", + mfc_core_get_clk_ref_cnt(core)); + } else { + core->pm.clock_off_steps |= BIT(3); + if (!IS_ERR(core->pm.clock)) { + clk_disable(core->pm.clock); + core->pm.clock_off_steps |= BIT(4); + } + } + + state = mfc_core_get_clk_ref_cnt(core); + + if (!core->dev->multi_core_inst_bits && !state) + mfc_core_mfc_off(core); + + core->pm.clock_off_steps |= BIT(5); + + mfc_core_debug(2, "clk_ref = %d\n", state); + MFC_TRACE_LOG_CORE("clk_ref = %d", state); +} + +int mfc_core_pm_power_on(struct mfc_core *core) +{ + int ret; + + MFC_TRACE_CORE("++ Power on\n"); + ret = pm_runtime_get_sync(core->pm.device); + if (ret < 0) { + mfc_core_err("Failed to get power: ret(%d)\n", ret); + goto err_power_on; + } + +#if (IS_ENABLED(CONFIG_COMMON_CLK_SAMSUNG)) + core->pm.clock = clk_get(core->device, "aclk_mfc"); + if (IS_ERR(core->pm.clock)) { + mfc_core_err("failed to get parent clock: ret(%d)\n", ret); + } else { + ret = clk_prepare(core->pm.clock); + if (ret) { + mfc_core_err("clk_prepare() failed: ret(%d)\n", ret); + clk_put(core->pm.clock); + } + } +#endif + + atomic_inc(&core->pm.pwr_ref); + + MFC_TRACE_CORE("-- Power on: ret(%d)\n", ret); + MFC_TRACE_LOG_CORE("p+%d", mfc_core_get_pwr_ref_cnt(core)); + + return 0; + +err_power_on: + return ret; +} + +int mfc_core_pm_power_off(struct mfc_core *core) +{ + int state; + int ret; + + MFC_TRACE_CORE("++ Power off\n"); + + state = mfc_core_get_clk_ref_cnt(core); + if (state > 0 && core->dev->pdata->support_hwacg != MFC_HWACG_HWFW_CTRL) { + mfc_core_info("MFC clock is still enabled (%d)\n", state); + mfc_core_pm_clock_off(core, 0); + } + + if (!IS_ERR(core->pm.clock)) { + clk_unprepare(core->pm.clock); + clk_put(core->pm.clock); + } + mfc_core_mfc_always_off(core); + + ret = pm_runtime_put_sync(core->pm.device); + if (ret < 0) { + mfc_core_err("Failed to put power: ret(%d)\n", ret); + return ret; + } + + atomic_dec(&core->pm.pwr_ref); + + MFC_TRACE_CORE("-- Power off: ret(%d)\n", ret); + MFC_TRACE_LOG_CORE("p-%d", mfc_core_get_pwr_ref_cnt(core)); + + return ret; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h new file mode 100644 index 000000000000..f0b6159ce91a --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_pm.h File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_PM_H +#define __MFC_CORE_PM_H __FILE__ + +#include <linux/clk.h> + +#include "base/mfc_common.h" + +static inline void mfc_core_pm_clock_get(struct mfc_core *core) +{ + /* This should be called after clock was enabled by mfc_core_pm_clock_on() */ + if (core->continue_clock_on) + mfc_core_info("MFC frequency : %ld\n", clk_get_rate(core->pm.clock)); +} + +void mfc_core_pm_init(struct mfc_core *core); +void mfc_core_pm_final(struct mfc_core *core); +int mfc_core_pm_clock_on(struct mfc_core *core, bool qos_update); +void mfc_core_pm_clock_off(struct mfc_core *core, bool qos_update); +int mfc_core_pm_power_on(struct mfc_core *core); +int mfc_core_pm_power_off(struct mfc_core *core); + +#endif /* __MFC_CORE_PM_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c new file mode 100644 index 000000000000..ec6699dbd451 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_reg_api.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/delay.h> + +#include "mfc_core_reg_api.h" + +void mfc_core_dbg_enable(struct mfc_core *core) +{ + unsigned int reg; + + mfc_core_debug(2, "MFC debug info enable\n"); + reg = MFC_CORE_READL(MFC_REG_DBG_INFO_ENABLE); + reg |= BIT(MFC_REG_DBG_INFO_ENABLE_SHIFT); + MFC_CORE_WRITEL(reg, MFC_REG_DBG_INFO_ENABLE); +} + +void mfc_core_dbg_disable(struct mfc_core *core) +{ + unsigned int reg; + + mfc_core_debug(2, "MFC debug info disable\n"); + reg = MFC_CORE_READL(MFC_REG_DBG_INFO_ENABLE); + reg &= ~BIT(MFC_REG_DBG_INFO_ENABLE_SHIFT); + MFC_CORE_WRITEL(reg, MFC_REG_DBG_INFO_ENABLE); +} + +void mfc_core_dbg_set_addr(struct mfc_core *core) +{ + struct mfc_ctx_buf_size *buf_size = core->dev->variant->buf_size->ctx_buf; + + memset((void *)core->dbg_info_buf.vaddr, 0, buf_size->dbg_info_buf); + + MFC_CORE_WRITEL(core->dbg_info_buf.daddr, MFC_REG_DBG_BUFFER_ADDR); + MFC_CORE_WRITEL(buf_size->dbg_info_buf, MFC_REG_DBG_BUFFER_SIZE); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h new file mode 100644 index 000000000000..a23d25edce5d --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_reg_api.h File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_REG_API_H +#define __MFC_CORE_REG_API_H __FILE__ + +#include "base/mfc_regs.h" +#include "base/mfc_utils.h" + +/* version */ +#define mfc_core_get_fimv_info() ((MFC_CORE_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_INFO_SHFT) \ + & MFC_REG_FW_VER_INFO_MASK) +#define mfc_core_get_fw_ver_year() ((MFC_CORE_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_YEAR_SHFT) \ + & MFC_REG_FW_VER_YEAR_MASK) +#define mfc_core_get_fw_ver_month() ((MFC_CORE_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_MONTH_SHFT) \ + & MFC_REG_FW_VER_MONTH_MASK) +#define mfc_core_get_fw_ver_date() ((MFC_CORE_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_DATE_SHFT) \ + & MFC_REG_FW_VER_DATE_MASK) +#define mfc_core_get_fw_ver_all() ((MFC_CORE_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_ALL_SHFT) \ + & MFC_REG_FW_VER_ALL_MASK) +#define mfc_core_get_mfc_version() ((MFC_CORE_READL(MFC_REG_MFC_VERSION) \ + >> MFC_REG_MFC_VER_SHFT) \ + & MFC_REG_MFC_VER_MASK) + +/* kind of interrupt */ +#define mfc_core_get_int_err() MFC_CORE_READL(MFC_REG_ERROR_CODE) + +#define mfc_core_get_inst_no() MFC_CORE_READL(MFC_REG_RET_INSTANCE_ID) + +void mfc_core_dbg_enable(struct mfc_core *core); +void mfc_core_dbg_disable(struct mfc_core *core); +void mfc_core_dbg_set_addr(struct mfc_core *core); +#endif /* __MFC_CORE_REG_API_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c new file mode 100644 index 000000000000..de13cdb9c99a --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_sync.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_sync.h" + +#include "mfc_core_hw_reg_api.h" + +#define R2H_BIT(x) ({ \ + typeof(x) _x = (x); \ + (_x > 0) ? BIT(_x - 1) : 0; \ +}) + +static inline unsigned int __mfc_r2h_bit_mask(int cmd) +{ + unsigned int mask = R2H_BIT(cmd); + + if (cmd == MFC_REG_R2H_CMD_FRAME_DONE_RET) + mask |= (R2H_BIT(MFC_REG_R2H_CMD_FIELD_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_COMPLETE_SEQ_RET) | + R2H_BIT(MFC_REG_R2H_CMD_SLICE_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_INIT_BUFFERS_RET) | + R2H_BIT(MFC_REG_R2H_CMD_NAL_ABORT_RET)); + /* FIXME: Temporal mask for S3D SEI processing */ + else if (cmd == MFC_REG_R2H_CMD_INIT_BUFFERS_RET) + mask |= (R2H_BIT(MFC_REG_R2H_CMD_FIELD_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_SLICE_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_FRAME_DONE_RET)); + + return (mask |= R2H_BIT(MFC_REG_R2H_CMD_ERR_RET)); +} + +void mfc_get_corelock_ctx(struct mfc_ctx *ctx) +{ + unsigned long flags; + + spin_lock_irqsave(&ctx->corelock.lock, flags); + mfc_ctx_debug(3, "[CORELOCK] get_corelock: cnt %d\n", + ctx->corelock.cnt); + + ctx->corelock.cnt++; + + spin_unlock_irqrestore(&ctx->corelock.lock, flags); +} + +void mfc_release_corelock_ctx(struct mfc_ctx *ctx) +{ + unsigned long flags; + + spin_lock_irqsave(&ctx->corelock.lock, flags); + + ctx->corelock.cnt--; + if (ctx->corelock.cnt == 0) + wake_up(&ctx->corelock.wq); + else if (ctx->corelock.cnt < 0) + mfc_ctx_err("[CORELOCK] wrong corelock cnt %d\n", ctx->corelock.cnt); + + mfc_ctx_debug(3, "[CORELOCK] release_corelock: cnt %d\n", + ctx->corelock.cnt); + spin_unlock_irqrestore(&ctx->corelock.lock, flags); +} + +#define wait_condition(x, c) ({ \ + typeof(x) __x = (x); \ + __x->int_condition && (R2H_BIT(__x->int_reason) & __mfc_r2h_bit_mask(c)); \ +}) + +#define is_err_cond(x) ({ \ + typeof(x) __x = (x); \ + __x->int_condition && (__x->int_reason == MFC_REG_R2H_CMD_ERR_RET); \ +}) + +/* + * Return value description + * 0: waked up before timeout + * 1: failed to get the response for the command before timeout + */ +int mfc_wait_for_done_core(struct mfc_core *core, int command) +{ + int ret; + + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't run HW. It's Error state\n"); + return 0; + } + + ret = wait_event_timeout(core->cmd_wq, + wait_condition(core, command), + msecs_to_jiffies(MFC_INT_TIMEOUT)); + if (ret == 0) { + mfc_core_err("Interrupt (core->int_reason:%d, command:%d) timed out\n", + core->int_reason, command); + if (mfc_core_check_risc2host(core)) { + ret = wait_event_timeout(core->cmd_wq, + wait_condition(core, command), + msecs_to_jiffies(MFC_INT_TIMEOUT * + MFC_INT_TIMEOUT_CNT)); + if (ret == 0) { + mfc_core_err("Timeout: MFC driver waited for upward of %dmsec\n", + 3 * MFC_INT_TIMEOUT); + } else { + goto wait_done; + } + } + return 1; + } + +wait_done: + if (is_err_cond(core)) { + mfc_core_err("Finished (core->int_reason:%d, command: %d)\n", + core->int_reason, command); + mfc_core_err("But error (core->int_err:%d)\n", core->int_err); + return -1; + } + + mfc_core_debug(2, "Finished waiting (core->int_reason:%d, command: %d)\n", + core->int_reason, command); + return 0; +} + +/* + * Return value description + * 0: waked up before timeout + * 1: failed to get the response for the command before timeout + * -1: got the error response for the command before timeout + */ +int mfc_wait_for_done_core_ctx(struct mfc_core_ctx *core_ctx, int command) +{ + struct mfc_core *core = core_ctx->core; + int ret; + unsigned int timeout = MFC_INT_TIMEOUT; + + if (core->state == MFCCORE_ERROR) { + mfc_info("[MSR] Couldn't run HW. It's Error state\n"); + return 0; + } + + if (command == MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET) + timeout = MFC_INT_SHORT_TIMEOUT; + + ret = wait_event_timeout(core_ctx->cmd_wq, + wait_condition(core_ctx, command), + msecs_to_jiffies(timeout)); + if (ret == 0) { + mfc_err("Interrupt (core_ctx->int_reason:%d, command:%d) timed out\n", + core_ctx->int_reason, command); + if (mfc_core_check_risc2host(core)) { + ret = wait_event_timeout(core_ctx->cmd_wq, + wait_condition(core_ctx, command), + msecs_to_jiffies + (MFC_INT_TIMEOUT * MFC_INT_TIMEOUT_CNT)); + if (ret == 0) { + mfc_err("Timeout: MFC driver waited for upward of %dmsec\n", + 3 * MFC_INT_TIMEOUT); + } else { + goto wait_done; + } + } + return 1; + } + +wait_done: + if (is_err_cond(core_ctx)) { + mfc_err("Finished (core_ctx->int_reason:%d, command: %d)\n", + core_ctx->int_reason, command); + mfc_err("But error (core_ctx->int_err:%d)\n", core_ctx->int_err); + return -1; + } + + mfc_debug(2, "Finished waiting (core_ctx->int_reason:%d, command: %d)\n", + core_ctx->int_reason, command); + return 0; +} + +/* Wake up device wait_queue */ +void mfc_wake_up_core(struct mfc_core *core, unsigned int reason, + unsigned int err) +{ + core->int_condition = 1; + core->int_reason = reason; + core->int_err = err; + wake_up(&core->cmd_wq); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h new file mode 100644 index 000000000000..2c19819048de --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_sync.h File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_SYNC_H +#define __MFC_CORE_SYNC_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_get_corelock_ctx(struct mfc_ctx *ctx); +void mfc_release_corelock_ctx(struct mfc_ctx *ctx); + +int mfc_wait_for_done_core(struct mfc_core *core, int command); +int mfc_wait_for_done_core_ctx(struct mfc_core_ctx *core_ctx, int command); +void mfc_wake_up_core(struct mfc_core *core, unsigned int reason, + unsigned int err); +int mfc_core_get_new_ctx(struct mfc_core *core); +#endif /* __MFC_CORE_SYNC_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c new file mode 100644 index 000000000000..5baa76a6b405 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_debugfs.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +#include "mfc_debugfs.h" + +static int __mfc_info_show(struct seq_file *s, void *unused) +{ + struct mfc_dev *dev = s->private; + struct mfc_core *core = NULL; + struct mfc_core_ctx *core_ctx = NULL; + int i, j; + + seq_puts(s, ">>> MFC common device information\n"); + seq_printf(s, " [DEBUG MODE] dt: %s sysfs: %s\n", + dev->pdata->debug_mode ? "enabled" : "disabled", + dev->debugfs.debug_mode_en ? "enabled" : "disabled"); + + seq_printf(s, " [LOWMEM] is_low_mem: %d\n", IS_LOW_MEM); + + for (j = 0; j < dev->num_core; j++) { + core = dev->core[j]; + if (!core) { + mfc_dev_debug(2, "There is no core[%d]\n", j); + continue; + } + seq_printf(s, ">>> MFC core-%d device information\n", j); + seq_printf(s, " [VERSION] H/W: v%x, F/W: %06x(%c, normal: %#x), DRV: %d\n", + core->core_pdata->ip_ver, core->fw.date, core->fw.fimv_info, + core->fw.status, MFC_DRIVER_INFO); + seq_printf(s, " [PM] power: %d, clock: %d, clk_get %s, QoS level: %d\n", + mfc_core_get_pwr_ref_cnt(core), + mfc_core_get_clk_ref_cnt(core), + IS_ERR(core->pm.clock) ? "failed" : "succeeded", + atomic_read(&core->qos_req_cur) - 1); + seq_printf(s, " [CTX] num_inst: %d, curr_ctx: %d\n", + core->num_inst, + core->curr_core_ctx); + seq_printf(s, " [HWLOCK] bits: %#lx, dev: %#lx, owned_by_irq = %d, wl_count = %d\n", + core->hwlock.bits, core->hwlock.dev, + core->hwlock.owned_by_irq, + core->hwlock.wl_count); + seq_printf(s, " >>> MFC core-%d instance information\n", j); + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + core_ctx = core->core_ctx[i]; + if (core_ctx) { + seq_printf(s, " [CORECTX:%d] state: %d\n", + i, core_ctx->state); + } + } + } + + return 0; +} + +static int __mfc_debug_info_show(struct seq_file *s, void *unused) +{ + seq_puts(s, ">> MFC debug information\n"); + + seq_puts(s, "-----SFR dump options (bit setting)\n"); + seq_puts(s, "ex) echo 0xff > /d/mfc/sfr_dump (all dump mode)\n"); + seq_puts(s, "1 BIT(0): dec SEQ_START\n"); + seq_puts(s, "2 BIT(1): dec INIT_BUFS\n"); + seq_puts(s, "4 BIT(2): dec first NAL_START\n"); + seq_puts(s, "8 BIT(3): enc SEQ_START\n"); + seq_puts(s, "16 BIT(4): enc INIT_BUFS\n"); + seq_puts(s, "32 BIT(5): enc first NAL_START\n"); + seq_puts(s, "64 BIT(6): ERR interrupt\n"); + seq_puts(s, "128 BIT(7): WARN interrupt\n"); + seq_puts(s, "256 BIT(8): dec NAL_START\n"); + seq_puts(s, "512 BIT(9): dec FRAME_DONE\n"); + seq_puts(s, "1024 BIT(10): enc NAL_START\n"); + seq_puts(s, "2048 BIT(11): enc FRAME_DONE\n"); + seq_puts(s, "0x1000 BIT(12): MOVE_INSTANCE_RET\n"); + seq_puts(s, "0x2000 BIT(13): Unknown unterrupt\n"); + seq_puts(s, "0x8000 BIT(15): dec SEQ_DONE\n"); + seq_puts(s, "0x10000 BIT(16): dec INIT_BUF_DONE\n"); + seq_puts(s, "0x20000 BIT(17): dec first FRAME_DONE\n"); + seq_puts(s, "0x40000 BIT(18): enc SEQ_DONE\n"); + seq_puts(s, "0x80000 BIT(19): enc INIT_BUF_DONE\n"); + seq_puts(s, "0x100000 BIT(20): enc first FRAME_DONE\n"); + seq_puts(s, "0x20000000 BIT(29): Dump decoder CRC\n"); + seq_puts(s, "0x40000000 BIT(30): Dump firmware\n"); + seq_puts(s, "0x80000000 BIT(31): Dump all info\n"); + + seq_puts(s, "-----Performance boost options (bit setting)\n"); + seq_puts(s, "1 BIT(0): DVFS (INT/MFC/MIF)\n"); + seq_puts(s, "2 BIT(1): MO value\n"); + seq_puts(s, "4 BIT(2): CPU frequency\n"); + + seq_puts(s, "-----Feature options (bit setting)\n"); + seq_puts(s, "ex) echo 1 > /d/mfc/feture_option\n"); + seq_puts(s, "1 BIT(0): recon SBWC disable\n"); + seq_puts(s, "2 BIT(1): decoding order\n"); + seq_puts(s, "4 BIT(2): meerkat disable\n"); + seq_puts(s, "8 BIT(3): OTF path test enable\n"); + seq_puts(s, "16 BIT(4): multi core disable\n"); + seq_puts(s, "32 BIT(5): force multi core enable\n"); + seq_puts(s, "64 BIT(6): black bar enable\n"); + seq_puts(s, "128 BIT(7): when dec and enc, SBWC enable\n"); + seq_puts(s, "256 BIT(8): sync minlock with clock disable\n"); + seq_puts(s, "512 BIT(9): dynamic weight disable (use fixed weight)\n"); + seq_puts(s, "1024 BIT(10): when high fps, SBWC enable\n"); + seq_puts(s, "2048 BIT(11): film grain disable\n"); + seq_puts(s, "0x4000 BIT(14): enable MSR mode once\n"); + + seq_puts(s, "-----Logging options (bit setting)\n"); + seq_puts(s, "ex) echo 7 > /d/mfc/logging_option (all logging option)\n"); + seq_puts(s, "1 BIT(0): kernel printk\n"); + seq_puts(s, "2 BIT(1): memlog printf\n"); + seq_puts(s, "4 BIT(2): memlog sfr dump\n"); + + seq_puts(s, "-----Scheduler type\n"); + seq_puts(s, "ex) echo 1 > /d/mfc/sched_type\n"); + seq_puts(s, "1 BIT(0): Round-robin scheduler\n"); + seq_puts(s, "2 BIT(1): PBS (Priority Based Scheduler)\n"); + + return 0; +} + +static int __mfc_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, __mfc_info_show, inode->i_private); +} + +static int __mfc_debug_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, __mfc_debug_info_show, inode->i_private); +} + +static const struct file_operations mfc_info_fops = { + .open = __mfc_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations debug_info_fops = { + .open = __mfc_debug_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void mfc_init_debugfs(struct mfc_dev *dev) +{ + struct mfc_debugfs *debugfs = &dev->debugfs; + + debugfs->root = debugfs_create_dir("mfc", NULL); + if (!debugfs->root) { + mfc_dev_err("debugfs: failed to create root directory\n"); + return; + } + + dev->debugfs.logging_option = MFC_DEFAULT_LOGGING_OPTION; + + debugfs_create_file("mfc_info", 0444, debugfs->root, dev, &mfc_info_fops); + debugfs_create_file("debug_info", 0444, debugfs->root, dev, &debug_info_fops); + + debugfs_create_u32("debug", 0644, debugfs->root, &dev->debugfs.debug_level); + debugfs_create_u32("debug_ts", 0644, debugfs->root, &dev->debugfs.debug_ts); + debugfs_create_u32("debug_mode_en", 0644, debugfs->root, &dev->debugfs.debug_mode_en); + debugfs_create_u32("dbg_enable", 0644, debugfs->root, &dev->debugfs.dbg_enable); + + debugfs_create_u32("sfr_dump", 0644, debugfs->root, &dev->debugfs.sfr_dump); + + debugfs_create_u32("feature_option", 0644, debugfs->root, &dev->debugfs.feature_option); + debugfs_create_u32("logging_option", 0644, debugfs->root, &dev->debugfs.logging_option); + debugfs_create_u32("sched_perf_disable", 0644, + debugfs->root, &dev->debugfs.sched_perf_disable); + debugfs_create_u32("sched_type", 0644, debugfs->root, &dev->debugfs.sched_type); +} + +void mfc_deinit_debugfs(struct mfc_dev *dev) +{ + struct mfc_debugfs *debugfs = &dev->debugfs; + + debugfs_remove_recursive(debugfs->root); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h new file mode 100644 index 000000000000..bbefd046587b --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_debugfs.h File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_DEBUGFS_H +#define __MFC_DEBUGFS_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_init_debugfs(struct mfc_dev *dev); +void mfc_deinit_debugfs(struct mfc_dev *dev); + +#endif /* __MFC_DEBUGFS_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035547epcas5p11f579ca8f8a83767cbb2b632fa9cd6f7@epcas5p1.samsung.com>]
* [PATCH 07/29] media: mfc: Add MFC core command, hwlock, ISR and run functionalities [not found] ` <CGME20250930035547epcas5p11f579ca8f8a83767cbb2b632fa9cd6f7@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce functions that define the core command interface, hardware‑lock management, interrupt handling, and run‑time control for the MFC driver. mfc_core_cmd.h API for core initialization, power management, instance lifecycle (open/close/abort) and cache flushing. mfc_core_hwlock.h APIs for initializing, acquiring and releasing hardware locks for both device and context structures. mfc_core_isr.h ISR prototypes for top‑half and threaded interrupt handling. mfc_core_run.h Functions for cache flush, hardware initialization, de‑initialization, and power state transitions (sleep/wakeup). All files reference the common core structures via base/mfc_common.h. This patch prepares the interface layer for upcoming implementation changes in the MFC driver. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/mfc_core_cmd.c | 158 ++++++++ .../samsung/exynos-mfc/mfc_core_cmd.h | 26 ++ .../samsung/exynos-mfc/mfc_core_hwlock.c | 336 ++++++++++++++++++ .../samsung/exynos-mfc/mfc_core_hwlock.h | 72 ++++ .../samsung/exynos-mfc/mfc_core_intlock.c | 98 +++++ .../samsung/exynos-mfc/mfc_core_intlock.h | 20 ++ .../samsung/exynos-mfc/mfc_core_isr.c | 124 +++++++ .../samsung/exynos-mfc/mfc_core_isr.h | 22 ++ .../samsung/exynos-mfc/mfc_core_run.c | 265 ++++++++++++++ .../samsung/exynos-mfc/mfc_core_run.h | 26 ++ 10 files changed, 1147 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c new file mode 100644 index 000000000000..5be9fd086a93 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_cmd.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_cmd.h" +#include "mfc_core_intlock.h" + +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" + +void mfc_core_cmd_sys_init(struct mfc_core *core, + enum mfc_buf_usage_type buf_type) +{ + struct mfc_dev *dev = core->dev; + struct mfc_ctx_buf_size *buf_size; + struct mfc_special_buf *ctx_buf; + + mfc_core_debug_enter(); + + mfc_core_clean_dev_int_flags(core); + + buf_size = dev->variant->buf_size->ctx_buf; + ctx_buf = &core->common_ctx_buf; + MFC_CORE_WRITEL(ctx_buf->daddr, MFC_REG_CONTEXT_MEM_ADDR); + MFC_CORE_WRITEL(buf_size->dev_ctx, MFC_REG_CONTEXT_MEM_SIZE); + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_SYS_INIT); + + mfc_core_debug_leave(); +} + +void mfc_core_cmd_sleep(struct mfc_core *core) +{ + mfc_core_debug_enter(); + + mfc_core_clean_dev_int_flags(core); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_SLEEP); + + mfc_core_debug_leave(); +} + +void mfc_core_cmd_wakeup(struct mfc_core *core) +{ + mfc_core_debug_enter(); + + mfc_core_clean_dev_int_flags(core); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_WAKEUP); + + mfc_core_debug_leave(); +} + +/* Open a new instance and get its number */ +void mfc_core_cmd_open_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + unsigned int reg; + + mfc_debug_enter(); + + /* Preparing decoding - getting instance number */ + mfc_debug(2, "Getting instance number\n"); + mfc_clean_core_ctx_int_flags(core_ctx); + + reg = MFC_CORE_READL(MFC_REG_CODEC_CONTROL); + /* Clear OTF_CONTROL[2:1] & OTF_DEBUG[3] */ + reg &= ~(0x7 << 1); + + MFC_CORE_WRITEL(reg, MFC_REG_CODEC_CONTROL); + + mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode); + reg = ctx->codec_mode & MFC_REG_CODEC_TYPE_MASK; + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->mem_clear)) { + reg |= BIT(MFC_REG_CLEAR_CTX_MEM_SHIFT); + mfc_debug(2, "Enable to clear context memory: %#x\n", reg); + } + MFC_CORE_WRITEL(reg, MFC_REG_CODEC_TYPE); + + MFC_CORE_WRITEL(core_ctx->instance_ctx_buf.daddr, MFC_REG_CONTEXT_MEM_ADDR); + MFC_CORE_WRITEL(core_ctx->instance_ctx_buf.size, MFC_REG_CONTEXT_MEM_SIZE); + + if (dev->debugfs.feature_option & MFC_OPTION_SET_MULTI_CORE_FORCE) { + reg = MFC_CORE_READL(MFC_REG_DBG_INFO_ENABLE); + reg |= BIT(MFC_REG_DBG_INFO_TWO_MFC_FORCING_SHIFT); + MFC_CORE_WRITEL(reg, MFC_REG_DBG_INFO_ENABLE); + mfc_info("[2CORE] Forcely enable multi core mode %#x\n", + MFC_CORE_READL(MFC_REG_DBG_INFO_ENABLE)); + } + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_OPEN_INSTANCE); + + mfc_debug_leave(); +} + +/* Close instance */ +int mfc_core_cmd_close_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + mfc_debug_enter(); + + /* Closing decoding instance */ + mfc_debug(2, "Returning instance number\n"); + mfc_clean_core_ctx_int_flags(core_ctx); + if (core_ctx->state == MFCINST_FREE) { + mfc_err("ctx already free status\n"); + return -EINVAL; + } + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_CLOSE_INSTANCE); + + mfc_debug_leave(); + + return 0; +} + +void mfc_core_cmd_abort_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + mfc_clean_core_ctx_int_flags(core_ctx); + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_NAL_ABORT); +} + +void mfc_core_cmd_cache_flush(struct mfc_core *core) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[core->curr_core_ctx]; + struct mfc_ctx *ctx = core_ctx->ctx; + u32 reg = 0; + + mutex_lock(&ctx->op_mode_mutex); + + reg = MFC_CORE_READL(MFC_REG_D_NAL_START_OPTIONS); + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + if (IS_MULTI_MODE(ctx) || ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2) + reg |= BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + else + reg |= (0 << MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + MFC_CORE_WRITEL(reg, MFC_REG_D_NAL_START_OPTIONS); + mfc_debug(3, "NAL_START_OPTIONS: %#x, op_mode: %d\n", reg, ctx->op_mode); + mutex_unlock(&ctx->op_mode_mutex); + + mfc_core_clean_dev_int_flags(core); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_CACHE_FLUSH); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h new file mode 100644 index 000000000000..86b82d63f3b5 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_cmd.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_CMD_H +#define __MFC_CORE_CMD_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_core_cmd_sys_init(struct mfc_core *core, + enum mfc_buf_usage_type buf_type); +void mfc_core_cmd_sleep(struct mfc_core *core); +void mfc_core_cmd_wakeup(struct mfc_core *core); + +void mfc_core_cmd_open_inst(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_cmd_close_inst(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_cmd_abort_inst(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_cmd_cache_flush(struct mfc_core *core); +#endif /* __MFC_CORE_CMD_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c new file mode 100644 index 000000000000..4de836543e82 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_hwlock.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_rm.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_run.h" +#include "mfc_core_pm.h" +#include "mfc_core_sync.h" + +#include "mfc_core_cmd.h" +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_utils.h" +#include "base/mfc_sched.h" + +static inline void __mfc_print_hwlock(struct mfc_core *core) +{ + mfc_core_debug(3, "%s%lx, %sx%lx, %s %d, %s %d, %s %d\n", + "hwlock.dev = 0x", core->hwlock.dev, + "bits = 0x", core->hwlock.bits, + "owned_by_irq =", core->hwlock.owned_by_irq, + "wl_count =", core->hwlock.wl_count, + "transfer_owner =", core->hwlock.transfer_owner); +} + +void mfc_core_init_hwlock(struct mfc_core *core) +{ + unsigned long flags; + + spin_lock_init(&core->hwlock.lock); + spin_lock_irqsave(&core->hwlock.lock, flags); + + INIT_LIST_HEAD(&core->hwlock.waiting_list); + core->hwlock.wl_count = 0; + core->hwlock.bits = 0; + core->hwlock.dev = 0; + core->hwlock.owned_by_irq = 0; + core->hwlock.transfer_owner = 0; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); +} + +static void __mfc_remove_listable_wq_core(struct mfc_core *core) +{ + struct mfc_listable_wq *listable_wq; + unsigned long flags; + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + list_for_each_entry(listable_wq, &core->hwlock.waiting_list, list) { + if (!listable_wq->core) + continue; + + mfc_core_debug(2, "Found dev and will delete it!\n"); + + list_del(&listable_wq->list); + core->hwlock.wl_count--; + + break; + } + + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); +} + +static void __mfc_remove_listable_wq_ctx(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_listable_wq *listable_wq; + unsigned long flags; + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + list_for_each_entry(listable_wq, &core->hwlock.waiting_list, list) { + if (!listable_wq->core_ctx) + continue; + + if (listable_wq->core_ctx->num == core_ctx->num) { + mfc_debug(2, "Found ctx and will delete it (%d)!\n", core_ctx->num); + + list_del(&listable_wq->list); + core->hwlock.wl_count--; + break; + } + } + + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); +} + +/* + * Return value description + * 0: succeeded to get hwlock + * -EIO: failed to get hwlock (time out) + */ +int mfc_core_get_hwlock_dev(struct mfc_core *core) +{ + int ret = 0; + unsigned long flags; + + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't lock HW. It's Error state\n"); + return 0; + } + + if (core->shutdown) { + mfc_core_info("Couldn't lock HW. Shutdown was called\n"); + return -EINVAL; + } + + mutex_lock(&core->hwlock_wq.wait_mutex); + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + if (core->hwlock.bits != 0 || core->hwlock.dev != 0) { + list_add_tail(&core->hwlock_wq.list, &core->hwlock.waiting_list); + core->hwlock.wl_count++; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + mfc_core_debug(2, "Waiting for hwlock to be released\n"); + + ret = wait_event_timeout + (core->hwlock_wq.wait_queue, + (core->hwlock.transfer_owner == 1 && + (core->hwlock.dev == 1)), + msecs_to_jiffies(MFC_HWLOCK_TIMEOUT)); + + core->hwlock.transfer_owner = 0; + __mfc_remove_listable_wq_core(core); + if (!ret) { + mfc_core_err("Woken up but timed out\n"); + __mfc_print_hwlock(core); + mutex_unlock(&core->hwlock_wq.wait_mutex); + return -EIO; + } + mfc_core_debug(2, "Woken up and got hwlock\n"); + __mfc_print_hwlock(core); + mutex_unlock(&core->hwlock_wq.wait_mutex); + } else { + core->hwlock.bits = 0; + core->hwlock.dev = 1; + core->hwlock.owned_by_irq = 0; + + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); + mutex_unlock(&core->hwlock_wq.wait_mutex); + } + + return 0; +} + +/* + * Return value description + * 0: succeeded to get hwlock + * -EIO: failed to get hwlock (time out) + */ +int mfc_core_get_hwlock_ctx(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + int ret = 0; + unsigned long flags; + + if (core->state == MFCCORE_ERROR) { + mfc_info("[MSR] Couldn't lock HW. It's Error state\n"); + return 0; + } + + if (core->shutdown) { + mfc_info("Couldn't lock HW. Shutdown was called\n"); + return -EINVAL; + } + + mutex_lock(&core_ctx->hwlock_wq.wait_mutex); + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + if (core->hwlock.bits != 0 || core->hwlock.dev != 0) { + list_add_tail(&core_ctx->hwlock_wq.list, &core->hwlock.waiting_list); + core->hwlock.wl_count++; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + mfc_debug(2, "core_ctx[%d] Waiting for hwlock to be released\n", + core_ctx->num); + + ret = wait_event_timeout + (core_ctx->hwlock_wq.wait_queue, + (core->hwlock.transfer_owner == 1 && + test_bit(core_ctx->num, &core->hwlock.bits)), + msecs_to_jiffies(MFC_HWLOCK_TIMEOUT)); + + core->hwlock.transfer_owner = 0; + __mfc_remove_listable_wq_ctx(core_ctx); + if (!ret) { + mfc_err("Woken up but timed out\n"); + __mfc_print_hwlock(core); + mutex_unlock(&core_ctx->hwlock_wq.wait_mutex); + return -EIO; + } + mfc_debug(2, "Woken up and got hwlock\n"); + __mfc_print_hwlock(core); + mutex_unlock(&core_ctx->hwlock_wq.wait_mutex); + } else { + core->hwlock.bits = 0; + core->hwlock.dev = 0; + set_bit(core_ctx->num, &core->hwlock.bits); + core->hwlock.owned_by_irq = 0; + + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); + mutex_unlock(&core_ctx->hwlock_wq.wait_mutex); + } + return 0; +} + +static void __mfc_release_hwlock(struct mfc_core *core) +{ + struct mfc_listable_wq *listable_wq; + + if (core->state == MFCCORE_ERROR) { + mfc_core_debug(2, "[MSR] Couldn't wakeup module. It's Error state\n"); + } else if (core->shutdown) { + mfc_core_debug(2, "Couldn't wakeup module. Shutdown was called\n"); + } else if (list_empty(&core->hwlock.waiting_list)) { + mfc_core_debug(2, "No waiting module\n"); + } else { + mfc_core_debug(2, "There is a waiting module\n"); + listable_wq = list_entry(core->hwlock.waiting_list.next, + struct mfc_listable_wq, list); + list_del(&listable_wq->list); + core->hwlock.wl_count--; + + if (listable_wq->core) { + mfc_core_debug(2, "Waking up core\n"); + core->hwlock.dev = 1; + } else { + mfc_core_debug(2, "Waking up another ctx\n"); + set_bit(listable_wq->core_ctx->num, &core->hwlock.bits); + } + + core->hwlock.transfer_owner = 1; + + wake_up(&listable_wq->wait_queue); + } + + __mfc_print_hwlock(core); +} + +void mfc_core_release_hwlock_dev(struct mfc_core *core) +{ + unsigned long flags; + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + core->hwlock.dev = 0; + core->hwlock.owned_by_irq = 0; + + __mfc_release_hwlock(core); + + spin_unlock_irqrestore(&core->hwlock.lock, flags); +} + +void mfc_core_release_hwlock_ctx(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + unsigned long flags; + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + clear_bit(core_ctx->num, &core->hwlock.bits); + core->hwlock.owned_by_irq = 0; + + __mfc_release_hwlock(core); + + spin_unlock_irqrestore(&core->hwlock.lock, flags); +} + +/* Run an operation on hardware */ +int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[new_ctx_index]; + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + unsigned int ret = 0; + int prio; + + mfc_core_idle_update_hw_run(core, ctx); + + if (core->state == MFCCORE_ERROR || core_ctx->state == MFCINST_ERROR) { + mfc_info("[MSR] Couldn't run HW. It's Error state\n"); + return 0; + } + + if (core_ctx->state == MFCINST_RUNNING) + mfc_clean_core_ctx_int_flags(core_ctx); + + mfc_debug(2, "New context: %d\n", new_ctx_index); + core->curr_core_ctx = core_ctx->num; + if (core->sched_type == MFC_SCHED_PRIO) { + spin_lock_irqsave(&core->prio_work_lock, flags); + prio = mfc_get_prio(core, ctx->rt, ctx->prio); + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + core->last_core_ctx[prio] = core_ctx->num; + core->next_ctx_idx = -1; + } + + mfc_debug(2, "core_ctx->state = %d\n", core_ctx->state); + /* Last frame has already been sent to MFC + * Now obtaining frames from MFC buffer + */ + + mfc_debug(2, "continue_clock_on = %d\n", core->continue_clock_on); + if (!core->continue_clock_on) + mfc_core_pm_clock_on(core, 1); + else + core->continue_clock_on = false; + + return ret; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h new file mode 100644 index 000000000000..35f34f306d7d --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_hwlock.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_HWLOCK_H +#define __MFC_CORE_HWLOCK_H __FILE__ + +#include "base/mfc_common.h" + +static inline void mfc_core_init_listable_wq_dev(struct mfc_core *core) +{ + if (!core) { + mfc_pr_err("no mfc core device to run\n"); + return; + } + + INIT_LIST_HEAD(&core->hwlock_wq.list); + init_waitqueue_head(&core->hwlock_wq.wait_queue); + mutex_init(&core->hwlock_wq.wait_mutex); + core->hwlock_wq.core_ctx = NULL; + core->hwlock_wq.core = core; +} + +static inline void mfc_core_init_listable_wq_ctx(struct mfc_core_ctx *core_ctx) +{ + if (!core_ctx) { + mfc_pr_err("no mfc core context to run\n"); + return; + } + + INIT_LIST_HEAD(&core_ctx->hwlock_wq.list); + init_waitqueue_head(&core_ctx->hwlock_wq.wait_queue); + mutex_init(&core_ctx->hwlock_wq.wait_mutex); + core_ctx->hwlock_wq.core_ctx = core_ctx; + core_ctx->hwlock_wq.core = NULL; +} + +static inline void mfc_core_destroy_listable_wq_core(struct mfc_core *core) +{ + if (!core) { + mfc_pr_err("no mfc core device to run\n"); + return; + } + + mutex_destroy(&core->hwlock_wq.wait_mutex); +} + +static inline void mfc_core_destroy_listable_wq_ctx(struct mfc_core_ctx *core_ctx) +{ + if (!core_ctx) { + mfc_pr_err("no mfc core context to run\n"); + return; + } + + mutex_destroy(&core_ctx->hwlock_wq.wait_mutex); +} + +void mfc_core_init_hwlock(struct mfc_core *core); + +int mfc_core_get_hwlock_dev(struct mfc_core *core); +int mfc_core_get_hwlock_ctx(struct mfc_core_ctx *core_ctx); + +void mfc_core_release_hwlock_dev(struct mfc_core *core); +void mfc_core_release_hwlock_ctx(struct mfc_core_ctx *core_ctx); +int mfc_core_just_run(struct mfc_core *core, int new_ctx_index); +#endif /* __MFC_CORE_HWLOCK_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c new file mode 100644 index 000000000000..facb7255c400 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_intlock.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_intlock.h" +#include "mfc_core_isr.h" + +void mfc_clear_core_intlock(struct mfc_ctx *ctx) +{ + mutex_lock(&ctx->intlock.core_mutex); + + ctx->intlock.bits = 0; + + mutex_unlock(&ctx->intlock.core_mutex); +} + +int mfc_get_core_intlock(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_dev *dev = core->dev; + struct mfc_ctx *ctx = core_ctx->ctx; + + if (!(IS_TWO_MODE2(ctx) && core_ctx->state == MFCINST_RUNNING)) + return 0; + + mutex_lock(&ctx->intlock.core_mutex); + + if (ctx->intlock.lock) { + mfc_debug(2, "[2CORE] previous interrupt isn't handled yet\n"); + set_bit(core->id, &ctx->intlock.pending); + mutex_unlock(&ctx->intlock.core_mutex); + return -1; + } + + /* + * 1) First interrupt case, should be core0. + * 2) Previous interrupt number should be different with current core. + */ + if ((!ctx->intlock.bits && core->id != 0) || + ctx->intlock.bits & BIT(core->id)) { + mfc_debug(2, "[2CORE] interrupt reverse, MFC-%d isr should be delayed handled\n", + core->id); + MFC_TRACE_RM("[c:%d] MFC-%d ISR reverse\n", ctx->num, core->id); + set_bit(core->id, &ctx->intlock.pending); + mutex_unlock(&ctx->intlock.core_mutex); + return -1; + } + + ctx->intlock.lock = 1; + ctx->intlock.bits = 0; + set_bit(core->id, &ctx->intlock.bits); + mfc_debug(3, "[2CORE] get core int lock: %#08lx\n", ctx->intlock.bits); + + mutex_unlock(&ctx->intlock.core_mutex); + + return 0; +} + +void mfc_release_core_intlock(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_dev *dev = core->dev; + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_core *pending_core = NULL; + int i; + + mutex_lock(&ctx->intlock.core_mutex); + + if (!ctx->intlock.lock) { + mfc_debug(4, "[2CORE] have been didn't get intlock\n"); + mutex_unlock(&ctx->intlock.core_mutex); + return; + } + + ctx->intlock.lock = 0; + mfc_debug(3, "[2CORE] release core int lock\n"); + + for (i = 0; i < dev->num_core; i++) { + if (ctx->intlock.pending & BIT(i)) { + pending_core = dev->core[i]; + clear_bit(i, &ctx->intlock.pending); + mfc_debug(2, "[2CORE] interrupt pending clear\n"); + MFC_TRACE_RM("[c:%d] MFC-%d ISR delayed handle\n", ctx->num, core->id); + } + } + + mutex_unlock(&ctx->intlock.core_mutex); + + if (pending_core) + mfc_core_irq(pending_core->irq, pending_core); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h new file mode 100644 index 000000000000..e1e2e9bdaabb --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_intlock.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_INTLOCK_H +#define __MFC_CORE_INTLOCK_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_clear_core_intlock(struct mfc_ctx *ctx); +int mfc_get_core_intlock(struct mfc_core_ctx *core_ctx); +void mfc_release_core_intlock(struct mfc_core_ctx *core_ctx); + +#endif /* __MFC_CORE_INTLOCK_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c new file mode 100644 index 000000000000..4c6f531ffc02 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_isr.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_intlock.h" +#include "mfc_core_pm.h" + +#include "mfc_core_hw_reg_api.h" +#include "mfc_core_reg_api.h" + +#include "base/mfc_utils.h" + +static inline int __mfc_core_is_err_condition(unsigned int err) +{ + switch (err) { + case MFC_REG_ERR_NO_AVAILABLE_DPB: + case MFC_REG_ERR_INSUFFICIENT_DPB_SIZE: + case MFC_REG_ERR_INSUFFICIENT_NUM_DPB: + case MFC_REG_ERR_INSUFFICIENT_MV_BUF_SIZE: + case MFC_REG_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE: + case MFC_REG_ERR_UNDEFINED_EXCEPTION: + return 1; + default: + return 0; + } +} + +irqreturn_t mfc_core_top_half_irq(int irq, void *priv) +{ + struct mfc_core *core = priv; + struct mfc_core_ctx *core_ctx; + unsigned int err; + unsigned int reason; + + core_ctx = core->core_ctx[core->curr_core_ctx]; + if (!core_ctx) { + mfc_core_err("no mfc context to run\n"); + return IRQ_WAKE_THREAD; + } + + reason = mfc_core_get_int_reason(); + err = mfc_core_get_int_err(); + + core->last_int = reason; + core->last_int_time = ktime_to_timespec64(ktime_get()); + + mfc_debug(2, "[c:%d] Int reason: %d (err: %d, warn: %d)\n", + core->curr_core_ctx, reason, mfc_get_err(err), mfc_get_warn(err)); + MFC_TRACE_CORE_CTX("<< INT(top): %d\n", reason); + MFC_TRACE_LOG_CORE("I%d", reason); + + return IRQ_WAKE_THREAD; +} + +static int __mfc_irq_dev(struct mfc_core *core, unsigned int reason, unsigned int err) +{ + switch (reason) { + case MFC_REG_R2H_CMD_CACHE_FLUSH_RET: + case MFC_REG_R2H_CMD_SYS_INIT_RET: + case MFC_REG_R2H_CMD_FW_STATUS_RET: + case MFC_REG_R2H_CMD_SLEEP_RET: + case MFC_REG_R2H_CMD_WAKEUP_RET: + mfc_core_clear_int(); + mfc_wake_up_core(core, reason, err); + return 0; + } + + return 1; +} + +/* Interrupt processing */ +irqreturn_t mfc_core_irq(int irq, void *priv) +{ + struct mfc_core *core = priv; + struct mfc_core_ctx *core_ctx; + struct mfc_ctx *ctx; + unsigned int reason; + unsigned int err; + int ret = -1; + + mfc_core_debug_enter(); + + if (mfc_core_get_pwr_ref_cnt(core) == 0) { + mfc_core_err("no mfc power on\n"); + goto irq_end; + } + + /* Get the reason of interrupt and the error code */ + reason = mfc_core_get_int_reason(); + err = mfc_core_get_int_err(); + mfc_core_debug(1, "[c:%d] Int reason: %d (err: %d, warn: %d)\n", + core->curr_core_ctx, reason, + mfc_get_err(err), mfc_get_warn(err)); + MFC_TRACE_CORE("<< INT: %d (err: %d)\n", reason, err); + + core->preempt_core_ctx = MFC_NO_INSTANCE_SET; + + if (core->dev->debugfs.dbg_enable && reason != MFC_REG_R2H_CMD_QUEUE_DONE_RET) + mfc_core_dbg_disable(core); + + if (__mfc_core_is_err_condition(err)) { + mfc_err("Interrupt Error Value %d", err); + WARN_ON(1); + } + + ret = __mfc_irq_dev(core, reason, err); + if (!ret) + goto irq_end; + mfc_ctx_info("not implemented context irq ctx"); + +irq_end: + mfc_core_debug_leave(); + return IRQ_HANDLED; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h new file mode 100644 index 000000000000..046b20e6d4c2 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_isr.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_ISR_H +#define __MFC_CORE_ISR_H __FILE__ + +#include <linux/interrupt.h> + +#include "mfc_rm.h" + +#include "base/mfc_utils.h" + +irqreturn_t mfc_core_top_half_irq(int irq, void *priv); +irqreturn_t mfc_core_irq(int irq, void *priv); +#endif /* __MFC_CORE_ISR_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c new file mode 100644 index 000000000000..fd7ebe95e715 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_run.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_run.h" + +#include "mfc_core_pm.h" +#include "mfc_core_sync.h" + +#include "mfc_core_cmd.h" +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_utils.h" +#include "base/mfc_mem.h" + +void mfc_core_run_cache_flush(struct mfc_core *core, + enum mfc_do_cache_flush do_cache_flush, + int reg_clear) +{ + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't lock HW. It's Error state\n"); + return; + } + + if (do_cache_flush == MFC_CACHEFLUSH) { + mfc_core_cmd_cache_flush(core); + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { + mfc_core_err("Failed to CACHE_FLUSH\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_CACHE_FLUSH); + } + } else if (do_cache_flush == MFC_NO_CACHEFLUSH) { + mfc_core_debug(2, "F/W has already done cache flush with prediction\n"); + } + + /* When init_hw(), reg_clear is required between cache flush and (un)protection */ + if (reg_clear) { + mfc_core_reg_clear(core); + mfc_core_debug(2, "Done register clear\n"); + } +} + +/* Initialize hardware */ +int mfc_core_run_init_hw(struct mfc_core *core) +{ + enum mfc_buf_usage_type buf_type; + int fw_ver; + int ret = 0; + + mfc_core_debug(2, "F/W initialize start\n"); + + /* 0. MFC reset */ + ret = mfc_core_pm_clock_on(core, 0); + if (ret) { + mfc_core_err("Failed to enable clock before reset(%d)\n", ret); + return ret; + } + + mfc_core_pm_clock_get(core); + + mfc_core_run_cache_flush(core, MFC_NO_CACHEFLUSH, 1); + + mfc_core_reset_mfc(core); + mfc_core_debug(2, "Done MFC reset\n"); + + /* 1. Set DRAM base Addr */ + mfc_core_set_risc_base_addr(core); + + /* 2. Release reset signal to the RISC */ + mfc_core_risc_on(core); + + mfc_core_debug(2, "Will now wait for completion of firmware transfer\n"); + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_FW_STATUS_RET)) { + mfc_core_err("Failed to RISC_ON\n"); + mfc_core_clean_dev_int_flags(core); + ret = -EIO; + goto err_init_hw; + } + + /* 3. Initialize firmware */ + mfc_core_cmd_sys_init(core, buf_type); + + mfc_core_debug(2, "Ok, now will write a command to init the system\n"); + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_SYS_INIT_RET)) { + mfc_core_err("Failed to SYS_INIT\n"); + mfc_core_clean_dev_int_flags(core); + ret = -EIO; + goto err_init_hw; + } + + core->int_condition = 0; + if (core->int_err != 0 || core->int_reason != MFC_REG_R2H_CMD_SYS_INIT_RET) { + /* Failure. */ + mfc_core_err("Failed to init firmware - error: %d, int: %d\n", + core->int_err, core->int_reason); + ret = -EIO; + goto err_init_hw; + } + + core->fw.fimv_info = mfc_core_get_fimv_info(); + if (core->fw.fimv_info != 'D' && core->fw.fimv_info != 'E') + core->fw.fimv_info = 'N'; + + mfc_core_info("[F/W] MFC v%x, %02xyy %02xmm %02xdd (%c)\n", + core->core_pdata->ip_ver, + mfc_core_get_fw_ver_year(), + mfc_core_get_fw_ver_month(), + mfc_core_get_fw_ver_date(), + core->fw.fimv_info); + + core->fw.date = mfc_core_get_fw_ver_all(); + /* Check MFC version and F/W version */ + fw_ver = mfc_core_get_mfc_version(); + if ((fw_ver & MFC_REG_MFC_VER_MAJOR_MASK) != core->core_pdata->ip_ver) { + mfc_core_err("Invalid F/W version(0x%x) for MFC H/W(0x%x)\n", + fw_ver, core->core_pdata->ip_ver); + ret = -EIO; + goto err_init_hw; + } + core->dev->fw_changed_info = (fw_ver & MFC_REG_MFC_VER_MINOR_MASK); + + mfc_core_change_fw_state(core, MFC_FW_INITIALIZED, 1); + +err_init_hw: + mfc_core_pm_clock_off(core, 0); + mfc_core_debug_leave(); + + return ret; +} + +/* Deinitialize hardware */ +void mfc_core_run_deinit_hw(struct mfc_core *core) +{ + int ret; + + mfc_core_debug(2, "mfc deinit start\n"); + + ret = mfc_core_pm_clock_on(core, 0); + if (ret) { + mfc_core_err("Failed to enable clock before reset(%d)\n", ret); + return; + } + + mfc_core_mfc_off(core); + + mfc_core_pm_clock_off(core, 0); + + mfc_core_debug(2, "mfc deinit completed\n"); +} + +int mfc_core_run_sleep(struct mfc_core *core) +{ + struct mfc_core_ctx *core_ctx; + int i; + + mfc_core_debug_enter(); + + core_ctx = core->core_ctx[core->curr_core_ctx]; + if (!core_ctx) { + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (core->core_ctx[i]) { + core_ctx = core->core_ctx[i]; + break; + } + } + + if (!core_ctx) { + mfc_core_err("no mfc context to run\n"); + return -EINVAL; + } + mfc_info("ctx is changed %d -> %d\n", + core->curr_core_ctx, core_ctx->num); + + core->curr_core_ctx = core_ctx->num; + } + + mfc_core_pm_clock_on(core, 0); + mfc_core_cmd_sleep(core); + + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_SLEEP_RET)) { + mfc_err("Failed to SLEEP\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_SLEEP); + return -EBUSY; + } + + core->int_condition = 0; + if (core->int_err != 0 || core->int_reason != MFC_REG_R2H_CMD_SLEEP_RET) { + /* Failure. */ + mfc_err("Failed to sleep - error: %d, int: %d\n", + core->int_err, core->int_reason); + return -EBUSY; + } + + core->sleep = 1; + + mfc_core_mfc_always_off(core); + mfc_core_pm_clock_off(core, 0); + + mfc_core_debug_leave(); + + return 0; +} + +int mfc_core_run_wakeup(struct mfc_core *core) +{ + int ret = 0; + + mfc_core_debug_enter(); + + /* 0. MFC reset */ + ret = mfc_core_pm_clock_on(core, 0); + if (ret) { + mfc_core_err("Failed to enable clock before reset(%d)\n", ret); + return ret; + } + mfc_core_reg_clear(core); + mfc_core_debug(2, "Done register clear\n"); + + mfc_core_reset_mfc(core); + mfc_core_debug(2, "Done MFC reset\n"); + + /* 1. Set DRAM base Addr */ + mfc_core_set_risc_base_addr(core); + + /* 2. Release reset signal to the RISC */ + mfc_core_risc_on(core); + + mfc_core_debug(2, "Will now wait for completion of firmware transfer\n"); + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_FW_STATUS_RET)) { + mfc_core_err("Failed to RISC_ON\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_RISC_ON); + return -EBUSY; + } + + mfc_core_debug(2, "Ok, now will write a command to wakeup the system\n"); + mfc_core_cmd_wakeup(core); + + mfc_core_debug(2, "Will now wait for completion of firmware wake up\n"); + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_WAKEUP_RET)) { + mfc_core_err("Failed to WAKEUP\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_WAKEUP); + return -EBUSY; + } + + core->int_condition = 0; + if (core->int_err != 0 || core->int_reason != MFC_REG_R2H_CMD_WAKEUP_RET) { + /* Failure. */ + mfc_core_err("Failed to wakeup - error: %d, int: %d\n", + core->int_err, core->int_reason); + } + + core->sleep = 0; + + mfc_core_pm_clock_off(core, 0); + + mfc_core_debug_leave(); + + return ret; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h new file mode 100644 index 000000000000..3d243dc18e15 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_run.h + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_CORE_RUN_H +#define __MFC_CORE_RUN_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_core_run_cache_flush(struct mfc_core *core, + enum mfc_do_cache_flush do_cache_flush, + int reg_clear); + +int mfc_core_run_init_hw(struct mfc_core *core); +void mfc_core_run_deinit_hw(struct mfc_core *core); + +int mfc_core_run_sleep(struct mfc_core *core); +int mfc_core_run_wakeup(struct mfc_core *core); +#endif /* __MFC_CORE_RUN_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035551epcas5p4ee7cb5af08eadb2f5ed6e5eaa06a60a9@epcas5p4.samsung.com>]
* [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support [not found] ` <CGME20250930035551epcas5p4ee7cb5af08eadb2f5ed6e5eaa06a60a9@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 2025-09-30 5:54 ` Krzysztof Kozlowski 0 siblings, 1 reply; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung Exynos MFC driver that supports firmware version 13 and later. Extend the top‑level Samsung platform Kconfig to disable the legacy S5P‑MFC driver when its firmware version is > v12 and to select the new Exynos‑MFC driver only when VIDEO_SAMSUNG_S5P_MFC is not enabled. Add exynos-mfc Kconfig and Makefile for probe functionality and creation of decoder and encoder device files by registering the driver object exynos_mfc.o and other relevant source files. Provide header files mfc_core_ops.h and mfc_rm.h containing core operation prototypes, resource‑manager helpers, and core‑selection utilities. Add a configurable option MFC_USE_COREDUMP to enable core‑dump support for debugging MFC errors. These changes bring support for newer Exynos‑based MFC hardware, cleanly separate it from the legacy S5P‑MFC driver, and lay the groundwork for future feature development and debugging. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- drivers/media/platform/samsung/Kconfig | 7 + drivers/media/platform/samsung/Makefile | 1 + .../media/platform/samsung/exynos-mfc/Kconfig | 34 + .../platform/samsung/exynos-mfc/Makefile | 24 + .../media/platform/samsung/exynos-mfc/mfc.c | 725 ++++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_core.c | 530 +++++++++++++ .../samsung/exynos-mfc/mfc_core_ops.c | 289 +++++++ .../samsung/exynos-mfc/mfc_core_ops.h | 16 + .../samsung/exynos-mfc/mfc_core_sched_prio.c | 100 +++ .../platform/samsung/exynos-mfc/mfc_rm.c | 142 ++++ .../platform/samsung/exynos-mfc/mfc_rm.h | 56 ++ 11 files changed, 1924 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/Kconfig create mode 100644 drivers/media/platform/samsung/exynos-mfc/Makefile create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.h diff --git a/drivers/media/platform/samsung/Kconfig b/drivers/media/platform/samsung/Kconfig index 0e34c5fc1dfc..13790b004f14 100644 --- a/drivers/media/platform/samsung/Kconfig +++ b/drivers/media/platform/samsung/Kconfig @@ -7,4 +7,11 @@ source "drivers/media/platform/samsung/exynos4-is/Kconfig" source "drivers/media/platform/samsung/s3c-camif/Kconfig" source "drivers/media/platform/samsung/s5p-g2d/Kconfig" source "drivers/media/platform/samsung/s5p-jpeg/Kconfig" + +comment "Disable S5P-MFC (FW <= v12) to select Exynos-MFC (FW >= v13)" + source "drivers/media/platform/samsung/s5p-mfc/Kconfig" + +if !VIDEO_SAMSUNG_S5P_MFC && !(VIDEO_SAMSUNG_S5P_MFC = m) +source "drivers/media/platform/samsung/exynos-mfc/Kconfig" +endif diff --git a/drivers/media/platform/samsung/Makefile b/drivers/media/platform/samsung/Makefile index 21fea3330e4b..afda9713d966 100644 --- a/drivers/media/platform/samsung/Makefile +++ b/drivers/media/platform/samsung/Makefile @@ -5,3 +5,4 @@ obj-y += s3c-camif/ obj-y += s5p-g2d/ obj-y += s5p-jpeg/ obj-y += s5p-mfc/ +obj-y += exynos-mfc/ diff --git a/drivers/media/platform/samsung/exynos-mfc/Kconfig b/drivers/media/platform/samsung/exynos-mfc/Kconfig new file mode 100644 index 000000000000..8b0212100994 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/Kconfig @@ -0,0 +1,34 @@ +config VIDEO_EXYNOS_MFC + tristate "Samsung Exynos MFC Driver (FW v13+)" + default n + depends on !VIDEO_SAMSUNG_S5P_MFC + select DMABUF_HEAPS + select DMABUF_HEAPS_SYSTEM + select DMABUF_HEAPS_CMA if !EXYNOS_IOMMU + select VIDEOBUF2_CORE + select VIDEOBUF2_DMA_SG + help + Enables the Exynos Multi‑Format Codec (MFC) driver for the V4L2 + subsystem, providing hardware‑accelerated video decoding and + encoding on Samsung Exynos SoCs that ship with firmware version 13 + or newer. The driver offloads video processing from the CPU, + improving performance and reducing power consumption for a wide + range of codecs and picture formats. It integrates with the + DMABUF‑HEAPS and videobuf2 frameworks for efficient buffer management + and should be selected only when the legacy VIDEO_SAMSUNG_S5P_MFC + driver is not present. Disable this option on platforms lacking + the required firmware version or when you prefer the older driver. + +config MFC_USE_COREDUMP + bool "MFC COREDUMP support" + default n + depends on VIDEO_EXYNOS_MFC + help + Enables generation of a core dump when the Exynos MFC driver + encounters a fatal error or hardware fault. The dump captures + internal driver state, register contents, and relevant buffer + information, providing valuable context for post‑mortem analysis. + This aids developers and integrators in diagnosing codec crashes + and improving driver stability without requiring a full system + reboot. Use this option only when debugging is needed, as it + may increase memory usage and expose sensitive data. diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile new file mode 100644 index 000000000000..bee95b16ac7c --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -0,0 +1,24 @@ +obj-$(CONFIG_VIDEO_EXYNOS_MFC) := exynos_mfc.o +#Header include +ccflags-y += -I$(srctree)/$(src) + +#Dev interface layer +exynos_mfc-y += mfc.o +#Dev control layer +exynos_mfc-y += mfc_rm.o mfc_debugfs.o +#Core interface layer +exynos_mfc-y += mfc_core.o mfc_core_ops.o mfc_core_isr.o +#Core control layer +exynos_mfc-y += mfc_core_hwlock.o mfc_core_intlock.o mfc_core_run.o +exynos_mfc-y += mfc_core_pm.o +exynos_mfc-y += mfc_core_sync.o mfc_core_sched_prio.o +#Core HW access layer +exynos_mfc-y += mfc_core_cmd.o +exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o +#Plugin interface layer +#Plugin control layer +#Plugin HW access layer +#Common base layer +exynos_mfc-y += base/mfc_buf.o base/mfc_mem.o +#Tracing +# exynos_mfc-y += trace/mfc_trace_points.o diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc.c b/drivers/media/platform/samsung/exynos-mfc/mfc.c new file mode 100644 index 000000000000..b5b66083cc8b --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc.c @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/of.h> +#include <linux/of_reserved_mem.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/poll.h> +#include <linux/iommu.h> + +#include "mfc_rm.h" +#include "mfc_debugfs.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_run.h" + +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" + +#define MFC_NAME "exynos-mfc" +#define MFC_DEC_NAME "exynos-mfc-dec" +#define MFC_ENC_NAME "exynos-mfc-enc" + +struct _mfc_trace g_mfc_trace[MFC_TRACE_COUNT_MAX]; +struct _mfc_trace g_mfc_trace_rm[MFC_TRACE_COUNT_MAX]; +struct _mfc_trace g_mfc_trace_longterm[MFC_TRACE_COUNT_MAX]; + +/* Open an MFC node */ +static int mfc_open(struct file *file) +{ + struct mfc_ctx *ctx = NULL; + struct mfc_dev *dev = video_drvdata(file); + int i, ret = 0; + enum mfc_node_type node; + struct video_device *vdev = NULL; + + if (!dev) { + mfc_pr_err("no mfc device to run\n"); + goto err_no_device; + } + + mfc_dev_debug(2, "mfc driver open called\n"); + + if (mutex_lock_interruptible(&dev->mfc_mutex)) + return -ERESTARTSYS; + + node = mfc_get_node_type(file); + if (node == MFCNODE_INVALID) { + mfc_dev_err("cannot specify node type\n"); + ret = -ENOENT; + goto err_node_type; + } + + dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ + + /* Allocate memory for context */ + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) { + ret = -ENOMEM; + goto err_ctx_alloc; + } + + switch (node) { + case MFCNODE_DECODER: + vdev = dev->vfd_dec; + break; + case MFCNODE_ENCODER: + vdev = dev->vfd_enc; + break; + default: + mfc_dev_err("Invalid node(%d)\n", node); + break; + } + + if (!vdev) + goto err_vdev; + + v4l2_fh_init(&ctx->fh, vdev); + file->private_data = &ctx->fh; + v4l2_fh_add(&ctx->fh, file); + + ctx->dev = dev; + + /* Get context number */ + ctx->num = 0; + while (dev->ctx[ctx->num]) { + ctx->num++; + if (ctx->num >= MFC_NUM_CONTEXTS) { + mfc_ctx_err("Too many open contexts\n"); + mfc_ctx_err("Print information to check if there was an error or not\n"); + ret = -EBUSY; + goto err_ctx_num; + } + } + + spin_lock_init(&ctx->corelock.lock); + mutex_init(&ctx->intlock.core_mutex); + mutex_init(&ctx->op_mode_mutex); + init_waitqueue_head(&ctx->corelock.wq); + + mfc_ctx_change_idle_mode(ctx, MFC_IDLE_MODE_NONE); + + if (mfc_is_decoder_node(node)) { + ctx->type = MFCINST_DECODER; + dev->num_dec_inst++; + } else { + ctx->type = MFCINST_ENCODER; + dev->num_enc_inst++; + } + + if (dev->num_inst == 1) { + /* all of the ctx list */ + INIT_LIST_HEAD(&dev->ctx_list); + spin_lock_init(&dev->ctx_list_lock); + /* idle mode */ + spin_lock_init(&dev->idle_bits_lock); + } + + mfc_ctx_info + ("NORMAL %s instance is opened [%d]\n", + ctx->type == MFCINST_DECODER ? "Decoder" : "Encoder", + dev->num_inst); + + /* Mark context as idle */ + dev->ctx[ctx->num] = ctx; + for (i = 0; i < MFC_NUM_CORE; i++) + ctx->op_core_num[i] = MFC_CORE_INVALID; + + ret = mfc_rm_instance_init(dev, ctx); + if (ret) { + mfc_ctx_err("rm_instance_init failed\n"); + goto err_inst_init; + } + + mfc_ctx_info + ("MFC open completed [%d] version = %d\n", + dev->num_inst, MFC_DRIVER_INFO); + MFC_TRACE_CTX_LT + ("[INFO] %s opened (ctx:%d, total:%d)\n", + mfc_is_decoder_node(node) ? "DEC" : "ENC", ctx->num, dev->num_inst); + + mutex_unlock(&dev->mfc_mutex); + return ret; + + /* Deinit when failure occurred */ +err_inst_init: + if (mfc_is_decoder_node(node)) + dev->num_dec_inst--; + else + dev->num_enc_inst--; + dev->ctx[ctx->num] = 0; + +err_ctx_num: + v4l2_fh_del(&ctx->fh, file); + v4l2_fh_exit(&ctx->fh); + +err_vdev: + kfree(ctx); + +err_ctx_alloc: + dev->num_inst--; + +err_node_type: + mfc_dev_err + ("MFC driver open is failed [%d]\n", + dev->num_inst); + mutex_unlock(&dev->mfc_mutex); + +err_no_device: + + return ret; +} + +/* Release MFC context */ +static int mfc_release(struct file *file) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + int ret = 0; + unsigned long flags; + + mutex_lock(&dev->mfc_mutex); + + mfc_ctx_info + ("%s instance release is called [%d]\n", + ctx->type == MFCINST_DECODER ? "Decoder" : "Encoder", + dev->num_inst); + + MFC_TRACE_CTX_LT("[INFO] release is called (ctx:%d, total:%d)\n", ctx->num, dev->num_inst); + + /* Free resources */ + v4l2_fh_del(&ctx->fh, file); + v4l2_fh_exit(&ctx->fh); + + /* + * mfc_release() can be called without a streamoff + * when the application is forcibly terminated. + * At that time, stop_streaming() is called by vb2_queue_release. + * So, we need to performed stop_streaming + * before instance de-init(CLOSE_INSTANCE). + */ + + ret = mfc_rm_instance_deinit(dev, ctx); + if (ret) { + mfc_dev_err("failed to rm_instance_deinit\n"); + goto end_release; + } + + dev->num_inst--; + + if (ctx->type == MFCINST_DECODER) + dev->num_dec_inst--; + else if (ctx->type == MFCINST_ENCODER) + dev->num_enc_inst--; + + MFC_TRACE_CTX_LT("[INFO] Release finished (ctx:%d, total:%d)\n", ctx->num, dev->num_inst); + + spin_lock_irqsave(&dev->ctx_list_lock, flags); + dev->ctx[ctx->num] = NULL; + kfree(ctx); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + + mfc_dev_info("mfc driver release finished [%d]\n", dev->num_inst); + +end_release: + mutex_unlock(&dev->mfc_mutex); + return ret; +} + +/* v4l2 ops */ +static const struct v4l2_file_operations mfc_fops = { + .owner = THIS_MODULE, + .open = mfc_open, + .release = mfc_release, + .poll = NULL, + .unlocked_ioctl = video_ioctl2, +}; + +static void __mfc_parse_dt_resource(struct mfc_dev *dev, struct device_node *np) +{ + struct device_node *np_resource; + struct device_node *np_tmp; + int idx = 0; + struct mfc_resource *resource; + unsigned int codec_mode; + + /* Initialization */ + for (idx = 0; idx < MFC_MAX_CODEC_TYPE; idx++) { + resource = &dev->pdata->mfc_resource[idx]; + resource->op_core_type = MFC_OP_CORE_NOT_FIXED; + } + + np_resource = of_get_child_by_name(np, "mfc_resource"); + if (!np_resource) { + dev_err(dev->device, "there is no mfc_resource\n"); + return; + } + + /* Parse resource information */ + for_each_child_of_node(np_resource, np_tmp) { + idx = 0; + of_property_read_u32_index(np_tmp, "info", idx++, &codec_mode); + resource = &dev->pdata->mfc_resource[codec_mode]; + of_property_read_u32_index(np_tmp, "info", idx++, (u32 *)&resource->op_core_type); + } +} + +static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) +{ + struct mfc_platdata *pdata = mfc->pdata; + + if (!np) { + dev_err(mfc->device, "there is no device node\n"); + return -EINVAL; + } + + /* MFC FW memory size */ + of_property_read_u32(np, "fw_mem_size", &pdata->fw_mem_size); + + /* MFC DVA reservation start address and DMA bit mask */ + of_property_read_u32(np, "reserved_start", &pdata->reserved_start); + of_property_read_u32(np, "dma_bit_mask", &pdata->dma_bit_mask); + + /* MFC version */ + of_property_read_u32(np, "ip_ver", &pdata->ip_ver); + + /* MFC firmware name */ + of_property_read_string(np, "fw_name", &pdata->fw_name); + + /* Debug mode */ + of_property_read_u32(np, "debug_mode", &pdata->debug_mode); + + /* Resource of standard */ + __mfc_parse_dt_resource(mfc, np); + + of_property_read_u32_array + (np, "mem_clear", + &pdata->mem_clear.support, 2); + of_property_read_u32_array + (np, "wait_fw_status", + &pdata->wait_fw_status.support, 2); + + /* Scheduler */ + of_property_read_u32(np, "scheduler", &pdata->scheduler); + of_property_read_u32(np, "pbs_num_prio", &pdata->pbs_num_prio); + + return 0; +} + +static void *__mfc_get_drv_data(struct platform_device *pdev); + +static struct video_device *__mfc_video_device_register + (struct mfc_dev *dev, char *name, int node_num) +{ + struct video_device *vfd; + int ret = 0; + + vfd = video_device_alloc(); + if (!vfd) { + v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); + return NULL; + } + strscpy_pad(vfd->name, name, sizeof(vfd->name)); + vfd->fops = &mfc_fops; + vfd->minor = -1; + vfd->release = video_device_release; + + vfd->lock = &dev->mfc_mutex; + vfd->v4l2_dev = &dev->v4l2_dev; + vfd->vfl_dir = VFL_DIR_M2M; + set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags); + vfd->device_caps = V4L2_CAP_VIDEO_CAPTURE + | V4L2_CAP_VIDEO_OUTPUT + | V4L2_CAP_VIDEO_CAPTURE_MPLANE + | V4L2_CAP_VIDEO_OUTPUT_MPLANE + | V4L2_CAP_STREAMING; + + ret = video_register_device(vfd, VFL_TYPE_VIDEO, node_num); + if (ret) { + v4l2_err(&dev->v4l2_dev, + "Failed to register video device /dev/video%d\n", + node_num); + video_device_release(vfd); + return NULL; + } + v4l2_info + (&dev->v4l2_dev, "video device registered as /dev/video%d\n", + vfd->num); + video_set_drvdata(vfd, dev); + + return vfd; +} + +/* MFC probe function */ +static int mfc_probe(struct platform_device *pdev) +{ + struct device *device = &pdev->dev; + struct device_node *np = device->of_node; + struct mfc_dev *dev; + int ret = -ENOENT; + + dev_info(&pdev->dev, "%s is called\n", __func__); + + dev = devm_kzalloc(&pdev->dev, sizeof(struct mfc_dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + /* empty device for CPU cache flush with dma_sync_* API */ + dev->cache_op_dev = devm_kzalloc(&pdev->dev, sizeof(struct device), GFP_KERNEL); + device_initialize(dev->cache_op_dev); + dma_coerce_mask_and_coherent(dev->cache_op_dev, DMA_BIT_MASK(36)); + + dev->device = &pdev->dev; + dev->variant = __mfc_get_drv_data(pdev); + platform_set_drvdata(pdev, dev); + + dev->pdata = devm_kzalloc(&pdev->dev, sizeof(struct mfc_platdata), GFP_KERNEL); + if (!dev->pdata) { + ret = -ENOMEM; + goto err_res_mem; + } + + ret = __mfc_parse_dt(dev->device->of_node, dev); + if (ret) + goto err_res_mem; + + mfc_init_debugfs(dev); + + atomic_set(&dev->trace_ref, 0); + atomic_set(&dev->trace_ref_longterm, 0); + dev->mfc_trace = g_mfc_trace; + dev->mfc_trace_rm = g_mfc_trace_rm; + dev->mfc_trace_longterm = g_mfc_trace_longterm; + + if (dev->pdata->dma_bit_mask < MFC_MIN_BITMASK) + dev->pdata->dma_bit_mask = MFC_MIN_BITMASK; + dma_set_mask(&pdev->dev, DMA_BIT_MASK(dev->pdata->dma_bit_mask)); + + mutex_init(&dev->mfc_mutex); + + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); + if (ret) + goto err_v4l2_dev; + + /* decoder */ + dev->vfd_dec = __mfc_video_device_register + (dev, MFC_DEC_NAME, + EXYNOS_VIDEONODE_MFC_DEC); + if (!dev->vfd_dec) { + ret = -ENOMEM; + goto alloc_vdev_dec; + } + + /* encoder */ + dev->vfd_enc = __mfc_video_device_register + (dev, MFC_ENC_NAME, + EXYNOS_VIDEONODE_MFC_ENC); + if (!dev->vfd_enc) { + ret = -ENOMEM; + goto alloc_vdev_enc; + } + /* end of node setting*/ + + /* for DVA reservation */ + if (dev->pdata->reserved_start) { + dev->domain = iommu_get_domain_for_dev(dev->device); + ret = mfc_iova_pool_init(dev); + if (ret) { + mfc_dev_err("Failed to reserve memory (%d)\n", ret); + goto err_iova_reserve; + } + } + + ret = mfc_configure_dma_memory(dev); + if (ret) { + dev_err(&pdev->dev, "failed to configure DMA memory\n"); + goto err_iova_reserve; + } + __platform_driver_register(&mfc_core_driver, THIS_MODULE); + of_platform_populate(np, NULL, NULL, device); + + dev_info(&pdev->dev, "%s is completed\n", __func__); + + return 0; + +/* Deinit MFC if probe had failed */ +err_iova_reserve: + video_unregister_device(dev->vfd_enc); +alloc_vdev_enc: + video_unregister_device(dev->vfd_dec); +alloc_vdev_dec: + v4l2_device_unregister(&dev->v4l2_dev); +err_v4l2_dev: + mutex_destroy(&dev->mfc_mutex); +err_res_mem: + return ret; +} + +/* Remove the driver */ +static void mfc_remove(struct platform_device *pdev) +{ + struct mfc_dev *dev = platform_get_drvdata(pdev); + + mfc_dev_info("++MFC remove\n"); + + platform_driver_unregister(&mfc_core_driver); + mfc_unconfigure_dma_memory(dev); + of_reserved_mem_device_release(dev->device); + + mfc_deinit_debugfs(dev); + video_unregister_device(dev->vfd_enc); + video_unregister_device(dev->vfd_dec); + v4l2_device_unregister(&dev->v4l2_dev); + + mfc_dev_info("--MFC remove\n"); +} + +static void mfc_shutdown(struct platform_device *pdev) +{ + struct platform_driver *pcoredrv = &mfc_core_driver; + struct mfc_dev *dev = platform_get_drvdata(pdev); + struct mfc_core *core; + int i; + + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + mfc_dev_debug(2, "There is no core[%d]\n", i); + continue; + } + + if (!core->shutdown) { + mfc_core_info("%s core shutdown was not performed\n", core->name); + pcoredrv->shutdown(to_platform_device(core->device)); + } + } + + mfc_dev_info("MFC shutdown is completed\n"); +} + +#if IS_ENABLED(CONFIG_PM_SLEEP) +static int mfc_suspend(struct device *device) +{ + struct mfc_dev *dev = platform_get_drvdata(to_platform_device(device)); + struct mfc_core *core[MFC_NUM_CORE]; + int i, ret; + + if (!dev) { + dev_err(device, "no mfc device to run\n"); + return -EINVAL; + } + + for (i = 0; i < dev->num_core; i++) { + core[i] = dev->core[i]; + if (!core[i]) { + dev_err(device, "no mfc core%d device to run\n", i); + return -EINVAL; + } + + if (core[i]->state == MFCCORE_ERROR) { + dev_info(device, "[MSR] Couldn't sleep. It's Error state\n"); + return 0; + } + } + + /* + * Multi core mode instance can send sleep command + * when there are no H/W operation both two core. + */ + for (i = 0; i < dev->num_core; i++) { + core[i] = dev->core[i]; + if (!core[i]) { + dev_err(device, "no mfc core%d device to run\n", i); + return -EINVAL; + } + + if (core[i]->num_inst == 0) { + core[i] = NULL; + continue; + } + + mfc_dev_info("MFC%d will suspend\n", i); + + ret = mfc_core_get_hwlock_dev(core[i]); + if (ret < 0) { + mfc_dev_err("Failed to get hwlock for MFC%d\n", i); + mfc_dev_err + ("dev:0x%lx, bits:0x%lx, owned:%d, wl:%d, trans:%d\n", + core[i]->hwlock.dev, core[i]->hwlock.bits, + core[i]->hwlock.owned_by_irq, + core[i]->hwlock.wl_count, + core[i]->hwlock.transfer_owner); + return -EBUSY; + } + + if (!mfc_core_get_pwr_ref_cnt(core[i])) { + mfc_dev_info("MFC%d power has not been turned on yet\n", i); + mfc_core_release_hwlock_dev(core[i]); + core[i] = NULL; + continue; + } + } + + for (i = 0; i < dev->num_core; i++) { + if (core[i]) { + ret = mfc_core_run_sleep(core[i]); + if (ret) { + mfc_dev_err("Failed core_run_sleep for MFC%d\n", i); + return -EFAULT; + } + + mfc_core_release_hwlock_dev(core[i]); + + mfc_dev_info("MFC%d suspend is completed\n", i); + } + } + + return 0; +} + +static int mfc_resume(struct device *device) +{ + struct mfc_dev *dev = platform_get_drvdata(to_platform_device(device)); + struct mfc_core *core; + int i, ret; + + if (!dev) { + dev_err(device, "no mfc device to run\n"); + return -EINVAL; + } + + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + dev_err(device, "no mfc core%d device to run\n", i); + return -EINVAL; + } + + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't wakeup. It's Error state\n"); + return 0; + } + } + + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + dev_err(device, "no mfc core%d device to run\n", i); + return -EINVAL; + } + + if (core->num_inst == 0) + continue; + + mfc_dev_info("MFC%d will resume\n", i); + + ret = mfc_core_get_hwlock_dev(core); + if (ret < 0) { + mfc_dev_err("Failed to get hwlock for MFC%d\n", i); + mfc_dev_err + ("dev:0x%lx, bits:0x%lx, owned:%d, wl:%d, trans:%d\n", + core->hwlock.dev, + core->hwlock.bits, + core->hwlock.owned_by_irq, + core->hwlock.wl_count, + core->hwlock.transfer_owner); + return -EBUSY; + } + + ret = mfc_core_run_wakeup(core); + if (ret) { + mfc_dev_err("Failed core_run_wakeup for MFC%d\n", i); + return -EFAULT; + } + + mfc_core_release_hwlock_dev(core); + + mfc_dev_info("MFC%d resume is completed\n", i); + } + + return 0; +} +#endif + +/* Power management */ +static const struct dev_pm_ops mfc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mfc_suspend, mfc_resume) +}; + +struct mfc_ctx_buf_size mfc_ctx_buf_size = { + .dev_ctx = PAGE_ALIGN(0x7800), /* 30KB */ + .dbg_info_buf = PAGE_ALIGN(0x1000), /* 4KB for DEBUG INFO */ +}; + +struct mfc_buf_size mfc_buf_size = { + .firmware_code = PAGE_ALIGN(SZ_1M), /* 1MB */ + .ctx_buf = &mfc_ctx_buf_size, +}; + +static struct mfc_variant mfc_drvdata = { + .buf_size = &mfc_buf_size, + .num_entities = 2, +}; + +static const struct of_device_id exynos_mfc_match[] = { + { + .compatible = "samsung,exynos-mfc", + .data = &mfc_drvdata, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos_mfc_match); + +static void *__mfc_get_drv_data(struct platform_device *pdev) +{ + struct mfc_variant *driver_data = NULL; + + if (pdev->dev.of_node) { + const struct of_device_id *match; + + match = of_match_node + (of_match_ptr(exynos_mfc_match), + pdev->dev.of_node); + if (match) + driver_data = (struct mfc_variant *)match->data; + } else { + driver_data = (struct mfc_variant *) + platform_get_device_id(pdev)->driver_data; + } + return driver_data; +} + +static struct platform_driver mfc_driver = { + .probe = mfc_probe, + .remove = mfc_remove, + .shutdown = mfc_shutdown, + .driver = { + .name = MFC_NAME, + .owner = THIS_MODULE, + .pm = &mfc_pm_ops, + .of_match_table = exynos_mfc_match, + .suppress_bind_attrs = true, + }, +}; + +module_platform_driver(mfc_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c new file mode 100644 index 000000000000..4f5cf459c36f --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/of_address.h> +#include <linux/proc_fs.h> +#include <linux/of.h> + +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/poll.h> +#include <linux/vmalloc.h> +#include <linux/version.h> +#include <linux/iommu.h> +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) +#include <linux/samsung/samsung-iommu.h> +#endif + +#include "mfc_core_ops.h" +#include "mfc_core_isr.h" +#include "mfc_debugfs.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_run.h" + +#include "mfc_core_pm.h" + +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_sched.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" + +#define MFC_CORE_NAME "mfc-core" + +struct _mfc_trace_logging g_mfc_core_trace_logging[MFC_TRACE_LOG_COUNT_MAX]; + +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) +static int mfc_core_sysmmu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, + int data, void *param) +{ + struct mfc_core *core = (struct mfc_core *)param; + struct mfc_core_platdata *pdata = core->core_pdata; + unsigned int fault_status, fault_info1, fault_info2 = 0; + + if (mfc_core_get_pwr_ref_cnt(core) == 0) { + mfc_core_info("This is not a MFC issue(not executed)\n"); + return 0; + } + + /* MMU Fault Status: If no page fault has occurred, it has a value of 0 */ + if (pdata->fault_status) + fault_status = pdata->fault_status + (data * 0x1000); + else + fault_status = MFC_MMU_INTERRUPT_STATUS; + /* MMU_FAULT_INFO1_VM[31:0]: It has AXID value. */ + if (pdata->fault_info1) + fault_info1 = pdata->fault_info1 + (data * 0x1000); + else + fault_info1 = MFC_MMU_FAULT_TRANS_INFO; + /* MMU_FAULT_INFO2_VM[31:0]: It has PMMU ID[31:24], MASTER ID[11:7], STREAM ID[6:0] */ + if (pdata->fault_info2) + fault_info2 = pdata->fault_info2 + (data * 0x1000); + + if (core->has_2sysmmu) { + if ((!MFC_MMU0_READL(fault_status)) && + (!MFC_MMU1_READL(fault_status))) { + mfc_core_info + ("This is not a MFC issue(fault status is zero)\n"); + return 0; + } + } else { + if (MFC_MMU0_READL(fault_status) == 0) { + mfc_core_info + ("This is not a MFC issue(fault status is zero)\n"); + return 0; + } + } + + /* If sysmmu is used with other IPs, it should be checked whether it's an MFC fault */ + if (pdata->share_sysmmu) { + if (mfc_get_mmu0_value(fault_info1, 0, pdata->axid_mask) != + pdata->mfc_axid) { + mfc_core_err("This is not a MFC page fault\n"); + return 0; + } + } + + if (MFC_MMU0_READL(fault_status)) { + /* + * Since it has become complicated to distinguish + * read or write of page fault in IP driver, + * the cause of page fault in logging data is unified into + * the page fault. + */ + core->logging_data->cause |= BIT(MFC_CAUSE_0PAGE_FAULT); + core->logging_data->fault_status = MFC_MMU0_READL(fault_status); + core->logging_data->fault_trans_info = + MFC_MMU0_READL(fault_info1); + } + + if (core->has_2sysmmu) { + if (MFC_MMU1_READL(fault_status)) { + core->logging_data->cause |= + BIT(MFC_CAUSE_1PAGE_FAULT); + core->logging_data->fault_status = + MFC_MMU1_READL(fault_status); + core->logging_data->fault_trans_info = + MFC_MMU1_READL(fault_info1); + } + } + core->logging_data->fault_addr = iova; + + mfc_core_err + ("MFC-%d SysMMU PAGE FAULT at %#lx, AxID: %#x, fault_status: %#x\n", + core->id, iova, core->logging_data->fault_trans_info, + core->logging_data->fault_status); + MFC_TRACE_CORE("MFC-%d SysMMU PAGE FAULT at %#lx (AxID: %#x)\n", + core->id, iova, core->logging_data->fault_trans_info); + + /* + * if return 0, sysmmu occurs kernel panic for debugging + * if -EAGAIN, sysmmu doesn't occur kernel panic (but need async-fault in dt). + */ + return 0; +} +#endif + +static int __mfc_core_parse_dt(struct device_node *np, struct mfc_core *core) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + + if (!np) { + mfc_pr_err("there is no device node\n"); + return -EINVAL; + } + + /* MFC version */ + of_property_read_u32(np, "ip_ver", &pdata->ip_ver); + + /* Sysmmu check */ + of_property_read_u32(np, "share_sysmmu", &pdata->share_sysmmu); + of_property_read_u32(np, "fault_status", &pdata->fault_status); + of_property_read_u32(np, "fault_info1", &pdata->fault_info1); + of_property_read_u32(np, "axid_mask", &pdata->axid_mask); + of_property_read_u32(np, "mfc_axid", &pdata->mfc_axid); + of_property_read_u32(np, "tsmux_axid", &pdata->tsmux_axid); + of_property_read_u32(np, "fault_info2", &pdata->fault_info2); + of_property_read_u32(np, "pmmuid_shift", &pdata->pmmuid_shift); + of_property_read_u32(np, "pmmuid_mask", &pdata->pmmuid_mask); + of_property_read_u32(np, "tsmux_pmmuid", &pdata->tsmux_pmmuid); + of_property_read_u32(np, "masterid_shift", &pdata->masterid_shift); + of_property_read_u32(np, "masterid_mask", &pdata->masterid_mask); + of_property_read_u32(np, "tsmux_masterid", &pdata->tsmux_masterid); + + return 0; +} + +static int __mfc_core_register_resource(struct platform_device *pdev, + struct mfc_core *core) +{ + struct device_node *np = core->device->of_node; + struct device_node *iommu; + struct device_node *pmu; + struct resource *res; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory region resource\n"); + return -ENOENT; + } + core->mfc_mem = + request_mem_region(res->start, resource_size(res), pdev->name); + if (!core->mfc_mem) { + dev_err(&pdev->dev, "failed to get memory region\n"); + return -ENOENT; + } + core->regs_base = + ioremap(core->mfc_mem->start, resource_size(core->mfc_mem)); + if (!core->regs_base) { + dev_err(&pdev->dev, "failed to ioremap address region\n"); + goto err_ioremap; + } + + iommu = of_get_child_by_name(np, "iommu"); + if (!iommu) { + dev_err(&pdev->dev, "failed to get iommu node\n"); + goto err_ioremap_mmu0; + } + + core->sysmmu0_base = of_iomap(iommu, 0); + if (!core->sysmmu0_base) { + dev_err(&pdev->dev, + "failed to ioremap sysmmu0 address region\n"); + goto err_ioremap_mmu0; + } +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + // sysmmu bypass settings for sysmmu0_base + writel(0x00, core->sysmmu0_base + 0x00); +#endif + + core->sysmmu1_base = of_iomap(iommu, 1); + if (!core->sysmmu1_base) { + dev_dbg(&pdev->dev, "there is only one MFC sysmmu\n"); + } else { + core->has_2sysmmu = 1; +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + // sysmmu bypass settings for sysmmu1_base + writel(0x00, core->sysmmu1_base + 0x00); +#endif + } + + pmu = of_get_child_by_name(np, "pmu"); + if (pmu) { + core->pmu_base = of_iomap(pmu, 0); + if (!core->pmu_base) { + core->has_pmu = 0; + dev_err(&pdev->dev, + "failed to iomap pmu address region\n"); + goto err_ioremap_pmu; + } + core->has_pmu = 1; + } + + core->irq = platform_get_irq(pdev, 0); + if (core->irq < 0) { + dev_err(&pdev->dev, "failed to get irq\n"); + goto err_res_irq; + } + + ret = + devm_request_threaded_irq(&pdev->dev, core->irq, + mfc_core_top_half_irq, mfc_core_irq, + IRQF_ONESHOT, pdev->name, core); + if (ret) { + dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); + goto err_res_irq; + } + + return 0; + + err_res_irq: + if (core->has_pmu) + iounmap(core->pmu_base); + err_ioremap_pmu: + if (core->has_2sysmmu) { + if (core->sysmmu1_base) + iounmap(core->sysmmu1_base); + } + if (core->sysmmu0_base) + iounmap(core->sysmmu0_base); + err_ioremap_mmu0: + iounmap(core->regs_base); + err_ioremap: + release_mem_region(core->mfc_mem->start, resource_size(core->mfc_mem)); + return -ENOENT; +} + +/* MFC probe function */ +static int mfc_core_probe(struct platform_device *pdev) +{ + struct mfc_core *core; + struct mfc_dev *dev; + int ret = -ENOENT; + + dev_info(&pdev->dev, "%s is called\n", __func__); + + core = devm_kzalloc(&pdev->dev, sizeof(struct mfc_core), GFP_KERNEL); + if (!core) + return -ENOMEM; + + core->device = &pdev->dev; + + /* set core id */ + of_property_read_u32(core->device->of_node, "id", &core->id); + snprintf(core->name, sizeof(core->name), "MFC%d", core->id); + + /* register core to dev */ + dev = dev_get_drvdata(pdev->dev.parent); + dev->core[core->id] = core; + dev->num_core++; + dev->num_subsystem++; + core->dev = dev; + core->core_ops = mfc_get_core_ops(); + + core->core_pdata = devm_kzalloc(&pdev->dev, + sizeof(struct mfc_core_platdata), + GFP_KERNEL); + if (!core->core_pdata) { + ret = -ENOMEM; + goto err_pm; + } + + ret = __mfc_core_parse_dt(core->device->of_node, core); + if (ret) + goto err_pm; + + atomic_set(&core->trace_ref_log, 0); + core->mfc_trace_logging = g_mfc_core_trace_logging; + + mfc_core_pm_init(core); + ret = __mfc_core_register_resource(pdev, core); + if (ret) + goto err_res_mem; + init_waitqueue_head(&core->cmd_wq); + mfc_core_init_listable_wq_dev(core); + + platform_set_drvdata(pdev, core); + + mfc_core_init_hwlock(core); + + mfc_sched_init_core(core); + + spin_lock_init(&core->batch_lock); + +#if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) + ret = samsung_iommu_register_fault_handler(core->device, + mfc_core_sysmmu_fault_handler, + core); + if (ret) { + dev_err(&pdev->dev, + "failed to register sysmmu fault handler %d\n", ret); + ret = -EPROBE_DEFER; + goto err_sysmmu_fault_handler; + } +#endif + /* set async suspend/resume */ + device_enable_async_suspend(core->device); + + mfc_alloc_firmware(core); + + core->logging_data = devm_kzalloc(&pdev->dev, sizeof(struct mfc_debug), + GFP_KERNEL); + if (!core->logging_data) { + ret = -ENOMEM; + goto err_alloc_debug; + } +#if IS_ENABLED(CONFIG_MFC_USE_COREDUMP) + core->dbg_info.size = MFC_DUMP_BUF_SIZE; + core->dbg_info.addr = vmalloc(core->dbg_info.size); + if (!core->dbg_info.addr) + dev_err(&pdev->dev, "failed to alloc for debug buffer\n"); +#endif +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + samsung_sysmmu_activate(core->device); +#endif + mfc_core_info("%s is completed\n", core->name); + + return 0; + + err_alloc_debug: +#if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) + samsung_iommu_unregister_fault_handler(&pdev->dev); + err_sysmmu_fault_handler: +#endif + if (core->has_2sysmmu) + iounmap(core->sysmmu1_base); + iounmap(core->sysmmu0_base); + iounmap(core->regs_base); + release_mem_region(core->mfc_mem->start, resource_size(core->mfc_mem)); + err_res_mem: + mfc_core_pm_final(core); + err_pm: + return ret; +} + +/* Remove the driver */ +static void mfc_core_remove(struct platform_device *pdev) +{ + struct mfc_core *core = platform_get_drvdata(pdev); + + mfc_core_info("++%s remove\n", core->name); + + if (core->dbg_info.addr) + vfree(core->dbg_info.addr); +#if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) + samsung_iommu_unregister_fault_handler(&pdev->dev); +#endif + mfc_core_destroy_listable_wq_core(core); + + mfc_release_common_context(core); + mfc_release_firmware(core); + core->fw.status = 0; + + if (core->has_2sysmmu) + if (core->sysmmu1_base) + iounmap(core->sysmmu1_base); + if (core->sysmmu0_base) + iounmap(core->sysmmu0_base); + iounmap(core->regs_base); + release_mem_region(core->mfc_mem->start, resource_size(core->mfc_mem)); + mfc_core_pm_final(core); + + mfc_core_info("--%s remove\n", core->name); +} + +static void mfc_core_shutdown(struct platform_device *pdev) +{ + struct mfc_core *core = platform_get_drvdata(pdev); + struct mfc_dev *dev = core->dev; + int ret; + + mfc_core_info("%s core shutdown is called\n", core->name); + if (core->shutdown) { + mfc_core_info("%s core shutdown was already performed\n", + core->name); + return; + } + + mutex_lock(&dev->mfc_mutex); + if (!mfc_core_get_pwr_ref_cnt(core)) { + core->shutdown = 1; + mfc_core_info("MFC is not running\n"); + mutex_unlock(&dev->mfc_mutex); + return; + } + + ret = mfc_core_get_hwlock_dev(core); + if (ret < 0) + mfc_core_err("Failed to get hwlock\n"); + + mfc_core_risc_off(core); + core->sched->clear_all_work(core); + mfc_core_release_hwlock_dev(core); + + core->shutdown = 1; + mutex_unlock(&dev->mfc_mutex); + + mfc_core_info("%s core shutdown completed\n", core->name); +} + +#if IS_ENABLED(CONFIG_PM_SLEEP) +static int mfc_core_suspend(struct device *device) +{ + struct mfc_core *core = + platform_get_drvdata(to_platform_device(device)); + + if (!core) { + dev_err(device, "no mfc device to run\n"); + return -EINVAL; + } + + mfc_core_debug(2, "MFC suspend will be handled by main driver\n"); + + return 0; +} + +static int mfc_core_resume(struct device *device) +{ + struct mfc_core *core = + platform_get_drvdata(to_platform_device(device)); + + if (!core) { + dev_err(device, "no mfc core to run\n"); + return -EINVAL; + } + + mfc_core_debug(2, "MFC resume will be handled by main driver\n"); + + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_PM) +static int mfc_core_runtime_suspend(struct device *device) +{ + struct mfc_core *core = + platform_get_drvdata(to_platform_device(device)); + + mfc_core_debug(3, "mfc runtime suspend\n"); + + return 0; +} + +static int mfc_core_runtime_idle(struct device *dev) +{ + return 0; +} + +static int mfc_core_runtime_resume(struct device *device) +{ + struct mfc_core *core = + platform_get_drvdata(to_platform_device(device)); + + mfc_core_debug(3, "mfc runtime resume\n"); + + return 0; +} +#endif + +/* Power management */ +static const struct dev_pm_ops mfc_core_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mfc_core_suspend, mfc_core_resume) + SET_RUNTIME_PM_OPS(mfc_core_runtime_suspend, + mfc_core_runtime_resume, + mfc_core_runtime_idle) +}; + +static const struct of_device_id exynos_mfc_core_match[] = { + { + .compatible = "samsung,exynos-mfc-core", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, exynos_mfc_core_match); + +struct platform_driver mfc_core_driver = { + .probe = mfc_core_probe, + .remove = mfc_core_remove, + .shutdown = mfc_core_shutdown, + .driver = { + .name = MFC_CORE_NAME, + .owner = THIS_MODULE, + .pm = &mfc_core_pm_ops, + .of_match_table = of_match_ptr(exynos_mfc_core_match), + }, +}; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c new file mode 100644 index 000000000000..d9200bba1bb5 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_ops.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_ops.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_run.h" +#include "mfc_core_pm.h" +#include "mfc_core_sync.h" + +#include "mfc_core_hw_reg_api.h" + +#include "base/mfc_sched.h" +#include "base/mfc_buf.h" +#include "base/mfc_utils.h" +#include "base/mfc_mem.h" + +static void __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = core->dev; + + /* set MFC idle timer */ + atomic_set(&core->hw_run_bits, 0); + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_NONE); + + if (!dev->fw_date) + dev->fw_date = core->fw.date; + else if (dev->fw_date > core->fw.date) + dev->fw_date = core->fw.date; +} + +static int __mfc_wait_close_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + + if (core->state == MFCCORE_ERROR) { + mfc_info("[MSR] Couldn't close inst. It's Error state\n"); + return 0; + } + + if (core_ctx->state <= MFCINST_INIT) { + mfc_debug(2, "mfc instance didn't opend or already closed\n"); + return 0; + } + + mfc_clean_core_ctx_int_flags(core_ctx); + mfc_change_state(core_ctx, MFCINST_RETURN_INST); + core->sched->set_work(core, core_ctx); + + /* To issue the command 'CLOSE_INSTANCE' */ + if (mfc_core_just_run(core, ctx->num)) { + mfc_err("failed to run MFC, state: %d\n", core_ctx->state); + MFC_TRACE_CTX_LT("[ERR][Release] failed to run MFC, state: %d\n", core_ctx->state); + return -EIO; + } + + /* Wait until instance is returned or timeout occurred */ + ret = mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET); + if (ret == 1) { + mfc_err("failed to wait CLOSE_INSTANCE(timeout)\n"); + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET)) { + mfc_err("waited once more but failed to wait CLOSE_INSTANCE\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_CLOSE_INST); + } + } else if (ret == -1) { + mfc_err("failed to wait CLOSE_INSTANCE(err)\n"); + } + + return 0; +} + +static int __mfc_core_deinit(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + + core->sched->clear_work(core, core_ctx); + + ret = __mfc_wait_close_inst(core, ctx); + if (ret) { + mfc_err("Failed to close instance\n"); + return ret; + } + + core->num_inst--; + + /* Last normal instance */ + if (core->num_inst == 0) { + core->curr_core_ctx = ctx->num; + mfc_core_pm_clock_on(core, 0); + mfc_core_run_cache_flush(core, MFC_CACHEFLUSH, 0); + mfc_core_pm_clock_off(core, 0); + + mfc_core_change_fw_state(core, MFC_FW_INITIALIZED, 0); + + mfc_core_change_fw_state(core, MFC_FW_LOADED, 0); + } + + if (core->num_inst == 0) { + mfc_core_run_deinit_hw(core); + + mfc_debug(2, "power off\n"); + mfc_core_pm_power_off(core); + + if (core->dev->debugfs.dbg_enable) + mfc_release_dbg_info_buffer(core); + + if (core->state == MFCCORE_ERROR) { + mfc_core_change_state(core, MFCCORE_INIT); + mfc_info("[MSR] MFC-%d will be reset\n", core->id); + } + } + + return 0; +} + +static int __mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = NULL; + int ret = 0; + enum mfc_fw_status fw_status; + struct mfc_special_buf *fw_buf; + + if (core->state == MFCCORE_ERROR) { + mfc_ctx_err("MFC-%d is ERROR state\n", core->id); + return -EBUSY; + } + + core->num_inst++; + + /* Allocate memory for core context */ + core_ctx = kzalloc(sizeof(*core_ctx), GFP_KERNEL); + if (!core_ctx) { + ret = -ENOMEM; + goto err_init_inst; + } + + core_ctx->core = core; + core_ctx->ctx = ctx; + core_ctx->num = ctx->num; + core_ctx->inst_no = MFC_NO_INSTANCE_SET; + core->core_ctx[core_ctx->num] = core_ctx; + + init_waitqueue_head(&core_ctx->cmd_wq); + mfc_core_init_listable_wq_ctx(core_ctx); + core->sched->clear_work(core, core_ctx); + + if (core->num_inst == 1) { + mfc_debug(2, "it is first instance in to core-%d\n", core->id); + + mfc_debug(2, "power on\n"); + ret = mfc_core_pm_power_on(core); + if (ret) { + mfc_err("Failed block power on, ret=%d\n", ret); + goto err_power_on; + } + + if (core->dev->debugfs.dbg_enable) + mfc_alloc_dbg_info_buffer(core); + } + + /* Load and verify the FW */ + + fw_buf = &core->fw_buf; + fw_status = core->fw.status; + + if (!(fw_status & MFC_FW_LOADED)) { + ret = mfc_request_load_firmware(core, fw_buf); + if (ret) + goto err_fw_load; + } + + if (!(fw_status & MFC_FW_INITIALIZED)) { + core->curr_core_ctx = ctx->num; + core->preempt_core_ctx = MFC_NO_INSTANCE_SET; + + ret = mfc_core_run_init_hw(core); + if (ret) + goto err_init_hw; + } + + if (core->num_inst == 1) + __mfc_core_init(core, ctx); + + return 0; + +err_init_hw: + mfc_core_change_fw_state(core, MFC_FW_LOADED, 0); + +err_fw_load: + if (core->dev->debugfs.dbg_enable) + mfc_release_dbg_info_buffer(core); + if (core->num_inst == 1) { + if (mfc_core_get_pwr_ref_cnt(core)) + mfc_core_pm_power_off(core); + } +err_power_on: + core->core_ctx[ctx->num] = 0; + kfree(core->core_ctx[ctx->num]); + +err_init_inst: + core->num_inst--; + + return ret; +} + +static int mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx) +{ + int ret = 0; + + mfc_core_debug_enter(); + + ret = mfc_core_get_hwlock_dev(core); + if (ret < 0) { + mfc_core_err("Failed to get hwlock\n"); + mfc_core_err("dev.hwlock.dev = 0x%lx, bits = 0x%lx, owned_by_irq = %d, wl_count = %d, transfer_owner = %d\n", + core->hwlock.dev, core->hwlock.bits, core->hwlock.owned_by_irq, + core->hwlock.wl_count, core->hwlock.transfer_owner); + return ret; + } + + ret = __mfc_core_instance_init(core, ctx); + if (ret) + mfc_core_err("Failed to core instance init\n"); + + mfc_core_release_hwlock_dev(core); + + mfc_core_debug_leave(); + + return ret; +} + +static int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + + if (!core_ctx) { + mfc_core_err("There is no instance\n"); + return -EINVAL; + } + + core->sched->clear_work(core, core_ctx); + + ret = mfc_core_get_hwlock_ctx(core_ctx); + if (ret < 0) { + mfc_err("Failed to get hwlock\n"); + MFC_TRACE_CTX_LT("[ERR][Release] failed to get hwlock (shutdown: %d)\n", + core->shutdown); + return -EBUSY; + } + + /* If instance was initialised then return instance and free reosurces */ + ret = __mfc_core_deinit(core, ctx); + if (ret) + goto err_release_try; + + mfc_core_release_hwlock_ctx(core_ctx); + mfc_core_destroy_listable_wq_ctx(core_ctx); + + core->core_ctx[core_ctx->num] = 0; + kfree(core_ctx); + + return 0; + +err_release_try: + mfc_core_release_hwlock_ctx(core_ctx); + return ret; +} + +static const struct mfc_core_ops mfc_core_ops = { + .instance_init = mfc_core_instance_init, + .instance_deinit = mfc_core_instance_deinit, +}; + +const struct mfc_core_ops *mfc_get_core_ops(void) +{ + return &mfc_core_ops; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h new file mode 100644 index 000000000000..80647b3b165a --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_ops.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ +#ifndef __MFC_CORE_OPS_H +#define __MFC_CORE_OPS_H __FILE__ + +#include "base/mfc_common.h" + +const struct mfc_core_ops *mfc_get_core_ops(void); +#endif /* __MFC_CORE_OPS_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c new file mode 100644 index 000000000000..a2f69a064d3d --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_core_sched_prio.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_hwlock.h" +#include "mfc_core_sync.h" + +#include "base/mfc_sched.h" +#include "base/mfc_utils.h" + +static inline void __mfc_print_workbits(struct mfc_core *core, int prio, int num) +{ + int i; + + mfc_core_debug(4, "[PRIO][c:%d] prio %d\n", num, prio); + for (i = 0; i < core->total_num_prio; i++) + mfc_core_debug(4, "[PRIO] MFC-%d P[%d] bits %08lx\n", + core->id, i, core->prio_work_bits[i]); +} + +static inline void __mfc_clear_all_prio_bits(struct mfc_core *core) +{ + unsigned long flags; + int i; + + spin_lock_irqsave(&core->prio_work_lock, flags); + for (i = 0; i < core->total_num_prio; i++) + core->prio_work_bits[i] = 0; + spin_unlock_irqrestore(&core->prio_work_lock, flags); +} + +static void mfc_create_work_prio(struct mfc_core *core) +{ + int num_prio = core->dev->pdata->pbs_num_prio; + + spin_lock_init(&core->prio_work_lock); + + core->sched_type = MFC_SCHED_PRIO; + core->num_prio = num_prio ? num_prio : 1; + core->total_num_prio = core->num_prio * 2 + 2; + + __mfc_clear_all_prio_bits(core); +} + +static void mfc_init_work_prio(struct mfc_core *core) +{ + core->sched_type = MFC_SCHED_PRIO; + __mfc_clear_all_prio_bits(core); + mfc_core_debug(2, "[SCHED][PRIO] Scheduler type is PBS\n"); +} + +static void mfc_clear_all_work_prio(struct mfc_core *core) +{ + __mfc_clear_all_prio_bits(core); +} + +static void mfc_set_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + int p; + + spin_lock_irqsave(&core->prio_work_lock, flags); + + p = mfc_get_prio(core, ctx->rt, ctx->prio); + __set_bit(core_ctx->num, &core->prio_work_bits[p]); + __mfc_print_workbits(core, p, core_ctx->num); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); +} + +static void mfc_clear_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + int p; + + spin_lock_irqsave(&core->prio_work_lock, flags); + + p = mfc_get_prio(core, ctx->rt, ctx->prio); + __clear_bit(core_ctx->num, &core->prio_work_bits[p]); + __mfc_print_workbits(core, p, core_ctx->num); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); +} + +struct mfc_sched_class mfc_sched_prio = { + .create_work = mfc_create_work_prio, + .init_work = mfc_init_work_prio, + .clear_all_work = mfc_clear_all_work_prio, + .set_work = mfc_set_work_prio, + .clear_work = mfc_clear_work_prio, +}; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c new file mode 100644 index 000000000000..a25a05642cf2 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_rm.c File + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_rm.h" + +#include "mfc_core_hwlock.h" +#include "mfc_core_intlock.h" +#include "mfc_core_hw_reg_api.h" +#include "mfc_core_pm.h" + +#include "base/mfc_buf.h" +#include "base/mfc_utils.h" +#include "base/mfc_mem.h" + +int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core; + int i, ret; + + mfc_ctx_debug_enter(); + + mfc_get_corelock_ctx(ctx); + + /* + * The FW memory for all cores is allocated in advance. + * (Only once at first time) + * Because FW base address should be the lowest address + * than all DVA that FW approaches. + */ + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + mfc_ctx_err("[RM] There is no MFC-%d\n", i); + continue; + } + + if (!(core->fw.status & MFC_FW_ALLOC)) { + ret = mfc_alloc_firmware(core); + if (ret) + goto err_inst_init; + } + + if (!(core->fw.status & MFC_CTX_ALLOC)) { + ret = mfc_alloc_common_context(core); + if (ret) + goto err_inst_init; + } + } + + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; + if (ctx->type == MFCINST_DECODER) + ctx->op_core_num[MFC_CORE_MAIN] = MFC_DEC_DEFAULT_CORE; + else + ctx->op_core_num[MFC_CORE_MAIN] = MFC_ENC_DEFAULT_CORE; + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + ret = -EINVAL; + goto err_inst_init; + } + + mfc_ctx_debug(2, "[RM] init instance core-%d\n", + ctx->op_core_num[MFC_CORE_MAIN]); + ret = core->core_ops->instance_init(core, ctx); + if (ret) { + ctx->op_core_num[MFC_CORE_MAIN] = MFC_CORE_INVALID; + mfc_ctx_err("[RM] Failed to init\n"); + } + +err_inst_init: + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); + + return ret; +} + +int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core = NULL, *subcore; + int i, ret = 0; + + mfc_ctx_debug_enter(); + + mfc_get_corelock_ctx(ctx); + + /* reset original stream mode */ + mutex_lock(&ctx->op_mode_mutex); + if (IS_SWITCH_SINGLE_MODE(ctx)) { + mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); + mfc_change_op_mode(ctx, ctx->stream_op_mode); + } + mutex_unlock(&ctx->op_mode_mutex); + + if (IS_TWO_MODE1(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) + mfc_ctx_err("[RM] There is no sub core for clock off\n"); + else + mfc_core_pm_clock_off(subcore, 0); + } + + for (i = (MFC_CORE_TYPE_NUM - 1); i >= 0; i--) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + continue; + + core = dev->core[ctx->op_core_num[i]]; + if (!core) { + mfc_ctx_err("[RM] There is no core[%d]\n", + ctx->op_core_num[i]); + ret = -EINVAL; + goto err_inst_deinit; + } + + mfc_core_debug(2, "[RM] core%d will be deinit, ctx[%d]\n", + i, ctx->num); + ret = core->core_ops->instance_deinit(core, ctx); + if (ret) + mfc_core_err("[RM] Failed to deinit\n"); + } + + clear_bit(ctx->num, &dev->multi_core_inst_bits); + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; + +err_inst_deinit: + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); + + return ret; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h new file mode 100644 index 000000000000..8f9e7494057e --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_rm.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_RM_H +#define __MFC_RM_H __FILE__ + +#include "mfc_core_sync.h" + +#define MFC_RM_LOAD_DELETE 0 +#define MFC_RM_LOAD_ADD 1 +#define MFC_RM_LOAD_DELETE_UPDATE 2 + +static inline struct mfc_core *mfc_get_main_core(struct mfc_dev *dev, + struct mfc_ctx *ctx) +{ + if (ctx->op_core_num[MFC_CORE_MAIN] == MFC_CORE_INVALID) + return NULL; + + return dev->core[ctx->op_core_num[MFC_CORE_MAIN]]; +} + +static inline struct mfc_core *mfc_get_sub_core(struct mfc_dev *dev, + struct mfc_ctx *ctx) +{ + if (ctx->op_core_num[MFC_CORE_SUB] == MFC_CORE_INVALID) + return NULL; + + return dev->core[ctx->op_core_num[MFC_CORE_SUB]]; +} + +static inline void mfc_rm_set_core_num(struct mfc_ctx *ctx, int main_core_num) +{ + ctx->op_core_num[MFC_CORE_MAIN] = main_core_num; + + if (main_core_num == MFC_DEC_DEFAULT_CORE) + ctx->op_core_num[MFC_CORE_SUB] = MFC_SURPLUS_CORE; + else + ctx->op_core_num[MFC_CORE_SUB] = MFC_DEC_DEFAULT_CORE; + + mfc_ctx_debug(2, "[RM] main core %d, sub core %d\n", + ctx->op_core_num[MFC_CORE_MAIN], + ctx->op_core_num[MFC_CORE_SUB]); +} + +/* core ops */ +int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx); +int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx); +#endif /* __MFC_RM_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support 2025-09-30 4:03 ` [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support Himanshu Dewangan @ 2025-09-30 5:54 ` Krzysztof Kozlowski 2025-09-30 15:46 ` Marek Szyprowski 0 siblings, 1 reply; 38+ messages in thread From: Krzysztof Kozlowski @ 2025-09-30 5:54 UTC (permalink / raw) To: Himanshu Dewangan Cc: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan <h.dewangan@samsung.com> wrote: > > From: Nagaraju Siddineni <nagaraju.s@samsung.com> > > Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung > Exynos MFC driver that supports firmware version 13 and later. > Extend the top‑level Samsung platform Kconfig to disable the legacy > S5P‑MFC driver when its firmware version is > v12 and to select the > new Exynos‑MFC driver only when VIDEO_SAMSUNG_S5P_MFC is not enabled. > > Add exynos-mfc Kconfig and Makefile for probe functionality and creation > of decoder and encoder device files by registering the driver object > exynos_mfc.o and other relevant source files. > > Provide header files mfc_core_ops.h and mfc_rm.h containing core > operation prototypes, resource‑manager helpers, > and core‑selection utilities. > > Add a configurable option MFC_USE_COREDUMP to enable core‑dump > support for debugging MFC errors. > > These changes bring support for newer Exynos‑based MFC hardware, > cleanly separate it from the legacy S5P‑MFC driver, and lay the > groundwork for future feature development and debugging. > No, NAK. Existing driver is well tested and already used on newest Exynos SoC, so all this new driver is exactly how you should not work in upstream. You need to integrate into existing driver. Samsung received this review multiple times already. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support 2025-09-30 5:54 ` Krzysztof Kozlowski @ 2025-09-30 15:46 ` Marek Szyprowski 2025-09-30 22:59 ` Krzysztof Kozlowski 0 siblings, 1 reply; 38+ messages in thread From: Marek Szyprowski @ 2025-09-30 15:46 UTC (permalink / raw) To: Krzysztof Kozlowski, Himanshu Dewangan Cc: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig Hi Krzysztof, On 30.09.2025 07:54, Krzysztof Kozlowski wrote: > On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan <h.dewangan@samsung.com> wrote: >> From: Nagaraju Siddineni <nagaraju.s@samsung.com> >> >> Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung >> Exynos MFC driver that supports firmware version 13 and later. >> Extend the top‑level Samsung platform Kconfig to disable the legacy >> S5P‑MFC driver when its firmware version is > v12 and to select the >> new Exynos‑MFC driver only when VIDEO_SAMSUNG_S5P_MFC is not enabled. >> >> Add exynos-mfc Kconfig and Makefile for probe functionality and creation >> of decoder and encoder device files by registering the driver object >> exynos_mfc.o and other relevant source files. >> >> Provide header files mfc_core_ops.h and mfc_rm.h containing core >> operation prototypes, resource‑manager helpers, >> and core‑selection utilities. >> >> Add a configurable option MFC_USE_COREDUMP to enable core‑dump >> support for debugging MFC errors. >> >> These changes bring support for newer Exynos‑based MFC hardware, >> cleanly separate it from the legacy S5P‑MFC driver, and lay the >> groundwork for future feature development and debugging. >> > No, NAK. Existing driver is well tested and already used on newest > Exynos SoC, so all this new driver is exactly how you should not work > in upstream. You need to integrate into existing driver. > > Samsung received this review multiple times already. Please don't be so categorical. The MFC hardware evolved quite a bit from the ancient times of S5PV210 SoC, when s5p-mfc driver was designed. The feature list of the new hardware hardly matches those and I really don't see the reason for forcing support for so different hardware in a single driver. Sometimes it is easier just to have 2 separate drivers if the common part is just the acronym in the hardware block name... Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support 2025-09-30 15:46 ` Marek Szyprowski @ 2025-09-30 22:59 ` Krzysztof Kozlowski 2025-09-30 23:06 ` Krzysztof Kozlowski 0 siblings, 1 reply; 38+ messages in thread From: Krzysztof Kozlowski @ 2025-09-30 22:59 UTC (permalink / raw) To: Marek Szyprowski Cc: Himanshu Dewangan, mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig On Wed, 1 Oct 2025 at 00:46, Marek Szyprowski <m.szyprowski@samsung.com> wrote: > > Hi Krzysztof, > > On 30.09.2025 07:54, Krzysztof Kozlowski wrote: > > On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan <h.dewangan@samsung.com> wrote: > >> From: Nagaraju Siddineni <nagaraju.s@samsung.com> > >> > >> Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung > >> Exynos MFC driver that supports firmware version 13 and later. > >> Extend the top‑level Samsung platform Kconfig to disable the legacy > >> S5P‑MFC driver when its firmware version is > v12 and to select the > >> new Exynos‑MFC driver only when VIDEO_SAMSUNG_S5P_MFC is not enabled. > >> > >> Add exynos-mfc Kconfig and Makefile for probe functionality and creation > >> of decoder and encoder device files by registering the driver object > >> exynos_mfc.o and other relevant source files. > >> > >> Provide header files mfc_core_ops.h and mfc_rm.h containing core > >> operation prototypes, resource‑manager helpers, > >> and core‑selection utilities. > >> > >> Add a configurable option MFC_USE_COREDUMP to enable core‑dump > >> support for debugging MFC errors. > >> > >> These changes bring support for newer Exynos‑based MFC hardware, > >> cleanly separate it from the legacy S5P‑MFC driver, and lay the > >> groundwork for future feature development and debugging. > >> > > No, NAK. Existing driver is well tested and already used on newest > > Exynos SoC, so all this new driver is exactly how you should not work > > in upstream. You need to integrate into existing driver. > > > > Samsung received this review multiple times already. > > Please don't be so categorical. The MFC hardware evolved quite a bit > from the ancient times of S5PV210 SoC, when s5p-mfc driver was designed. > The feature list of the new hardware hardly matches those and I really > don't see the reason for forcing support for so different hardware in a > single driver. Sometimes it is easier just to have 2 separate drivers if > the common part is just the acronym in the hardware block name... > I know it is easier for Samsung to write new driver, but this should answer to - why the maintainers and the community would like to maintain two drivers. Sure, make a case why we would like to take this code. The easiest argument here why we wouldn't is: new vendor downstream code means replicating all known issues, old coding style, everything which we already fixed and changed. ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support 2025-09-30 22:59 ` Krzysztof Kozlowski @ 2025-09-30 23:06 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2025-09-30 23:06 UTC (permalink / raw) To: Marek Szyprowski Cc: Himanshu Dewangan, mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig On Wed, 1 Oct 2025 at 07:59, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Wed, 1 Oct 2025 at 00:46, Marek Szyprowski <m.szyprowski@samsung.com> wrote: > > > > Hi Krzysztof, > > > > On 30.09.2025 07:54, Krzysztof Kozlowski wrote: > > > On Tue, 30 Sept 2025 at 12:56, Himanshu Dewangan <h.dewangan@samsung.com> wrote: > > >> From: Nagaraju Siddineni <nagaraju.s@samsung.com> > > >> > > >> Introduce a new Kconfig entry VIDEO_EXYNOS_MFC for the Samsung > > >> Exynos MFC driver that supports firmware version 13 and later. > > >> Extend the top‑level Samsung platform Kconfig to disable the legacy > > >> S5P‑MFC driver when its firmware version is > v12 and to select the > > >> new Exynos‑MFC driver only when VIDEO_SAMSUNG_S5P_MFC is not enabled. > > >> > > >> Add exynos-mfc Kconfig and Makefile for probe functionality and creation > > >> of decoder and encoder device files by registering the driver object > > >> exynos_mfc.o and other relevant source files. > > >> > > >> Provide header files mfc_core_ops.h and mfc_rm.h containing core > > >> operation prototypes, resource‑manager helpers, > > >> and core‑selection utilities. > > >> > > >> Add a configurable option MFC_USE_COREDUMP to enable core‑dump > > >> support for debugging MFC errors. > > >> > > >> These changes bring support for newer Exynos‑based MFC hardware, > > >> cleanly separate it from the legacy S5P‑MFC driver, and lay the > > >> groundwork for future feature development and debugging. > > >> > > > No, NAK. Existing driver is well tested and already used on newest > > > Exynos SoC, so all this new driver is exactly how you should not work > > > in upstream. You need to integrate into existing driver. > > > > > > Samsung received this review multiple times already. > > > > Please don't be so categorical. The MFC hardware evolved quite a bit > > from the ancient times of S5PV210 SoC, when s5p-mfc driver was designed. > > The feature list of the new hardware hardly matches those and I really > > don't see the reason for forcing support for so different hardware in a > > single driver. Sometimes it is easier just to have 2 separate drivers if > > the common part is just the acronym in the hardware block name... > > > > I know it is easier for Samsung to write new driver, but this should > answer to - why the maintainers and the community would like to > maintain two drivers. Sure, make a case why we would like to take this > code. > > The easiest argument here why we wouldn't is: new vendor downstream > code means replicating all known issues, old coding style, everything > which we already fixed and changed. And 15 second look at one of the patches already confirmed this: replicating downstream issue - undocumented DT ABI not following current style, code relying on some other downstream drivers. 15 seconds was enough to find it. ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035557epcas5p2efa9fa41298b8a9aabb46e5fac70d49e@epcas5p2.samsung.com>]
* [PATCH 09/29] media: mfc: Add bus‑devfreq, QoS, multi‑view and control infrastructure [not found] ` <CGME20250930035557epcas5p2efa9fa41298b8a9aabb46e5fac70d49e@epcas5p2.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Optional bus‑devfreq support (CONFIG_MFC_USE_BUS_DEVFREQ). - New control framework (mfc_ctrl_type, mfc_ctrl_mode, ops structs). - QoS and per‑context/core power‑clock handling. - Multi‑view / depth‑map support with related buffers and constants. - Added helper macros (mfc_macros.h) and extra pixel formats. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_data_struct.h | 659 +++++++++++++++++- .../samsung/exynos-mfc/base/mfc_format.h | 132 ++++ .../samsung/exynos-mfc/base/mfc_macros.h | 95 +++ 3 files changed, 882 insertions(+), 4 deletions(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h index 59fef39095d2..34b4b13b4f01 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h @@ -12,6 +12,13 @@ #ifndef __MFC_DATA_STRUCT_H #define __MFC_DATA_STRUCT_H __FILE__ +#if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) || IS_ENABLED(CONFIG_EXYNOS_PM_QOS_MODULE) +#define CONFIG_MFC_USE_BUS_DEVFREQ +#endif + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ +#include <soc/samsung/exynos_pm_qos.h> +#endif #include <linux/videodev2.h> #include <linux/cma.h> #include <linux/genalloc.h> @@ -24,6 +31,7 @@ #include "mfc_media.h" /* DEBUGFS */ +#define MFC_DEFAULT_MEMLOG_LEVEL 0x7 #define MFC_DEFAULT_LOGGING_OPTION 0x7 #define MFC_NUM_CORE 2 @@ -36,6 +44,9 @@ #define MFC_SFR_LOGGING_COUNT_SET1 28 #define MFC_SFR_LOGGING_COUNT_SET2 32 #define MFC_LOGGING_DATA_SIZE 950 +#define MFC_MAX_DEFAULT_PARAM 100 +#define MFC_NUM_EXTRA_DPB 5 +#define MFC_MAX_MB_TABLE 30 /* the number of priority is 2N(num of OPP) + 2 */ #define MFC_MAX_PRIO 12 /* The number of display DRC max frames that can occur continuously in NAL_Q */ @@ -60,6 +71,14 @@ #define MFC_FMT_FLAG_MULTI_VIEW 0x0010 #define MFC_FMT_FLAG_DEPTH_MAP 0x0020 +/* MFC Multi-View */ +#define MFC_NUM_FD_DEPTH_MAP 1 +#define MFC_NUM_MULTI_VIEW 2 +#define MFC_NUM_FD_SUB_VIEW_META 1 + +/* MFC meminfo */ +#define MFC_MEMINFO_MAX_NUM 10 + #define MFC_NUM_SPECIAL_BUF_NAME 25 #define BANK_L_CTX 0 @@ -102,10 +121,59 @@ enum mfc_inst_type { enum mfc_inst_state { MFCINST_FREE = 0, MFCINST_INIT = 100, + MFCINST_GOT_INST, + MFCINST_HEAD_PARSED, + MFCINST_RUNNING_BUF_FULL, MFCINST_RUNNING, + MFCINST_FINISHING, MFCINST_RETURN_INST, MFCINST_ERROR, - MFCINST_ABORT + MFCINST_ABORT, + MFCINST_RES_CHANGE_INIT, + MFCINST_RES_CHANGE_FLUSH, + MFCINST_RES_CHANGE_FLUSH_FINISHED, + MFCINST_RES_CHANGE_END, + MFCINST_FINISHED, + MFCINST_ABORT_INST, + MFCINST_DPB_FLUSHING, + MFCINST_MOVE_INST, + MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET, +}; + +enum mfc_inst_state_query { + EQUAL = 0, + BIGGER, + SMALLER, + EQUAL_BIGGER, + EQUAL_SMALLER, + EQUAL_OR, +}; + +/** + * enum mfc_queue_state - The state of buffer queue. + */ +enum mfc_queue_state { + QUEUE_FREE = 0, + QUEUE_BUFS_REQUESTED, + QUEUE_BUFS_QUERIED, + QUEUE_BUFS_MMAPED, +}; + +enum mfc_dec_wait_state { + WAIT_NONE = 0, + WAIT_G_FMT = BIT(0), + WAIT_STOP = BIT(1), +}; + +/** + * enum mfc_check_state - The state for user notification + */ +enum mfc_check_state { + MFCSTATE_PROCESSING = 0, + MFCSTATE_DEC_RES_DETECT, + MFCSTATE_DEC_TERMINATING, + MFCSTATE_ENC_NO_OUTPUT, + MFCSTATE_DEC_S3D_REALLOC, }; enum mfc_buf_usage_type { @@ -116,6 +184,54 @@ enum mfc_buf_usage_type { MFCBUF_DRM_FW, }; +enum mfc_buf_process_type { + MFCBUFPROC_DEFAULT = 0x0, + MFCBUFPROC_COPY = BIT(0), + MFCBUFPROC_SHARE = BIT(1), + MFCBUFPROC_META = BIT(2), + MFCBUFPROC_ANBSHARE = BIT(3), + MFCBUFPROC_ANBSHARE_NV12L = BIT(4), +}; + +enum mfc_ctrl_type { + MFC_CTRL_TYPE_GET_SRC = 0x1, + MFC_CTRL_TYPE_GET_DST = 0x2, + MFC_CTRL_TYPE_SET_SRC = 0x4, + MFC_CTRL_TYPE_SET_DST = 0x8, +}; + +enum mfc_ctrl_mode { + MFC_CTRL_MODE_NONE = 0x0, + MFC_CTRL_MODE_SFR = 0x1, +}; + +enum mfc_mb_flag { + /* Driver set to user when DST DQbuf */ + MFC_FLAG_HDR_CONTENT_LIGHT = 0, + MFC_FLAG_HDR_DISPLAY_COLOUR = 1, + MFC_FLAG_HDR_MAXTIX_COEFF = 2, + MFC_FLAG_HDR_COLOUR_DESC = 3, + MFC_FLAG_HDR_VIDEO_SIGNAL_TYPE = 4, + MFC_FLAG_BLACKBAR_DETECT = 5, + MFC_FLAG_HDR_PLUS = 6, + MFC_FLAG_DISP_RES_CHANGE = 7, + MFC_FLAG_UNCOMP = 8, + MFC_FLAG_FRAMERATE_CH = 9, + MFC_FLAG_SYNC_FRAME = 10, + MFC_FLAG_AV1_FILM_GRAIN = 11, + MFC_FLAG_MULTIFRAME = 12, + MFC_FLAG_RIGHT_IS_MAIN_VIEW = 13, + /* Driver set to user when SRC DQbuf */ + MFC_FLAG_CONSUMED_ONLY = 15, + /* User set to driver when SRC Qbuf */ + MFC_FLAG_ENC_SRC_VOTF = 26, + MFC_FLAG_ENC_SRC_FAKE = 27, + MFC_FLAG_ENC_SRC_UNCOMP = 28, + MFC_FLAG_CSD = 29, + MFC_FLAG_EMPTY_DATA = 30, + MFC_FLAG_LAST_FRAME = 31, +}; + enum mfc_frame_error_type { MFC_ERR_FRAME_NO_ERR = 0, MFC_ERR_FRAME_CONCEALMENT = 1, @@ -152,6 +268,31 @@ enum mfc_debug_cause { MFC_CAUSE_FAIL_DPB_FLUSH = 12, MFC_CAUSE_FAIL_CACHE_FLUSH = 13, MFC_CAUSE_FAIL_MOVE_INST = 14, + /* last information */ + MFC_LAST_INFO_BLACK_BAR = 26, + MFC_LAST_INFO_NAL_QUEUE = 27, + MFC_LAST_INFO_CLOCK = 28, + MFC_LAST_INFO_POWER = 29, + MFC_LAST_INFO_SHUTDOWN = 30, + MFC_LAST_INFO_DRM = 31, +}; + +enum mfc_request_work { + MFC_WORK_BUTLER = 0x1, + MFC_WORK_TRY = 0x2, +}; + +enum mfc_qos_control { + MFC_QOS_ON = 0x1, + MFC_QOS_OFF = 0x2, + MFC_QOS_TRIGGER = 0x3, +}; + +enum mfc_ts_type { + MFC_TS_SRC = 0x1, + MFC_TS_DST_Q = 0x2, + MFC_TS_SRC_Q = 0x3, + MFC_TS_DST_DQ = 0x4, }; enum mfc_core_type { @@ -200,6 +341,13 @@ enum mfc_real_time { MFC_RT_UNDEFINED = 4, }; +enum mfc_hwapg_status { + MFC_HWAPG_CLEAR = 0, + MFC_HWAPG_ENABLE = 1, + MFC_HWAPG_HOST_SET = 2, + MFC_HWAPG_HOST_CLEAR = 3, +}; + enum mfc_sched_type { MFC_SCHED_RR = 0, MFC_SCHED_PRIO = 1, @@ -236,6 +384,7 @@ struct mfc_debug { u8 power_cnt; u8 clock_cnt; /* for decoder only */ + u64 dynamic_used; u32 last_src_addr; u32 last_dst_addr[MFC_MAX_PLANES]; /* total logging data */ @@ -268,6 +417,7 @@ struct mfc_buf { unsigned char *vir_addr[MFC_MAX_PLANES]; u32 flag; unsigned long i_ino; + int select_view; }; struct mfc_buf_queue { @@ -275,6 +425,12 @@ struct mfc_buf_queue { unsigned int count; }; +struct mfc_bits { + unsigned long bits; + /* protection */ + spinlock_t lock; +}; + struct mfc_hwlock { struct list_head waiting_list; unsigned int wl_count; @@ -307,9 +463,11 @@ struct mfc_core_intlock { struct mfc_core_lock { int cnt; + int migrate; /* protection */ spinlock_t lock; wait_queue_head_t wq; + wait_queue_head_t migrate_wq; }; struct mfc_pm { @@ -344,6 +502,7 @@ struct mfc_fw { struct mfc_ctx_buf_size { size_t dev_ctx; + size_t h264_dec_ctx; size_t dbg_info_buf; }; @@ -487,6 +646,7 @@ struct mfc_debugfs { unsigned int sfr_dump; unsigned int logging_option; unsigned int feature_option; + unsigned int core_balance; unsigned int sched_perf_disable; unsigned int sched_type; }; @@ -524,6 +684,74 @@ struct mfc_mem { size_t size; }; +enum mfc_meminfo_type { + MFC_MEMINFO_FW = 0, + MFC_MEMINFO_INTERNAL = 1, + MFC_MEMINFO_INPUT = 2, + MFC_MEMINFO_OUTPUT = 3, + MFC_MEMINFO_CTX_ALL = 4, + MFC_MEMINFO_CTX_MAX = 5, + MFC_MEMINFO_DEV_ALL = 6, +}; + +struct mfc_meminfo { + enum mfc_meminfo_type type; + const char *name; + unsigned int count; + size_t size; + size_t total; +}; + +struct mfc_bw_data { + unsigned int peak; + unsigned int read; + unsigned int write; +}; + +struct mfc_bw_info { + struct mfc_bw_data bw_dec_h264; +}; + +/* + * threshold_mb - threshold of total MB(macroblock) count + * Total MB count can be calculated by + * (MB of width) * (MB of height) * fps + */ +struct mfc_qos { + unsigned int threshold_mb; + unsigned int freq_mfc; + unsigned int freq_int; + unsigned int freq_mif; + unsigned int mo_value; + unsigned int time_fw; + unsigned int bts_scen_idx; + const char *name; +}; + +struct mfc_qos_boost { + unsigned int num_cluster; + unsigned int num_cpu[MAX_NUM_CLUSTER]; + unsigned int freq_mfc; + unsigned int freq_int; + unsigned int freq_mif; + unsigned int freq_cluster[MAX_NUM_CLUSTER]; + unsigned int bts_scen_idx; + const char *name; +}; + +struct mfc_qos_ctrl { + unsigned int idx; + unsigned int table_type; + unsigned int mfc_freq; +}; + +struct mfc_qos_weight { + unsigned int weight_h264_hevc; + unsigned int weight_3plane; + unsigned int weight_num_of_tile; + unsigned int weight_mbaff; +}; + struct mfc_feature { unsigned int support; unsigned int version; @@ -537,25 +765,58 @@ struct mfc_resource { struct mfc_platdata { /* Debug mode */ unsigned int debug_mode; + unsigned int stride_align; + unsigned int stride_type; + unsigned int stream_buf_limit; + unsigned int support_8K_cavlc; + /* Formats */ + unsigned int support_10bit; + unsigned int support_422; + /* Resolution */ + unsigned int support_check_res; + + /* error type for sync_point display */ + unsigned int display_err_type; + /* output buffer Q framerate */ + unsigned int display_framerate; /* Resource */ struct mfc_resource mfc_resource[MFC_MAX_CODEC_TYPE]; /* Features */ + struct mfc_feature skype; + struct mfc_feature black_bar; + struct mfc_feature color_aspect_dec; + struct mfc_feature static_info_dec; + struct mfc_feature vp9_stride_align; struct mfc_feature mem_clear; struct mfc_feature wait_fw_status; + struct mfc_feature hevc_pic_output_flag; + + struct mfc_bw_info mfc_bw_info; + unsigned int dynamic_weight; + struct mfc_qos_weight qos_weight; const char *fw_name; unsigned int fw_mem_size; unsigned int reserved_start; unsigned int dma_bit_mask; unsigned int ip_ver; + int num_mfc_freq; + unsigned int mfc_freqs[MAX_NUM_MFC_FREQ]; + unsigned int core_balance; unsigned int iova_threshold; + unsigned int idle_clk_ctrl; + unsigned int qos_ctrl_level; unsigned int memlog_size; + unsigned int memlog_sfr_size; + + unsigned int reg_h264_loop_filter_disable; unsigned int scheduler; unsigned int pbs_num_prio; enum mfc_hwacg_type support_hwacg; + unsigned int support_mv_hevc; }; struct mfc_core_platdata { @@ -575,6 +836,36 @@ struct mfc_core_platdata { unsigned int masterid_shift; unsigned int masterid_mask; unsigned int tsmux_masterid; + /* QoS */ + unsigned int num_default_qos_steps; + unsigned int max_mb; + unsigned int max_hw_mb; + unsigned int mfc_freq_control; + unsigned int mo_control; + unsigned int bw_control; + unsigned int pm_qos_id; + unsigned int mfc_bw_index; + struct mfc_qos *default_qos_table; + struct mfc_qos *encoder_qos_table; + struct mfc_qos_boost *qos_boost_table; +}; + +struct mfc_perf { + void __iomem *regs_base0; + void __iomem *regs_base1; + + struct timespec64 begin; + struct timespec64 end; + + int new_start; + int count; + int drv_margin; + unsigned int latency; +}; + +struct mfc_dump_ops { + void (*dump_info_context)(struct mfc_dev *dev); + void (*dump_and_stop_debug_mode)(struct mfc_dev *dev); }; struct mfc_dev_memlog { @@ -618,14 +909,17 @@ struct mfc_dev { /* protection */ struct mutex mfc_mutex; + /* protection */ + struct mutex mfc_migrate_mutex; struct mfc_ctx *ctx[MFC_NUM_CONTEXTS]; struct mfc_ctx *move_ctx[MFC_NUM_CONTEXTS]; dma_addr_t dma_base[BANK_NUM]; - + int move_ctx_cnt; struct list_head ctx_list; /* protection */ spinlock_t ctx_list_lock; + unsigned int core_balance; atomic_t queued_bits; /* protection */ @@ -641,14 +935,45 @@ struct mfc_dev { /* Debugfs and dump */ struct mfc_debugfs debugfs; + struct mfc_dump_ops *dump_ops; + + /* Instance migration worker */ + struct workqueue_struct *migration_wq; + struct work_struct migration_work; + + /* Butler */ + struct workqueue_struct *butler_wq; + struct work_struct butler_work; + + /* Lazy unmap disable */ + int skip_lazy_unmap; + + int tmu_fps; + + int max_kbps; + + /* Reg test */ + char *reg_buf; + unsigned int *reg_val; + unsigned int reg_cnt; + struct mfc_meminfo meminfo[MFC_MEMINFO_DEV_ALL + 1]; struct mfc_dev_memlog memlog; + const struct mfc_votf_ops *votf_ops; }; struct mfc_core_ops { int (*instance_init)(struct mfc_core *core, struct mfc_ctx *ctx); int (*instance_deinit)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_open)(struct mfc_core *core, struct mfc_ctx *ctx); + void (*instance_cache_flush)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_move_to)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_move_from)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*request_work)(struct mfc_core *core, enum mfc_request_work work, struct mfc_ctx *ctx); + /* for DEC */ + void (*instance_dpb_flush)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_init_buf)(struct mfc_core *core, struct mfc_ctx *ctx); }; struct dump_info { @@ -693,6 +1018,7 @@ struct mfc_core { /* Power and Clock */ atomic_t clk_ref; struct mfc_pm pm; + struct mfc_perf perf; bool continue_clock_on; bool sleep; bool shutdown; @@ -725,13 +1051,17 @@ struct mfc_core { int next_ctx_idx; /* HW lock */ + struct mfc_bits work_bits; struct mfc_hwlock hwlock; struct mfc_listable_wq hwlock_wq; wait_queue_head_t cmd_wq; + struct mfc_core_dump_ops *dump_ops; + /* batch mode */ int batch_enable; int batch_index; + enum mfc_hwapg_status hwapg_status; /* protection */ spinlock_t batch_lock; @@ -748,10 +1078,20 @@ struct mfc_core { int cache_flush_flag; int last_cmd_has_cache_flush; + /* Butler */ + struct workqueue_struct *butler_wq; + struct work_struct butler_work; + /* QoS */ struct list_head qos_queue; atomic_t qos_req_cur; - +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + struct exynos_pm_qos_request qos_req_mfc_noidle; + struct exynos_pm_qos_request qos_req_mfc; + struct exynos_pm_qos_request qos_req_int; + struct exynos_pm_qos_request qos_req_mif; + struct freq_qos_request qos_req_cluster[MAX_NUM_CLUSTER]; +#endif /* protection */ struct mutex qos_mutex; int mfc_freq_by_bps; @@ -760,6 +1100,14 @@ struct mfc_core { unsigned long total_mb; unsigned int cpu_boost_enable; + /* QoS control depending on MFC H/W run */ + struct workqueue_struct *qos_ctrl_wq; + struct work_struct qos_ctrl_work; + struct mfc_qos_ctrl qos_ctrl[MAX_NUM_QOS_DYNAMIC]; + unsigned int qos_ctrl_last_idx; + atomic_t qos_ctrl_cnt; + /* protection */ + struct mutex pm_qos_mutex; /* Logging trace data */ atomic_t trace_ref_log; struct _mfc_trace_logging *mfc_trace_logging; @@ -773,6 +1121,10 @@ struct mfc_core { struct dump_info dbg_info; /* Debug */ + char *reg_buf; + unsigned int *reg_val; + unsigned int reg_cnt; + struct mfc_meminfo meminfo[MFC_MEMINFO_DEV_ALL + 1]; struct mfc_core_memlog memlog; }; @@ -783,6 +1135,7 @@ struct mfc_ctx_ctrl_val { struct mfc_ctx_ctrl { struct list_head list; + enum mfc_ctrl_type type; unsigned int id; unsigned int addr; struct mfc_ctx_ctrl_val set; @@ -792,6 +1145,7 @@ struct mfc_ctx_ctrl { struct mfc_buf_ctrl { struct list_head list; unsigned int id; + enum mfc_ctrl_type type; int has_new; int val; unsigned int old_val; /* only for MFC_CTRL_TYPE_SET */ @@ -808,6 +1162,7 @@ struct mfc_buf_ctrl { }; struct mfc_ctrl_cfg { + enum mfc_ctrl_type type; unsigned int id; unsigned int is_volatile; /* only for MFC_CTRL_TYPE_SET */ unsigned int mode; @@ -819,6 +1174,46 @@ struct mfc_ctrl_cfg { unsigned int flag_shft; /* only for MFC_CTRL_TYPE_SET */ }; +/* per buffer control */ +extern struct mfc_ctrls_ops mfc_ctrls_ops; +struct mfc_ctrls_ops { + void (*cleanup_ctx_ctrls)(struct mfc_ctx *ctx); + int (*init_ctx_ctrls)(struct mfc_ctx *ctx); + void (*reset_buf_ctrls)(struct list_head *head); + int (*cleanup_buf_ctrls)(struct mfc_ctx *ctx, enum mfc_ctrl_type type, unsigned int index); + int (*init_buf_ctrls)(struct mfc_ctx *ctx, enum mfc_ctrl_type type, unsigned int index); + void (*to_buf_ctrls)(struct mfc_ctx *ctx, struct list_head *head); + void (*to_ctx_ctrls)(struct mfc_ctx *ctx, struct list_head *head); + int (*get_buf_ctrl_val)(struct mfc_ctx *ctx, struct list_head *head, unsigned int id); + void (*update_buf_val)(struct mfc_ctx *ctx, struct list_head *head, + unsigned int id, int value); +}; + +extern struct mfc_bufs_ops mfc_bufs_ops; +struct mfc_bufs_ops { + int (*core_set_buf_ctrls)(struct mfc_core *core, + struct mfc_ctx *ctx, struct list_head *head); + int (*core_get_buf_ctrls)(struct mfc_core *core, + struct mfc_ctx *ctx, struct list_head *head); + int (*core_recover_buf_ctrls)(struct mfc_core *core, + struct mfc_ctx *ctx, struct list_head *head); + int (*core_restore_buf_ctrls)(struct mfc_ctx *ctx, struct list_head *head); +}; + +struct stored_dpb_info { + int fd[MFC_MAX_PLANES]; +}; + +struct dec_dpb_ref_info { + int index; + struct stored_dpb_info dpb[MFC_MAX_BUFFERS]; +}; + +struct temporal_layer_info { + unsigned int temporal_layer_count; + unsigned int temporal_layer_bitrate[VIDEO_MAX_TEMPORAL_LAYERS]; +}; + struct mfc_user_shared_handle { int fd; struct dma_buf *dma_buf; @@ -835,6 +1230,35 @@ struct mfc_raw_info { unsigned int total_plane_size; }; +struct mfc_timestamp { + struct list_head list; + struct timespec64 timestamp; + int index; + int interval; +}; + +struct mfc_ts_control { + struct mfc_timestamp ts_array[MAX_TIME_INDEX]; + int ts_interval_array[MAX_TIME_INDEX]; + struct list_head ts_list; + int ts_count; + int ts_is_full; + int ts_last_interval; + /* protection */ + spinlock_t ts_lock; +}; + +struct mfc_bitrate { + struct list_head list; + int bytesused; +}; + +struct mfc_mb_control { + struct list_head list; + unsigned long mb_per_sec; + unsigned int fps; +}; + struct dpb_table { dma_addr_t addr[MFC_MAX_PLANES]; phys_addr_t paddr; @@ -849,6 +1273,97 @@ struct dpb_table { struct sg_table *sgt[MFC_MAX_PLANES]; }; +struct disp_drc_info { + int disp_res_change; + int push_idx; + int pop_idx; + int width[MFC_MAX_DRC_FRAME]; + int height[MFC_MAX_DRC_FRAME]; +}; + +struct mfc_dec { + int total_dpb_count; + + unsigned int src_buf_size; + + int loop_filter_mpeg4; + int display_delay; + int immediate_display; + int slice_enable; + int mv_count; + int idr_decoding; + int is_interlaced; + int is_mbaff; + int is_dts_mode; + int inter_res_change; + struct disp_drc_info disp_drc; + + int crc_enable; + unsigned int *crc; + int crc_idx; + + unsigned int consumed; + + int sei_parse; + + int cr_left, cr_right, cr_top, cr_bot; + + int detect_black_bar; + bool black_bar_updated; + struct v4l2_rect black_bar; + + /* For dynamic DPB */ + int is_dynamic_dpb; + int is_dpb_full; + int display_index; + unsigned long queued_dpb; + unsigned long dynamic_set; + unsigned long dynamic_used; + + int is_multiframe; + int has_multiframe; + int is_multiple_show; + + unsigned int num_of_tile_over_4; + unsigned int super64_bframe; + + unsigned int color_range; + unsigned int color_space; + + unsigned int decoding_order; + unsigned int frame_display_delay; + + struct mfc_fmt *uncomp_fmt; + + /* for Internal DPB */ + struct mfc_special_buf internal_dpb[MFC_MAX_DPBS]; + unsigned long plugin_used; + + /* for Dynamic DPB */ + struct dpb_table dpb[MFC_MAX_DPBS]; + /* protection */ + struct mutex dpb_mutex; + unsigned long dpb_table_used; + struct dec_dpb_ref_info *ref_info; + struct stored_dpb_info ref_buf[MFC_MAX_BUFFERS]; + int refcnt; + int last_dpb_max_index; + struct mfc_user_shared_handle sh_handle_dpb; + + /* for debugging about black bar detection */ + void *frame_vaddr[3][30]; + dma_addr_t frame_daddr[3][30]; + int index[3][30]; + int fd[3][30]; + unsigned int frame_size[3][30]; + unsigned char frame_cnt; +}; + +struct mfc_resolution { + int width; + int height; +}; + struct mfc_fmt { char *name; u32 fourcc; @@ -868,18 +1383,65 @@ enum mfc_multi_view_buf_idx { MFC_MV_BUF_IDX_MAX, }; +struct mfc_multi_view_buf_info { + int offset; + int num_fd; +}; + /** * struct mfc_ctx - This struct contains the instance context */ struct mfc_ctx { struct mfc_dev *dev; + struct mfc_dec *dec_priv; int num; int prio; int user_prio; enum mfc_real_time rt; + struct mfc_fmt *src_fmt; + struct mfc_fmt *dst_fmt; + + struct mfc_buf_queue src_buf_ready_queue; + struct mfc_buf_queue dst_buf_queue; + struct mfc_buf_queue err_buf_queue; + struct mfc_buf_queue ref_buf_queue; /* Encoder only */ + spinlock_t buf_queue_lock; + enum mfc_inst_type type; + int subcore_inst_no; + + int img_width; + int img_height; + int crop_width; + int crop_height; + int crop_left; + int crop_top; + int mb_width; + int mb_height; + int dpb_count; + int rgb_bpp; + + int min_dpb_size[3]; + int min_dpb_size_2bits[3]; + + int bytesperline[3]; + struct mfc_raw_info raw_buf; + + int num_fd_frame; + struct mfc_multi_view_buf_info view_buf_info[MFC_MV_BUF_IDX_MAX]; + int select_view; + int select_view_irq; + + enum mfc_queue_state capture_state; + enum mfc_queue_state output_state; + + DECLARE_BITMAP(src_ctrls_avail, MFC_MAX_BUFFERS); + DECLARE_BITMAP(dst_ctrls_avail, MFC_MAX_BUFFERS); + + unsigned int sequence; + int stored_tag; /* operation mode */ int op_core_num[MFC_NUM_CORE]; @@ -888,7 +1450,9 @@ struct mfc_ctx { enum mfc_op_mode op_mode; enum mfc_op_core_type op_core_type; struct mfc_core_lock corelock; - + int serial_src_index; + int curr_src_index; + int cmd_counter; /* protection */ struct mutex op_mode_mutex; int last_op_core; @@ -900,10 +1464,20 @@ struct mfc_ctx { int codec_mode; __u32 pix_format; + /* Profile information */ + int is_422; + int bit_depth_luma; + int bit_depth_chroma; + + /* for AV1 Annex B */ + int is_av1_annex_b; + int is_heif_mode; int is_dpb_realloc; + enum mfc_dec_wait_state wait_state; /* protection */ + struct mutex drc_wait_mutex; int clear_work_bit; /* Extra Buffers */ @@ -911,8 +1485,25 @@ struct mfc_ctx { struct mfc_special_buf mv_buf; unsigned long framerate; + unsigned long last_framerate; + unsigned long operating_framerate; + unsigned long dst_q_framerate; + unsigned long dst_dq_framerate; + unsigned long src_q_framerate; + unsigned long max_framerate; + unsigned int qos_ratio; + bool update_framerate; + bool update_bitrate; + bool check_src_ts_full; + bool ktime_used; + + struct mfc_ts_control src_ts; + struct mfc_ts_control dst_q_ts; + struct mfc_ts_control src_q_ts; + struct mfc_ts_control dst_dq_ts; /* bitrate control for QoS*/ + struct mfc_bitrate bitrate_array[MAX_TIME_INDEX]; struct list_head bitrate_list; int bitrate_index; int bitrate_is_full; @@ -922,6 +1513,7 @@ struct mfc_ctx { unsigned long weighted_mb; struct list_head list; + unsigned int *mfc_qos_portion; int disp_ratio; int buf_process_type; @@ -939,11 +1531,35 @@ struct mfc_ctx { /* QoS idle */ enum mfc_idle_mode idle_mode; + /* Lazy unmap disable */ + int skip_lazy_unmap; + /* external structure */ struct v4l2_fh fh; struct vb2_queue vq_src; struct vb2_queue vq_dst; + /* per buffer controls */ + struct mfc_ctrls_ops *c_ops; + struct mfc_bufs_ops *b_ops; + struct list_head ctrls; + struct list_head src_ctrls[MFC_MAX_BUFFERS]; + struct list_head dst_ctrls[MFC_MAX_BUFFERS]; + + /* Extra Buffers size */ + size_t mv_size; + size_t scratch_buf_size; + size_t loopfilter_luma_size; + size_t loopfilter_chroma_size; + + /* mem info */ + struct mfc_buf_queue meminfo_inbuf_q; + struct mfc_buf_queue meminfo_outbuf_q; + /* protection */ + spinlock_t meminfo_queue_lock; + struct mfc_meminfo meminfo[MFC_MEMINFO_MAX_NUM]; + size_t meminfo_size[MFC_MEMINFO_CTX_MAX + 1]; + u32 ready_to_be_multi_view_enable; u32 multi_view_enable; u32 left_view_id; @@ -963,11 +1579,35 @@ struct mfc_core_ctx { unsigned int int_err; bool check_dump; + struct mfc_buf_queue src_buf_queue; + struct mfc_buf_queue dst_buf_queue; + /* protection */ + spinlock_t buf_queue_lock; + unsigned long dynamic_set; + enum mfc_inst_state state; enum mfc_inst_state prev_state; + /* QoS */ + struct list_head qos_list; + + /* MB control for QoS */ + struct mfc_mb_control mb_table[MFC_MAX_MB_TABLE]; + struct list_head mb_list; + int mb_index; + int mb_is_full; + int dynamic_weight_level; + unsigned int dynamic_weight_started; + int mb_update_time; + unsigned int avg_runtime; + unsigned long mb_not_coded_time; + /* Extra Buffers */ + int codec_buffer_allocated; + int scratch_buffer_allocated; + struct mfc_special_buf codec_buf; struct mfc_special_buf instance_ctx_buf; + struct mfc_special_buf scratch_buf; /* wait queue */ wait_queue_head_t cmd_wq; @@ -979,7 +1619,18 @@ struct mfc_sched_class { void (*create_work)(struct mfc_core *core); void (*init_work)(struct mfc_core *core); void (*clear_all_work)(struct mfc_core *core); + void (*queue_work)(struct mfc_core *core); + int (*is_work)(struct mfc_core *core); + int (*pick_next_work)(struct mfc_core *core); + int (*get_next_work)(struct mfc_core *core); + void (*set_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); void (*clear_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); + int (*enqueue_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); + int (*enqueue_otf_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx, bool flag); + int (*dequeue_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); + void (*yield_work)(struct mfc_core *core, struct mfc_core_ctx *core_ctx); + int (*change_prio_work)(struct mfc_core *core, struct mfc_ctx *ctx, + int cur_rt, int cur_prio, int new_rt, int new_prio); }; #endif /* __MFC_DATA_STRUCT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h new file mode 100644 index 000000000000..3307c2eeaebb --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_format.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_FORMAT_H +#define __MFC_FORMAT_H __FILE__ + +#define MFC_NUM_FORMATS ARRAY_SIZE(mfc_formats) + +static struct mfc_fmt mfc_formats[] = { + { + .name = "Unknown", + .fourcc = 0, + .codec_mode = 0, + .type = 0, + .num_planes = 0, + .mem_planes = 0, + }, + { + .name = "YUV420M", + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME, + .num_planes = 3, + .mem_planes = 3, + }, + { + .name = "YVU420M", + .fourcc = V4L2_PIX_FMT_YVU420M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME, + .num_planes = 3, + .mem_planes = 3, + }, + { + .name = "NV12M", + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME, + .num_planes = 2, + .mem_planes = 2, + }, + { + .name = "NV21M", + .fourcc = V4L2_PIX_FMT_NV21M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME, + .num_planes = 2, + .mem_planes = 2, + }, + { + .name = "NV16M", + .fourcc = V4L2_PIX_FMT_NV16M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_422, + .num_planes = 2, + .mem_planes = 2, + }, + { + .name = "NV61M", + .fourcc = V4L2_PIX_FMT_NV61M, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_422, + .num_planes = 2, + .mem_planes = 2, + }, + { + .name = "RGB888 24bpp", + .fourcc = V4L2_PIX_FMT_RGB24, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "RGB565 16bpp", + .fourcc = V4L2_PIX_FMT_RGB565, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "RGBX8888 32bpp", + .fourcc = V4L2_PIX_FMT_RGB32X, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "BGRA8888 32bpp", + .fourcc = V4L2_PIX_FMT_BGR32, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "ARGB8888 32bpp", + .fourcc = V4L2_PIX_FMT_ARGB32, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "RGB8888 32bpp", + .fourcc = V4L2_PIX_FMT_RGB32, + .codec_mode = MFC_FORMATS_NO_CODEC, + .type = MFC_FMT_FRAME | MFC_FMT_RGB, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC H264", + .fourcc = V4L2_PIX_FMT_H264, + .codec_mode = MFC_REG_CODEC_H264_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, +}; + +#endif /* __MFC_FORMAT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h new file mode 100644 index 000000000000..a41686214988 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_macros.h file + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_MACROS_H +#define __MFC_MACROS_H __FILE__ + +/* helper macros */ +#ifndef __ALIGN_UP +#define __ALIGN_UP(x, a) ({ \ + typeof(a) _a = (a); \ + (((x) + (_a - 1)) & ~(_a - 1)); \ +}) +#endif + +#define WIDTH_MB(x_size) (((x_size) + 15) / 16) +#define HEIGHT_MB(y_size) (((y_size) + 15) / 16) + +/* + * Note that lcu_width and lcu_height are defined as follows : + * lcu_width = (frame_width + lcu_size - 1)/lcu_size + * lcu_height = (frame_height + lcu_size - 1)/lcu_size. + * (lcu_size is 32(encoder) or 64(decoder)) + * + * Note that ctb_width and ctb_height are defined as follows : + * ctb_width = (frame_width + ctb_size - 1)/ctb_size + * ctb_height = (frame_hegiht + ctb_size - 1)/ctb_size + * (ctb_size is 128(AV1 decoder)) + * + */ +#define DEC_LCU_WIDTH(x_size) (((x_size) + 63) / 64) +#define ENC_LCU_WIDTH(x_size) (((x_size) + 31) / 32) +#define DEC_LCU_HEIGHT(y_size) (((y_size) + 63) / 64) +#define ENC_LCU_HEIGHT(y_size) (((y_size) + 31) / 32) + +#define DEC_CTB_WIDTH(x_size) (((x_size) + 127) / 128) +#define DEC_CTB_HEIGHT(y_size) (((y_size) + 127) / 128) + +#define STREAM_BUF_ALIGN SZ_512 +#define MFC_LINEAR_BUF_SIZE SZ_256 + +#define DEC_STATIC_BUFFER_SIZE 20480 +/* STATIC buffer for AV1 will be aligned by 32 */ +#define DEC_AV1_STATIC_BUFFER_SIZE(x_size, y_size) \ + __ALIGN_UP((440192 + (DEC_LCU_WIDTH(x_size) * DEC_LCU_HEIGHT(y_size) * SZ_8K)), SZ_32) + +#define DEC_MV_SIZE_MB(x, y) (WIDTH_MB(x) \ + * (((HEIGHT_MB(y) + SZ_1) / SZ_2) * SZ_2) * SZ_64 + SZ_1K) +#define DEC_HEVC_MV_SIZE(x, y) (DEC_LCU_WIDTH(x) * DEC_LCU_HEIGHT(y) * SZ_256 + SZ_512) +#define DEC_AV1_MV_SIZE(x, y) ((DEC_CTB_WIDTH(x) * DEC_CTB_HEIGHT(y) * 1536) * 10) + +#define ENC_LUMA_DPB_SIZE(x, y) ((((x) + 63) / 64) * 64 * (((y) + 31) / 32) * 32 + 64) +#define ENC_CHROMA_DPB_SIZE(x, y) ((((x) + 63) / 64) * 64 * (((((y) + 31) / 32) * 32) / 2) + 64) + +#define ENC_V100_H264_ME_SIZE(x, y) \ + ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + ((((__x) + 3) * ((__y) + 3) * 8) + (((((__x) * (__y)) + 63) / 64) * 32) + \ + ((((__y) * 64) + 2304) * ((__x) + 7) / 8)); \ + }) +#define ENC_V100_MPEG4_ME_SIZE(x, y) \ + ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + ((((__x) + 3) * ((__y) + 3) * 8) + (((((__x) * (__y)) + 127) / 128) * 16) + \ + ((((__y) * 64) + 2304) * ((__x) + 7) / 8)); \ + }) +#define ENC_V100_VP8_ME_SIZE(x, y) \ + ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + ((((__x) + 3) * ((__y) + 3) * 8) + ((((__y) * 64) + 2304) * ((__x) + 7) / 8)); \ + }) +#define ENC_V100_VP9_ME_SIZE(x, y) \ + ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + (((((__x) * 2) + 3) * (((__y) * 2) + 3) * 128) + \ + ((((__y) * 256) + 2304) * ((__x) + 1) / 2)); \ + }) +#define ENC_V100_HEVC_ME_SIZE(x, y) \ + ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + ((((__x) + 3) * ((__y) + 3) * 32) + ((((__y) * 128) + 2304) * ((__x) + 3) / 4)); \ + }) + +#endif /* __MFC_MACROS_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035600epcas5p13782313e204588986f44514d005ccf70@epcas5p1.samsung.com>]
* [PATCH 10/29] media: mfc: Add buffer‑queue and IOVMM support [not found] ` <CGME20250930035600epcas5p13782313e204588986f44514d005ccf70@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Implement full buffer queue and DPB management (mfc_queue). - Extended mfc_common.h with runtime/boost macros and helper calls. - Added IOVMM helpers ; DPB allocation now uses IOVMM. - Introduced macros for MMCache timeout, boost timing, resolution thresholds, default runtime, and codec limits. - Refined debug and error handling throughout. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 1 + .../samsung/exynos-mfc/base/mfc_common.h | 174 +++- .../samsung/exynos-mfc/base/mfc_mem.c | 190 ++++ .../samsung/exynos-mfc/base/mfc_mem.h | 31 + .../samsung/exynos-mfc/base/mfc_queue.c | 930 ++++++++++++++++++ .../samsung/exynos-mfc/base/mfc_queue.h | 156 +++ .../samsung/exynos-mfc/base/mfc_utils.h | 41 + 7 files changed, 1522 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index bee95b16ac7c..5353289fa810 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -19,6 +19,7 @@ exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o #Plugin control layer #Plugin HW access layer #Common base layer +exynos_mfc-y += base/mfc_queue.o exynos_mfc-y += base/mfc_buf.o base/mfc_mem.o #Tracing # exynos_mfc-y += trace/mfc_trace_points.o diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h index 4a1ec714fbb5..de22c28d1625 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h @@ -20,6 +20,7 @@ #include <linux/cacheflush.h> #include "mfc_data_struct.h" #include "mfc_regs.h" +#include "mfc_macros.h" #include "mfc_debug.h" #include "mfc_media.h" @@ -51,9 +52,20 @@ #define MFC_HWLOCK_TIMEOUT 12000 /* Busy wait timeout */ #define MFC_BW_TIMEOUT 500 - +/* MMCache invalidation timeout */ +#define MMCACHE_INVAL_TIMEOUT 1000 /* Interrupt timeout count*/ #define MFC_INT_TIMEOUT_CNT 3 +/* The initial skip frame for boost */ +#define MFC_INITIAL_SKIP_FRAME 60 +/* The MAX I frame interval for boosting is 2000ms(2sec) */ +#define MFC_BOOST_TIME (2000) +/* The boost mode is maintained at least 20msec */ +#define MFC_BOOST_OFF_TIME ((MFC_BOOST_TIME * NSEC_PER_MSEC) - (20 * NSEC_PER_MSEC)) +/* The boost speed is multiplied by the framerate */ +#define MFC_BOOST_SPEED (8) + +#define MFC_DEFAULT_RUNTIME (33000) /* * This value guarantees 299.4msec ~ 2.25sec according to MFC clock (668MHz ~ 89MHz) @@ -63,6 +75,10 @@ /* 250ms is the mfc firmware timeout value*/ #define MFC_TIMEOUT_VALUE_IN_MSEC 250 +#define NUM_MPEG4_LF_BUF 2 + +#define FRAME_RATE_RESOLUTION 10000 + #define DEFAULT_TAG (0xE05) #define IGNORE_TAG (0xD5C) /* ex) encoder DRC */ #define HEADER_TAG (0xC5D) @@ -70,6 +86,11 @@ #define MFC_NO_INSTANCE_SET -1 +#define MFC_ENC_CAP_PLANE_COUNT 1 +#define MFC_ENC_OUT_PLANE_COUNT 2 + +#define MFC_NAME_LEN 16 + #define STUFF_BYTE 4 #define MFC_EXTRA_DPB 5 #define MFC_ALL_AVAILABLE_DPB 0xffffffffffffffff @@ -82,12 +103,30 @@ #define mfc_get_warn(x) (((x) >> MFC_REG_WARN_STATUS_SHIFT) \ & MFC_REG_WARN_STATUS_MASK) +/* MFC conceal color is black */ +#define MFC_CONCEAL_COLOR 0x8020000 + #define vb_to_mfc_buf(x) \ container_of(x, struct mfc_buf, vb.vb2_buf) #define fh_to_mfc_ctx(x) \ container_of(x, struct mfc_ctx, fh) +#define call_bop(ctx, op, args...) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->b_ops->op) ? (_ctx->b_ops->op(args)) : 0); \ +}) + +#define call_cop(ctx, op, args...) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->c_ops->op) ? (_ctx->c_ops->op(args)) : 0); \ +}) + +#define MFC_CTRL_TYPE_GET (MFC_CTRL_TYPE_GET_SRC | MFC_CTRL_TYPE_GET_DST) +#define MFC_CTRL_TYPE_SET (MFC_CTRL_TYPE_SET_SRC | MFC_CTRL_TYPE_SET_DST) +#define MFC_CTRL_TYPE_SRC (MFC_CTRL_TYPE_SET_SRC | MFC_CTRL_TYPE_GET_SRC) +#define MFC_CTRL_TYPE_DST (MFC_CTRL_TYPE_SET_DST | MFC_CTRL_TYPE_GET_DST) + #define MFC_FMT_STREAM BIT(0) #define MFC_FMT_FRAME BIT(1) #define MFC_FMT_10BIT BIT(2) @@ -112,6 +151,132 @@ (_n == EXYNOS_VIDEONODE_MFC_ENC_OTF_DRM)); \ }) +/* Decoder codec mode check */ +#define IS_H264_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_DEC) + +#define ON_RES_CHANGE(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->state >= MFCINST_RES_CHANGE_INIT) && \ + (_ctx->state < MFCINST_RES_CHANGE_END)); \ +}) +#define ON_RUNNING(ctx) ((ctx)->state == MFCINST_RUNNING) +#define NEED_TO_DPB_FLUSH(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->state == MFCINST_FINISHING) || (_ctx->state == MFCINST_RUNNING) || \ + (_ctx->state == MFCINST_RES_CHANGE_END)); \ +}) +#define NEED_TO_WAIT_NAL_ABORT(ctx) ((ctx)->state == MFCINST_ABORT_INST) +#define NEED_TO_GET_CROP(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->state == MFCINST_HEAD_PARSED) || (_ctx->state == MFCINST_RUNNING) || \ + (_ctx->state == MFCINST_FINISHING)); \ +}) +#define IS_NO_ERROR(err) ({ \ + typeof(err) _err = (err); \ + (_err == 0 || (mfc_get_warn(_err) == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED)); \ +}) +#define CODEC_HAS_IDR(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_H264_DEC(_ctx)); \ +}) + +/* + * levels with maximum property values + * level Maximum frame size in MB (MB width x MB height) + * LV5 22,080 + * LV5.1 36,864 + * LV6 139,264 + */ + +#define LV51_MB_MIN (22080) +#define LV51_MB_MAX (36864) +#define LV60_MB_MAX (139264) + +#define IS_LV51_MB(mb) ({ \ + typeof(mb) _mb = (mb); \ + ((_mb > LV51_MB_MIN) && (_mb <= LV51_MB_MAX)); \ +}) +#define IS_LV60_MB(mb) ({ \ + typeof(mb) _mb = (mb); \ + ((_mb > LV51_MB_MAX) && (_mb <= LV60_MB_MAX)); \ +}) + +/* 8K resolution */ +#define MFC_8K_RES (7680 * 4320) +#define IS_8K_RES(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->crop_width * _ctx->crop_height) >= MFC_8K_RES); \ +}) +/* For max h/w performance */ +#define IS_8K_PERF(ctx) ({ \ + typeof(ctx) __ctx = (ctx); \ + ((__ctx->crop_width * __ctx->crop_height) >= (MFC_8K_RES / 2)); \ +}) +#define UNDER_8K_RES(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->crop_width * _ctx->crop_height) < MFC_8K_RES); \ +}) + +/* 4K resolution */ +/* VP9 needs 64 alignment because of min MB(64x64) */ +#define MFC_4K_RES (4096 * 2160) +#define MFC_4K_RES_64ALIGN (4096 * 2176) +#define UNDER_4K_RES(ctx) ({ \ + typeof(ctx) __ctx = (ctx); \ + ((__ctx->crop_width * __ctx->crop_height) < MFC_4K_RES_64ALIGN); \ +}) +#define IS_MULTI_MODE_RES(ctx) ({ \ + typeof(ctx) __ctx = (ctx); \ + ((__ctx->img_width * __ctx->img_height) >= (2 * MFC_4K_RES)); \ +}) + +/* UHD resolution */ +#define MFC_UHD_RES (3840 * 2160) +#define OVER_UHD_RES(ctx) ({ \ + typeof(ctx) __ctx = (ctx); \ + ((__ctx->crop_width * __ctx->crop_height) >= MFC_UHD_RES); \ +}) +#define UNDER_UHD_RES(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->crop_width * _ctx->crop_height) <= MFC_4K_RES_64ALIGN); \ +}) + +/* FHD resolution */ +#define MFC_FHD_RES (1920 * 1088) +#define MFC_1080P_RES (1920 * 1080) +#define MFC_FHD_RES_MB (((1920 + 15) / 16) * ((1088 + 15) / 16)) +#define UNDER_FHD_RES(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((_ctx->crop_width * _ctx->crop_height) <= MFC_FHD_RES); \ +}) +#define UNDER_1080P_RES(ctx) ({ \ + typeof(ctx) __ctx = (ctx); \ + (((__ctx)->crop_width * (__ctx)->crop_height) < MFC_1080P_RES); \ +}) + +/* HD resolution */ +#define MFC_HD_RES_MB (((1280 + 15) / 16) * ((720 + 15) / 16)) + +/* + * If it is a resolution that requires max performance, + * the performance degradation option is not available. + * (2-ref, B frame) + */ +#define IS_MFC_MAX_PERF(ctx, fps) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_8K_PERF(_ctx) || (OVER_UHD_RES(_ctx) && ((fps) > 60))); \ +}) +#define IS_MFC_HEAVY_PERF(ctx, fps) ({ \ + typeof(ctx) _ctx = (ctx); \ + typeof(fps) _fps = (fps); \ + (IS_8K_PERF(_ctx) || (OVER_UHD_RES(_ctx) && (_fps >= 60)) || \ + (_fps >= 240)); \ +}) + +#define IS_BLACKBAR_OFF(ctx) ((ctx)->crop_height > 2160) + +#define IS_SINGLE_FD(ctx, fmt) ((!(ctx)->rgb_bpp) && ((fmt)->mem_planes == 1)) + #define IS_MULTI_CORE_DEVICE(dev) ((dev)->num_core > 1) #define IS_SINGLE_MODE(ctx) ((ctx)->op_mode == MFC_OP_SINGLE) #define IS_TWO_MODE1(ctx) ((ctx)->op_mode == MFC_OP_TWO_MODE1) @@ -134,6 +299,13 @@ (_ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2)); \ }) +#define IS_MODE_SWITCHING(ctx) ((ctx)->op_mode == MFC_OP_SWITCHING) + +#define IS_NO_INFOLOG(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (_ctx->dec_priv && _ctx->dec_priv->is_multiframe); \ +}) + /* Extra information for Decoder */ #define DEC_SET_DUAL_DPB BIT(0) #define DEC_SET_DYNAMIC_DPB BIT(1) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c index dfb58ddcbd5d..17cc1d793cbc 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c @@ -334,6 +334,196 @@ void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *speci } } +void mfc_put_iovmm(struct mfc_ctx *ctx, struct dpb_table *dpb, int num_planes, int index) +{ + int i; + + MFC_TRACE_CTX("DPB[%d] fd: %d addr: %#llx put(%d)\n", + index, dpb[index].fd[0], dpb[index].addr[0], dpb[index].mapcnt); + + for (i = 0; i < num_planes; i++) { + if (dpb[index].addr[i]) + mfc_ctx_debug(2, "[IOVMM] index %d buf[%d] fd: %d addr: %#llx\n", + index, i, dpb[index].fd[i], dpb[index].addr[i]); + if (dpb[index].sgt[i]) + dma_buf_unmap_attachment_unlocked(dpb[index].attach[i], dpb[index].sgt[i], + DMA_BIDIRECTIONAL); + if (dpb[index].attach[i]) + dma_buf_detach(dpb[index].dmabufs[i], dpb[index].attach[i]); + if (dpb[index].dmabufs[i]) + dma_buf_put(dpb[index].dmabufs[i]); + + dpb[index].fd[i] = -1; + dpb[index].addr[i] = 0; + dpb[index].attach[i] = NULL; + dpb[index].dmabufs[i] = NULL; + dpb[index].sgt[i] = NULL; + } + + dpb[index].new_fd = -1; + dpb[index].mapcnt--; + mfc_ctx_debug(2, "[IOVMM] index %d mapcnt %d\n", index, dpb[index].mapcnt); + + if (dpb[index].mapcnt != 0) { + mfc_ctx_err("[IOVMM] DPB[%d] %#llx invalid mapcnt %d\n", + index, dpb[index].addr[0], dpb[index].mapcnt); + dpb[index].mapcnt = 0; + } +} + +void mfc_get_iovmm(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct dpb_table *dpb) +{ + struct mfc_dev *dev = ctx->dev; + int i, mem_get_count = 0; + struct mfc_buf *mfc_buf = vb_to_mfc_buf(vb); + int index = mfc_buf->dpb_index; + int sub_view_index, offset; + + if (dpb[index].mapcnt != 0) + mfc_ctx_err("[IOVMM] DPB[%d] %#llx invalid mapcnt %d\n", + index, dpb[index].addr[0], dpb[index].mapcnt); + + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) { + mem_get_count++; + + dpb[index].fd[i] = vb->planes[i].m.fd; + + dpb[index].dmabufs[i] = dma_buf_get(vb->planes[i].m.fd); + if (IS_ERR(dpb[index].dmabufs[i])) { + mfc_ctx_err("[IOVMM] Failed to dma_buf_get (err %ld)\n", + PTR_ERR(dpb[index].dmabufs[i])); + dpb[index].dmabufs[i] = NULL; + goto err_iovmm; + } + + dpb[index].attach[i] = dma_buf_attach(dpb[index].dmabufs[i], dev->device); + if (IS_ERR(dpb[index].attach[i])) { + mfc_ctx_err("[IOVMM] Failed to get dma_buf_attach (err %ld)\n", + PTR_ERR(dpb[index].attach[i])); + dpb[index].attach[i] = NULL; + goto err_iovmm; + } + + dpb[index].sgt[i] = + dma_buf_map_attachment_unlocked(dpb[index].attach[i], + DMA_BIDIRECTIONAL); + if (IS_ERR(dpb[index].sgt[i])) { + mfc_ctx_err("[IOVMM] Failed to get sgt (err %ld)\n", + PTR_ERR(dpb[index].sgt[i])); + dpb[index].sgt[i] = NULL; + goto err_iovmm; + } + + dpb[index].addr[i] = sg_dma_address(dpb[index].sgt[i]->sgl); + if (IS_ERR_VALUE(dpb[index].addr[i])) { + mfc_ctx_err("[IOVMM] Failed to get iova (err 0x%p)\n", + &dpb[index].addr[i]); + dpb[index].addr[i] = 0; + goto err_iovmm; + } + + mfc_ctx_debug(2, "[IOVMM] index %d buf[%d] fd: %d addr: %#llx\n", + index, i, dpb[index].fd[i], dpb[index].addr[i]); + } +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + dpb[index].paddr = page_to_phys(sg_page(dpb[index].sgt[0]->sgl)); +#else + dpb[index].paddr = dpb[index].sgt[0]->sgl->dma_address; +#endif + mfc_ctx_debug(2, "[DPB] dpb index [%d][%d] paddr %#llx daddr %#llx\n", + mfc_buf->vb.vb2_buf.index, + index, dpb[index].paddr, dpb[index].addr[0]); + + dpb[index].mapcnt++; + mfc_ctx_debug(2, "[IOVMM] index %d mapcnt %d\n", index, dpb[index].mapcnt); + MFC_TRACE_CTX("DPB[%d] fd: %d addr: %#llx get(%d)\n", + index, dpb[index].fd[0], dpb[index].addr[0], dpb[index].mapcnt); + + /* In multi_view_enable, sub_view should be mapped together. + * Lower 32 bits are used for main_view. Upper 32 bits are used for sub_view. + */ + if (ctx->multi_view_enable) { + sub_view_index = index + MFC_MAX_DPBS / 2; + if (dpb[sub_view_index].mapcnt != 0) + mfc_ctx_err("[IOVMM] DPB[%d] %#llx invalid mapcnt %d\n", + sub_view_index, dpb[sub_view_index].addr[0], + dpb[sub_view_index].mapcnt); + + offset = ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1].offset; + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) { + mem_get_count++; + + dpb[sub_view_index].fd[i] = vb->planes[offset + i].m.fd; + + dpb[sub_view_index].dmabufs[i] = dma_buf_get(vb->planes[offset + i].m.fd); + if (IS_ERR(dpb[sub_view_index].dmabufs[i])) { + mfc_ctx_err("[IOVMM] Failed to dma_buf_get (err %ld)\n", + PTR_ERR(dpb[sub_view_index].dmabufs[i])); + dpb[sub_view_index].dmabufs[i] = NULL; + goto err_iovmm_sub; + } + + dpb[sub_view_index].attach[i] = + dma_buf_attach(dpb[sub_view_index].dmabufs[i], dev->device); + if (IS_ERR(dpb[sub_view_index].attach[i])) { + mfc_ctx_err("[IOVMM] Failed to get dma_buf_attach (err %ld)\n", + PTR_ERR(dpb[sub_view_index].attach[i])); + dpb[sub_view_index].attach[i] = NULL; + goto err_iovmm_sub; + } + + dpb[sub_view_index].sgt[i] = + dma_buf_map_attachment_unlocked(dpb[sub_view_index].attach[i], + DMA_BIDIRECTIONAL); + if (IS_ERR(dpb[sub_view_index].sgt[i])) { + mfc_ctx_err("[IOVMM] Failed to get sgt (err %ld)\n", + PTR_ERR(dpb[sub_view_index].sgt[i])); + dpb[sub_view_index].sgt[i] = NULL; + goto err_iovmm_sub; + } + + dpb[sub_view_index].addr[i] = + sg_dma_address(dpb[sub_view_index].sgt[i]->sgl); + if (IS_ERR_VALUE(dpb[sub_view_index].addr[i])) { + mfc_ctx_err("[IOVMM] Failed to get iova (err 0x%p)\n", + &dpb[sub_view_index].addr[i]); + dpb[sub_view_index].addr[i] = 0; + goto err_iovmm_sub; + } + + mfc_ctx_debug(2, "[IOVMM] sub_view_index %d buf[%d] fd: %d addr: %#llx\n", + sub_view_index, i, dpb[sub_view_index].fd[i], + dpb[sub_view_index].addr[i]); + } +#if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) + dpb[sub_view_index].paddr = page_to_phys(sg_page(dpb[sub_view_index].sgt[0]->sgl)); +#else + dpb[sub_view_index].paddr = dpb[sub_view_index].sgt[0]->sgl->dma_address; +#endif + mfc_ctx_debug(2, "[DPB] dpb index [%d][%d] paddr %#llx daddr %#llx\n", + mfc_buf->vb.vb2_buf.index, + sub_view_index, dpb[sub_view_index].paddr, + dpb[sub_view_index].addr[0]); + + dpb[sub_view_index].mapcnt++; + mfc_ctx_debug(2, "[IOVMM] index %d mapcnt %d\n", index, dpb[sub_view_index].mapcnt); + MFC_TRACE_CTX("DPB[%d] fd: %d addr: %#llx get(%d)\n", + sub_view_index, dpb[sub_view_index].fd[0], + dpb[sub_view_index].addr[0], dpb[sub_view_index].mapcnt); + } + + return; + +err_iovmm: + dpb[index].mapcnt++; + mfc_put_iovmm(ctx, dpb, mem_get_count, index); + return; +err_iovmm_sub: + dpb[sub_view_index].mapcnt++; + mfc_put_iovmm(ctx, dpb, mem_get_count, index); + mfc_put_iovmm(ctx, dpb, mem_get_count, sub_view_index); +} + void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf) { /* Project that do not support iova reservation */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h index 7b37e5fedbf2..3deeb0d611a0 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h @@ -66,9 +66,40 @@ static inline size_t mfc_mem_get_sg_length(struct mfc_dev *dev, struct sg_table return size; } +static inline void mfc_print_dpb_table(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *mfc_buf = NULL; + unsigned long flags; + int i, found = 0; + + mfc_ctx_debug(3, "[DPB] dynamic_used: %#lx, queued: %#lx, table_used: %#lx\n", + dec->dynamic_used, dec->queued_dpb, dec->dpb_table_used); + for (i = 0; i < MFC_MAX_DPBS; i++) { + found = 0; + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + list_for_each_entry(mfc_buf, &ctx->dst_buf_queue.head, list) { + if (i == mfc_buf->dpb_index) { + found = 1; + break; + } + } + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + mfc_ctx_debug(3, "[%d] dpb [%d] %#010llx %#010llx %#010llx fd %d(%d) (%s, %s, %s)\n", + i, found ? mfc_buf->vb.vb2_buf.index : -1, + dec->dpb[i].addr[0], dec->dpb[i].addr[1], + dec->dpb[i].paddr, dec->dpb[i].fd[0], dec->dpb[i].new_fd, + dec->dpb[i].mapcnt ? "map" : "unmap", + dec->dpb[i].ref ? "ref" : "free", + dec->dpb[i].queued ? "Q" : "DQ"); + } +} int mfc_mem_special_buf_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf); void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *special_buf); +void mfc_put_iovmm(struct mfc_ctx *ctx, struct dpb_table *dpb, int num_planes, int index); +void mfc_get_iovmm(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct dpb_table *dpb); void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf); int mfc_iova_pool_alloc(struct mfc_dev *dev, struct mfc_special_buf *buf); int mfc_iova_pool_init(struct mfc_dev *dev); diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c new file mode 100644 index 000000000000..f56e800c55f0 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c @@ -0,0 +1,930 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_queue.c + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_queue.h" + +#include "mfc_utils.h" +#include "mfc_mem.h" + +void mfc_add_tail_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + struct mfc_buf *mfc_buf) +{ + unsigned long flags; + + if (!mfc_buf) { + mfc_ctx_err("mfc_buf is NULL!\n"); + return; + } + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + mfc_buf->used = 0; + list_add_tail(&mfc_buf->list, &queue->head); + queue->count++; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +struct mfc_buf *mfc_get_buf_no_used(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&queue->head)) { + mfc_ctx_debug(2, "queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + list_for_each_entry(mfc_buf, &queue->head, list) { + if (mfc_buf->used) + continue; + + if (used == MFC_BUF_RESET_USED || used == MFC_BUF_SET_USED) + mfc_buf->used = used; + + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; +} + +struct mfc_buf *mfc_get_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&queue->head)) { + mfc_ctx_debug(2, "queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + + if (used == MFC_BUF_RESET_USED || used == MFC_BUF_SET_USED) + mfc_buf->used = used; + + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; +} + +struct mfc_buf *mfc_get_del_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&queue->head)) { + mfc_ctx_debug(2, "queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + + if (used == MFC_BUF_RESET_USED || used == MFC_BUF_SET_USED) + mfc_buf->used = used; + + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + + list_del(&mfc_buf->list); + queue->count--; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; +} + +struct mfc_buf *mfc_get_del_if_consumed(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + unsigned int consumed, + unsigned int min_bytes, + int error, + int *deleted) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + unsigned int remained, strm_size; + bool exceed = false; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&queue->head)) { + mfc_ctx_debug(2, "queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + + strm_size = mfc_dec_get_strm_size(ctx, mfc_buf); + if (strm_size >= consumed) { + remained = strm_size - consumed; + } else { + remained = 0; + exceed = true; + mfc_ctx_err("[MULTIFRAME] consumed (%d) exceeded the strm_size (%d)\n", + consumed, strm_size); + } + + if (consumed > 0 && remained > min_bytes && + IS_NO_ERROR(error) && !exceed) { + /* do not delete from queue */ + *deleted = 0; + } else { + list_del(&mfc_buf->list); + queue->count--; + + *deleted = 1; + } + + mfc_ctx_debug(2, "[MULTIFRAME] strm %d, consumed %d, remained %d, deleted %d, error %d, exceed %d\n", + strm_size, consumed, remained, *deleted, error, exceed); + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; +} + +struct mfc_buf *mfc_get_move_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, + enum mfc_queue_used_type used, + enum mfc_queue_top_type top) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&from_queue->head)) { + mfc_ctx_debug(2, "from_queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); + + if (used == MFC_BUF_RESET_USED || used == MFC_BUF_SET_USED) + mfc_buf->used = used; + + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + + list_del(&mfc_buf->list); + from_queue->count--; + + if (top == MFC_QUEUE_ADD_TOP) + list_add(&mfc_buf->list, &to_queue->head); + else + list_add_tail(&mfc_buf->list, &to_queue->head); + + to_queue->count++; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; +} + +struct mfc_buf *mfc_get_move_buf_used(struct mfc_ctx *ctx, + struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&from_queue->head)) { + mfc_ctx_debug(2, "from_queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; + } + + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); + + if (mfc_buf->used) { + mfc_ctx_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); + + list_del(&mfc_buf->list); + from_queue->count--; + + list_add_tail(&mfc_buf->list, &to_queue->head); + to_queue->count++; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; +} + +struct mfc_buf *mfc_find_first_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + dma_addr_t addr) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + dma_addr_t mb_addr; + int i; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&queue->head)) { + mfc_ctx_debug(2, "queue is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + + mfc_ctx_debug(4, "Looking for this address: 0x%08llx\n", addr); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + if (mfc_buf->num_valid_bufs > 0) { + for (i = 0; i < mfc_buf->num_valid_bufs; i++) { + mb_addr = mfc_buf->addr[i][0]; + mfc_ctx_debug(4, "[BUFCON] batch[%d] addr[0]: 0x%08llx\n", i, mb_addr); + if (addr == mb_addr) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + } + } else { + mb_addr = mfc_buf->addr[0][0]; + mfc_ctx_debug(4, "addr[0]: 0x%08llx\n", mb_addr); + + if (addr == mb_addr) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + } + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; +} + +struct mfc_buf *mfc_find_buf(struct mfc_ctx *ctx, struct mfc_buf_queue *queue, dma_addr_t addr) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + dma_addr_t mb_addr; + int i; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + mfc_ctx_debug(4, "Looking for this address: 0x%08llx\n", addr); + list_for_each_entry(mfc_buf, &queue->head, list) { + if (mfc_buf->num_valid_bufs > 0) { + for (i = 0; i < mfc_buf->num_valid_bufs; i++) { + mb_addr = mfc_buf->addr[i][0]; + mfc_ctx_debug(4, "[BUFCON] batch[%d] addr[0]: 0x%08llx\n", + i, mb_addr); + if (addr == mb_addr) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + } + } else { + mb_addr = mfc_buf->addr[0][0]; + mfc_ctx_debug(4, "addr[0]: 0x%08llx\n", mb_addr); + + if (addr == mb_addr) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + } + } + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; +} + +struct mfc_buf *mfc_find_del_buf(struct mfc_ctx *ctx, struct mfc_buf_queue *queue, dma_addr_t addr) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + dma_addr_t mb_addr; + int found = 0, i; + int index_view; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + mfc_ctx_debug(4, "Looking for this address: 0x%08llx\n", addr); + list_for_each_entry(mfc_buf, &queue->head, list) { + if (mfc_buf->num_valid_bufs > 0) { + for (i = 0; i < mfc_buf->num_valid_bufs; i++) { + mb_addr = mfc_buf->addr[i][0]; + mfc_ctx_debug(4, "batch buf[%d] plane[0] addr: 0x%08llx\n", + i, mb_addr); + + if (addr == mb_addr) { + found = 1; + break; + } + } + + if (found) + break; + } else { + /* + * In case of not Multi-View, Main view will be selected always. + */ + if (ctx->type == MFCINST_DECODER) + index_view = ctx->select_view_irq == MFC_VIEW_ID_MAIN ? + MFC_MV_BUF_IDX_VIEW0 : MFC_MV_BUF_IDX_VIEW1; + else + index_view = ctx->select_view == MFC_VIEW_ID_MAIN ? + MFC_MV_BUF_IDX_VIEW0 : MFC_MV_BUF_IDX_VIEW1; + mb_addr = mfc_buf->addr[index_view][0]; + mfc_ctx_debug(4, "addr[0]: 0x%08llx\n", mb_addr); + + if (addr == mb_addr) { + found = 1; + break; + } + } + } + + if (found == 1) { + list_del(&mfc_buf->list); + queue->count--; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return NULL; +} + +void mfc_move_buf_all(struct mfc_ctx *ctx, struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, enum mfc_queue_top_type top) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (top == MFC_QUEUE_ADD_TOP) { + while (!list_empty(&from_queue->head)) { + mfc_buf = list_entry(from_queue->head.prev, struct mfc_buf, list); + + list_del(&mfc_buf->list); + from_queue->count--; + + list_add(&mfc_buf->list, &to_queue->head); + to_queue->count++; + } + } else { + while (!list_empty(&from_queue->head)) { + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); + + list_del(&mfc_buf->list); + from_queue->count--; + + list_add_tail(&mfc_buf->list, &to_queue->head); + to_queue->count++; + } + } + + INIT_LIST_HEAD(&from_queue->head); + from_queue->count = 0; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +void mfc_return_buf_to_ready_queue(struct mfc_ctx *ctx, + struct mfc_buf_queue *maincore_queue, + struct mfc_buf_queue *subcore_queue) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_buf_queue *to_queue = &ctx->src_buf_ready_queue; + struct mfc_buf_queue *first_queue, *second_queue; + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + int maincore_src_index = -1, subcore_src_index = -1; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (list_empty(&maincore_queue->head) && list_empty(&subcore_queue->head)) { + mfc_ctx_debug(2, "all src queue of core_ctx is empty\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return; + } + + /* Search the last distributed src index */ + if (!list_empty(&maincore_queue->head)) { + mfc_buf = list_entry(maincore_queue->head.prev, struct mfc_buf, list); + maincore_src_index = mfc_buf->src_index; + mfc_ctx_debug(4, "maincore src last buf src index: %d\n", maincore_src_index); + } + if (!list_empty(&subcore_queue->head)) { + mfc_buf = list_entry(subcore_queue->head.prev, struct mfc_buf, list); + subcore_src_index = mfc_buf->src_index; + mfc_ctx_debug(4, "subcore src last buf src index: %d\n", subcore_src_index); + } + + MFC_TRACE_RM("[c:%d] last src index maincore %d subcore %d\n", + ctx->num, maincore_src_index, subcore_src_index); + + /* Select the core_ctx->src_buf_queue to take out first */ + if (maincore_src_index > subcore_src_index) { + first_queue = maincore_queue; + second_queue = subcore_queue; + mfc_ctx_debug(2, "last src index (maincore:%d, subcore:%d) move first maincore\n", + maincore_src_index, subcore_src_index); + } else { + first_queue = subcore_queue; + second_queue = maincore_queue; + mfc_ctx_debug(2, "last src index (maincore:%d, subcore:%d) move first subcore\n", + maincore_src_index, subcore_src_index); + } + + /* Src index is sequentially returned to ready_queue */ + while (1) { + if (!list_empty(&first_queue->head)) { + mfc_buf = list_entry(first_queue->head.prev, struct mfc_buf, list); + + list_del(&mfc_buf->list); + first_queue->count--; + + list_add(&mfc_buf->list, &to_queue->head); + to_queue->count++; + mfc_ctx_debug(2, "first queue src[%d] move\n", mfc_buf->src_index); + MFC_TRACE_RM("[c:%d] first queue src[%d] move\n", ctx->num, + mfc_buf->src_index); + } + + if (!list_empty(&second_queue->head)) { + mfc_buf = list_entry(second_queue->head.prev, struct mfc_buf, list); + + list_del(&mfc_buf->list); + second_queue->count--; + + list_add(&mfc_buf->list, &to_queue->head); + to_queue->count++; + mfc_ctx_debug(2, "second queue src[%d] move\n", mfc_buf->src_index); + MFC_TRACE_RM("[c:%d] second queue src[%d] move\n", ctx->num, + mfc_buf->src_index); + } + + if (list_empty(&first_queue->head) && list_empty(&second_queue->head)) { + mfc_ctx_debug(2, "all src of core_ctx return to ready_queue\n"); + mfc_ctx_debug(2, "ready %d maincore %d subcore %d\n", + to_queue->count, maincore_queue->count, + subcore_queue->count); + MFC_TRACE_RM("[c:%d] all src return to ready\n", ctx->num); + MFC_TRACE_RM("[c:%d] ready %d maincore %d subcore %d\n", ctx->num, + to_queue->count, maincore_queue->count, + subcore_queue->count); + INIT_LIST_HEAD(&first_queue->head); + first_queue->count = 0; + INIT_LIST_HEAD(&second_queue->head); + second_queue->count = 0; + break; + } + } + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue) +{ + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + int i; + + spin_lock_irqsave(plock, flags); + + while (!list_empty(&queue->head)) { + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + + for (i = 0; i < mfc_buf->vb.vb2_buf.num_planes; i++) + vb2_set_plane_payload(&mfc_buf->vb.vb2_buf, i, 0); + + vb2_buffer_done(&mfc_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + list_del(&mfc_buf->list); + queue->count--; + } + + INIT_LIST_HEAD(&queue->head); + queue->count = 0; + + spin_unlock_irqrestore(plock, flags); +} + +void mfc_print_dpb_queue(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_buf *mfc_buf = NULL; + + mfc_debug(2, "[DPB] src: %d(ready: %d), dst %d, used %#lx, queued %#lx, set %#lx(dec: %#lx)\n", + core_ctx->src_buf_queue.count, + ctx->src_buf_ready_queue.count, + ctx->dst_buf_queue.count, + dec->dynamic_used, dec->queued_dpb, + core_ctx->dynamic_set, dec->dynamic_set); + + if (!list_empty(&ctx->dst_buf_queue.head)) + list_for_each_entry(mfc_buf, &ctx->dst_buf_queue.head, list) + mfc_debug(2, "[DPB] dst[%d][%d] %#llx used: %d\n", + mfc_buf->vb.vb2_buf.index, + mfc_buf->dpb_index, + mfc_buf->addr[0][0], mfc_buf->used); +} + +void mfc_print_dpb_queue_with_lock(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + mfc_print_dpb_queue(core_ctx, dec); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +int mfc_get_available_dpb_count(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *mfc_buf = NULL; + unsigned long flags, used_flag_count; + int cnt = 0; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + if (ctx->dst_buf_queue.count == 0) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return 0; + } + + list_for_each_entry(mfc_buf, &ctx->dst_buf_queue.head, list) { + if (IS_TWO_MODE2(ctx) && (dec->dynamic_set & (1UL << mfc_buf->dpb_index))) { + mfc_debug(2, "[DPB] dst index %d already set\n", + mfc_buf->dpb_index); + continue; + } + if ((dec->dynamic_used & (1UL << mfc_buf->dpb_index)) == 0) { + mfc_debug(2, "[DPB] There is available dpb(index:%d, used:%#lx)\n", + mfc_buf->dpb_index, dec->dynamic_used); + cnt++; + } + } + + if (cnt) { + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return cnt; + } + + used_flag_count = hweight64(dec->dynamic_used); + if (used_flag_count >= ctx->dpb_count) { + mfc_debug(2, "[DPB] All DPB(%ld) of min count are referencing\n", + used_flag_count); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return 1; + } + + mfc_debug(2, "[DPB] There is no available DPB\n"); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + + return 0; +} + +/* Try to search non-referenced DPB on dst-queue */ +struct mfc_buf *mfc_search_for_dpb(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dec *dec = ctx->dec_priv; + unsigned long flags, used_flag_count; + struct mfc_buf *mfc_buf = NULL; + int dpb_index; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + list_for_each_entry(mfc_buf, &ctx->dst_buf_queue.head, list) { + dpb_index = mfc_buf->dpb_index; + /* sub_view was mapped together(at qbuf). + * At the time, dpb_index of sub_view is dpb_index of main_view + MFC_MAX_DPBS / 2 + */ + if (ctx->multi_view_enable && ctx->select_view == MFC_VIEW_ID_SUB) + dpb_index += (MFC_MAX_DPBS / 2); + if (IS_TWO_MODE2(ctx) && (dec->dynamic_set & (1UL << dpb_index))) { + mfc_debug(2, "[DPB] dst index %d already set\n", + dpb_index); + continue; + } + if ((dec->dynamic_used & (1UL << dpb_index)) == 0) { + mfc_buf->used = 1; + dec->dynamic_set = 1UL << dpb_index; + core_ctx->dynamic_set = 1UL << dpb_index; + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + } + + /* + * Bumping process + * In case of H.264/HEVC codec, + * all of the queued buffers can be referenced by F/W. + * At that time, we should set the any DPB to F/W, + * F/W will returns display only buffer whether if reference or not. + * In this way the reference can be released by circulating. + */ + used_flag_count = hweight64(dec->dynamic_used); + if (used_flag_count >= ctx->dpb_count) { + mfc_buf = list_entry(ctx->dst_buf_queue.head.next, struct mfc_buf, list); + mfc_buf->used = 1; + dpb_index = mfc_buf->dpb_index; + if (ctx->multi_view_enable && ctx->select_view == MFC_VIEW_ID_SUB) + dpb_index += (MFC_MAX_DPBS / 2); + mfc_debug(2, "[DPB] All DPB(%ld) of min count are referencing. select buf[%d][%d]\n", + used_flag_count, mfc_buf->vb.vb2_buf.index, dpb_index); + dec->dynamic_set = 1UL << dpb_index; + core_ctx->dynamic_set = 1UL << dpb_index; + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return mfc_buf; + } + + /* + * 1) ctx->dst_buf_queue.count >= (ctx->dpb_count + MFC_EXTRA_DPB): All DPBs queued in DRV + * 2) ctx->dst_buf_queue.count == 0: All DPBs dequeued to user + * we will wait + */ + mfc_debug(2, "[DPB] All enqueued DPBs are referencing or there's no DPB in DRV (in %d/total %d)\n", + ctx->dst_buf_queue.count, ctx->dpb_count + MFC_EXTRA_DPB); + if (!(dec->queued_dpb & ~dec->dynamic_used)) + mfc_debug(2, "[DPB] All enqueued DPBs are referencing\n"); + + mfc_print_dpb_queue(core_ctx, dec); + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + + mutex_lock(&dec->dpb_mutex); + mfc_print_dpb_table(ctx); + mutex_unlock(&dec->dpb_mutex); + + return NULL; +} + +static int __mfc_assign_dpb_index(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned long used; + int index = -1; + int max_dpb = MFC_MAX_DPBS; + int i, dpb_table_used; + + /* When multi_view_enable(MV-HEVC), driver has to limit assign dpb_index + * as the half of MAX_DPB. Because, upper half is for sub_view + */ + if (ctx->multi_view_enable) + max_dpb = MFC_MAX_DPBS / 2; + + /* case 1: dpb has same address with vb index */ + if (mfc_buf->paddr == dec->dpb[mfc_buf->vb.vb2_buf.index].paddr && index < max_dpb) { + mfc_ctx_debug(2, "[DPB] vb index [%d] %#llx has same address\n", + mfc_buf->vb.vb2_buf.index, mfc_buf->paddr); + index = mfc_buf->vb.vb2_buf.index; + return index; + } + + /* case 2: dpb has same address with referenced buffer */ + used = dec->dynamic_used; + if (used) { + for (i = __ffs(used); i < max_dpb;) { + if (mfc_buf->paddr == dec->dpb[i].paddr) { + mfc_ctx_debug(2, "[DPB] index [%d][%d] %#llx is referenced\n", + mfc_buf->vb.vb2_buf.index, i, mfc_buf->paddr); + index = i; + return index; + } + used &= ~(1UL << i); + if (used == 0) + break; + i = __ffs(used); + } + } + + /* case 3: allocate new dpb index */ + dpb_table_used = dec->dpb_table_used; + /* When multi_view_enable(MV-HEVC), upper half bits should be 1 not to be assigned. */ + if (ctx->multi_view_enable) + dpb_table_used = dec->dpb_table_used | 0xFFFFFFFF00000000; + if (dpb_table_used == ~0UL) { + mfc_ctx_err("[DPB] index is full\n"); + return 0; + } + index = __ffs(~dpb_table_used); + + return index; +} + +static void __mfc_update_base_addr_dpb(struct mfc_ctx *ctx, struct mfc_buf *buf, + int index) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw; + size_t offset = 0; + int i; + + if (ctx->dst_fmt->mem_planes == 1) { + raw = &ctx->raw_buf; + for (i = 0; i < ctx->dst_fmt->num_planes; i++) { + buf->addr[0][i] = dec->dpb[index].addr[0] + offset; + offset += raw->plane_size[i]; + } + } else { + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) + buf->addr[0][i] = dec->dpb[index].addr[i]; + } + + mfc_ctx_debug(2, "[DPB] index [%d] daddr plane[0] %#llx [1] %#llx [2] %#llx\n", + index, buf->addr[0][0], buf->addr[0][1], buf->addr[0][2]); +} + +static int __mfc_update_dpb_fd(struct mfc_ctx *ctx, struct vb2_buffer *vb, int index) +{ + struct mfc_dec *dec = ctx->dec_priv; + + if (dec->dpb[index].queued) { + mfc_ctx_err("[REFINFO] DPB[%d] is already queued\n", index); + return -EINVAL; + } + + if (dec->dpb[index].fd[0] == vb->planes[0].m.fd) + mfc_ctx_debug(3, "[REFINFO] same dma_buf has same fd\n"); + + if (dec->dpb[index].new_fd != -1) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[index].fd[0]; + dec->refcnt++; + dec->dpb[index].fd[0] = dec->dpb[index].new_fd; + } + + dec->dpb[index].new_fd = vb->planes[0].m.fd; + mfc_ctx_debug(3, "[REFINFO] index %d update fd: %d -> %d after release\n", + vb->index, dec->dpb[index].fd[0], + dec->dpb[index].new_fd); + + return 0; +} + +static void __mfc_store_dynamic_dpb(struct mfc_ctx *ctx, struct mfc_dec *dec, struct vb2_buffer *vb) +{ + struct mfc_buf *mfc_buf; + unsigned long flags; + int index, plane, ret = 0; + + mfc_buf = vb_to_mfc_buf(vb); + mfc_buf->used = 0; + + mutex_lock(&dec->dpb_mutex); + mfc_buf->dpb_index = __mfc_assign_dpb_index(ctx, mfc_buf); + mfc_ctx_debug(2, "[DPB] DPB vb_index %d -> dpb_index %d addr %#llx (used: %#lx)\n", + vb->index, mfc_buf->dpb_index, mfc_buf->addr[0][0], dec->dynamic_used); + + index = mfc_buf->dpb_index; + if (index > dec->last_dpb_max_index) { + mfc_ctx_debug(3, "[DPB] last dpb max index update %d -> %d\n", + dec->last_dpb_max_index, index); + if (index > (dec->last_dpb_max_index + 1)) { + mfc_ctx_err("[DPB] wrong dpb max index: %d max: %d\n", + index, dec->last_dpb_max_index); + MFC_TRACE_CTX("wrong dpb max index: %d max: %d\n", + index, dec->last_dpb_max_index); + } + dec->last_dpb_max_index = index; + } + + if (!dec->dpb[index].mapcnt) { + mfc_get_iovmm(ctx, vb, dec->dpb); + } else { + if (dec->dpb[index].paddr == mfc_buf->paddr) { + mfc_ctx_debug(2, "[DPB] DPB[%d] is same %#llx(used: %#lx)\n", + index, dec->dpb[index].paddr, dec->dynamic_used); + ret = __mfc_update_dpb_fd(ctx, vb, index); + } else { + mfc_ctx_err("[DPB] wrong assign dpb index\n"); + } + } + + if (ret) { + /* + * Handling exception case that + * the queued buffer is same with already queued buffer's paddr. + * Driver cannot use that buffer so moves it to err_buf_queue + * and will dequeue in ISR. + */ + mutex_unlock(&dec->dpb_mutex); + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + list_add_tail(&mfc_buf->list, &ctx->err_buf_queue.head); + ctx->err_buf_queue.count++; + mfc_ctx_debug(2, "[DPB] DPB[%d][%d] fd: %d will be not used %#llx %s %s (%d)\n", + mfc_buf->vb.vb2_buf.index, index, + mfc_buf->vb.planes[0].m.fd, mfc_buf->addr[0][0], + (dec->dynamic_used & (1UL << index)) ? "ref" : "no-ref", + dec->dpb[index].queued ? "q" : "dq", + ctx->err_buf_queue.count); + MFC_TRACE_CTX("unused DPB[%d][%d] fd: %d %#llx %s %s (%d)\n", + mfc_buf->vb.vb2_buf.index, index, + mfc_buf->vb.planes[0].m.fd, mfc_buf->addr[0][0], + (dec->dynamic_used & (1UL << index)) ? "ref" : "no-ref", + dec->dpb[index].queued ? "q" : "dq", + ctx->err_buf_queue.count); + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); + return; + } + + __mfc_update_base_addr_dpb(ctx, mfc_buf, index); + + dec->dpb[index].size = 0; + for (plane = 0; plane < vb->num_planes; ++plane) + dec->dpb[index].size += vb->planes[plane].length; + + dec->dpb[index].queued = 1; + dec->dpb_table_used |= (1UL << index); + mutex_unlock(&dec->dpb_mutex); + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + list_add_tail(&mfc_buf->list, &ctx->dst_buf_queue.head); + ctx->dst_buf_queue.count++; + set_bit(index, &dec->queued_dpb); + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +/* Add dst buffer in dst_buf_queue */ +void mfc_store_dpb(struct mfc_ctx *ctx, struct vb2_buffer *vb) +{ + struct mfc_dec *dec; + + dec = ctx->dec_priv; + if (!dec) { + mfc_ctx_err("[DPB] no mfc decoder to run\n"); + return; + } + + __mfc_store_dynamic_dpb(ctx, dec, vb); +} + +void mfc_dec_drc_find_del_buf(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core *core = core_ctx->core; + struct mfc_buf *dst_mb; + int i; + + if (!dec || dec->disp_drc.disp_res_change) + return; + + dst_mb = mfc_get_del_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) + return; + + mfc_info("[DRC] already stopped and dqbuf with DRC\n"); + i = dst_mb->vb.vb2_buf.index; + dst_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; + + mfc_clear_mb_flag(dst_mb); + dst_mb->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_ERROR); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[i]) < 0) + mfc_err("[DRC] failed in core_get_buf_ctrls\n"); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[i], + V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, + MFC_REG_DEC_STATUS_DECODING_EMPTY); + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[i], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, UNUSED_TAG); + + ctx->wait_state = WAIT_G_FMT | WAIT_STOP; + mfc_debug(2, "[DRC] Decoding waiting again! : %d\n", ctx->wait_state); + MFC_TRACE_CTX("[DRC] wait again\n"); + vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h new file mode 100644 index 000000000000..055e7a23a527 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_queue.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_QUEUE_H +#define __MFC_QUEUE_H __FILE__ + +#include "mfc_common.h" + +/** + * enum mfc_queue_used_type + */ +enum mfc_queue_used_type { + MFC_BUF_NO_TOUCH_USED = -1, + MFC_BUF_RESET_USED = 0, + MFC_BUF_SET_USED = 1, +}; + +/** + * enum mfc_queue_top_type + */ +enum mfc_queue_top_type { + MFC_QUEUE_ADD_BOTTOM = 0, + MFC_QUEUE_ADD_TOP = 1, +}; + +static inline unsigned int mfc_get_queue_count(spinlock_t *plock, struct mfc_buf_queue *queue) +{ + unsigned long flags; + unsigned int ret = 0; + + spin_lock_irqsave(plock, flags); + ret = queue->count; + spin_unlock_irqrestore(plock, flags); + + return ret; +} + +static inline int mfc_is_queue_count_same(spinlock_t *plock, + struct mfc_buf_queue *queue, + unsigned int value) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(plock, flags); + if (queue->count == value) + ret = 1; + spin_unlock_irqrestore(plock, flags); + + return ret; +} + +static inline int mfc_is_queue_count_greater(spinlock_t *plock, + struct mfc_buf_queue *queue, + unsigned int value) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(plock, flags); + if (queue->count > value) + ret = 1; + spin_unlock_irqrestore(plock, flags); + + return ret; +} + +static inline void mfc_init_queue(struct mfc_buf_queue *queue) +{ + INIT_LIST_HEAD(&queue->head); + queue->count = 0; +} + +static inline void mfc_create_queue(struct mfc_buf_queue *queue) +{ + mfc_init_queue(queue); +} + +static inline void mfc_delete_queue(struct mfc_buf_queue *queue) +{ + mfc_init_queue(queue); +} + +void mfc_add_tail_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + struct mfc_buf *mfc_buf); + +struct mfc_buf *mfc_get_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used); + +struct mfc_buf *mfc_get_buf_no_used(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used); + +struct mfc_buf *mfc_get_del_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + enum mfc_queue_used_type used); + +struct mfc_buf *mfc_get_del_if_consumed(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + unsigned int consumed, + unsigned int min_bytes, + int err, + int *deleted); + +struct mfc_buf *mfc_get_move_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, + enum mfc_queue_used_type used, + enum mfc_queue_top_type top); + +struct mfc_buf *mfc_get_move_buf_used(struct mfc_ctx *ctx, + struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue); + +struct mfc_buf *mfc_find_first_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + dma_addr_t addr); + +struct mfc_buf *mfc_find_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + dma_addr_t addr); + +struct mfc_buf *mfc_find_del_buf(struct mfc_ctx *ctx, + struct mfc_buf_queue *queue, + dma_addr_t addr); + +void mfc_move_buf_all(struct mfc_ctx *ctx, + struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, + enum mfc_queue_top_type top); + +void mfc_return_buf_to_ready_queue(struct mfc_ctx *ctx, + struct mfc_buf_queue *maincore_queue, + struct mfc_buf_queue *subcore_queue); + +void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue); + +void mfc_print_dpb_queue(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec); +void mfc_print_dpb_queue_with_lock(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec); +int mfc_get_available_dpb_count(struct mfc_core_ctx *core_ctx); +struct mfc_buf *mfc_search_for_dpb(struct mfc_core_ctx *core_ctx); + +void mfc_store_dpb(struct mfc_ctx *ctx, struct vb2_buffer *vb); + +void mfc_dec_drc_find_del_buf(struct mfc_core_ctx *core_ctx); +#endif /* __MFC_QUEUE_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h index f965a2e440c0..320dc96a40ed 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h @@ -116,6 +116,47 @@ static inline int mfc_is_decoder_node(enum mfc_node_type node) return 0; } +static inline void mfc_clear_mb_flag(struct mfc_buf *mfc_buf) +{ + mfc_buf->flag = 0; +} + +static inline u32 mfc_dec_get_strm_size(struct mfc_ctx *ctx, struct mfc_buf *src_mb) +{ + struct vb2_plane *vb_plane; + struct mfc_dec *dec = ctx->dec_priv; + unsigned int strm_size; + + /* + * struct v4l2_plane data_offset is included in bytesused. + * So the size of image is bytesused - data_offset from start of the plane. + * And the dec->consumed is cumulate-decoded size. + */ + vb_plane = &src_mb->vb.vb2_buf.planes[0]; + if (!vb_plane->bytesused) { + strm_size = 0; + } else if (vb_plane->bytesused > vb_plane->data_offset) { + strm_size = vb_plane->bytesused - vb_plane->data_offset; + } else { + strm_size = vb_plane->bytesused; + mfc_ctx_info("[STREAM] invalid offset (bytesused %d, data_offset: %d)\n", + vb_plane->bytesused, vb_plane->data_offset); + } + + if (dec->consumed) { + if (strm_size > dec->consumed) { + strm_size -= dec->consumed; + } else { + mfc_ctx_info("[STREAM] invalid consumed (strm_size: %d, consumed: %d)", + strm_size, dec->consumed); + } + } + + mfc_ctx_debug(2, "[STREAM] strm_size: %d (bytesused %d, data_offset %d, consumed %d)\n", + strm_size, vb_plane->bytesused, vb_plane->data_offset, dec->consumed); + + return strm_size; +} /* Meerkat interval */ #define MEERKAT_TICK_INTERVAL 1000 /* After how many executions meerkat should assume lock up */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035606epcas5p3c38c2ba8148bd90a56415f544c5072f1@epcas5p3.samsung.com>]
* [PATCH 11/29] media: mfc: Add rate‑calculation framework and memory utilities [not found] ` <CGME20250930035606epcas5p3c38c2ba8148bd90a56415f544c5072f1@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Implement runtime rate‑calculation (timestamp handling, framerate/BPS estimation, QoS adjustments, performance checks) with new helper APIs. - Add utility layer for format validation, resolution/stride/size computation, DPB size, address mapping, and view‑buffer bookkeeping. - Export functions used by decoder/encoder paths for dynamic QoS and memory handling. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../samsung/exynos-mfc/base/mfc_mem.c | 187 ++++++ .../samsung/exynos-mfc/base/mfc_mem.h | 44 ++ .../exynos-mfc/base/mfc_rate_calculate.c | 612 ++++++++++++++++++ .../exynos-mfc/base/mfc_rate_calculate.h | 100 +++ .../samsung/exynos-mfc/base/mfc_utils.c | 284 ++++++++ .../samsung/exynos-mfc/base/mfc_utils.h | 214 +++++- 7 files changed, 1441 insertions(+), 2 deletions(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index 5353289fa810..bd5f80953bab 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -19,7 +19,7 @@ exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o #Plugin control layer #Plugin HW access layer #Common base layer -exynos_mfc-y += base/mfc_queue.o +exynos_mfc-y += base/mfc_rate_calculate.o base/mfc_queue.o base/mfc_utils.o exynos_mfc-y += base/mfc_buf.o base/mfc_mem.o #Tracing # exynos_mfc-y += trace/mfc_trace_points.o diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c index 17cc1d793cbc..c99c1c081b0e 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c @@ -18,6 +18,70 @@ #include "mfc_mem.h" +struct vb2_mem_ops *mfc_mem_ops(void) +{ + return (struct vb2_mem_ops *)&vb2_dma_sg_memops; +} + +int mfc_mem_get_user_shared_handle(struct mfc_ctx *ctx, + struct mfc_user_shared_handle *handle, char *name) +{ + struct iosys_map map = IOSYS_MAP_INIT_VADDR(NULL); + int ret = 0; + + handle->dma_buf = dma_buf_get(handle->fd); + if (IS_ERR(handle->dma_buf)) { + mfc_ctx_err("[MEMINFO][SH][%s] Failed to import fd\n", name); + ret = PTR_ERR(handle->dma_buf); + goto import_dma_fail; + } + + if (handle->dma_buf->size < handle->data_size) { + mfc_ctx_err("[MEMINFO][SH][%s] User-provided dma_buf size(%ld) is smaller than required size(%ld)\n", + name, handle->dma_buf->size, handle->data_size); + ret = -EINVAL; + goto dma_buf_size_fail; + } + ret = dma_buf_vmap_unlocked(handle->dma_buf, &map); + if (ret) { + mfc_ctx_err("[MEMINFO][SH][%s] Failed to get kernel virtual address\n", name); + ret = -EINVAL; + goto map_kernel_fail; + } + + handle->vaddr = map.vaddr; + mfc_ctx_debug(2, "[MEMINFO][SH][%s] shared handle fd: %d, vaddr: 0x%p, buf size: %zu, data size: %zu\n", + name, handle->fd, handle->vaddr, + handle->dma_buf->size, handle->data_size); + + return 0; + +map_kernel_fail: + handle->vaddr = NULL; +dma_buf_size_fail: + dma_buf_put(handle->dma_buf); +import_dma_fail: + handle->dma_buf = NULL; + handle->fd = -1; + return ret; +} + +void mfc_mem_cleanup_user_shared_handle(struct mfc_ctx *ctx, + struct mfc_user_shared_handle *handle) +{ + struct iosys_map map = IOSYS_MAP_INIT_VADDR(handle->vaddr); + + if (handle->vaddr) + dma_buf_vunmap_unlocked(handle->dma_buf, &map); + if (handle->dma_buf) + dma_buf_put(handle->dma_buf); + + handle->data_size = 0; + handle->dma_buf = NULL; + handle->vaddr = NULL; + handle->fd = -1; +} + static int mfc_mem_fw_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf) { #if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) @@ -334,6 +398,26 @@ void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *speci } } +void mfc_bufcon_put_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int plane) +{ + int i; + + for (i = 0; i < mfc_buf->num_valid_bufs; i++) { + if (mfc_buf->addr[i][plane]) { + mfc_ctx_debug(4, "[BUFCON] put batch buf addr[%d][%d]: 0x%08llx\n", + i, plane, mfc_buf->addr[i][plane]); + } + if (mfc_buf->attachments[i][plane]) + dma_buf_detach(mfc_buf->dmabufs[i][plane], mfc_buf->attachments[i][plane]); + if (mfc_buf->dmabufs[i][plane]) + dma_buf_put(mfc_buf->dmabufs[i][plane]); + + mfc_buf->addr[i][plane] = 0; + mfc_buf->attachments[i][plane] = NULL; + mfc_buf->dmabufs[i][plane] = NULL; + } +} + void mfc_put_iovmm(struct mfc_ctx *ctx, struct dpb_table *dpb, int num_planes, int index) { int i; @@ -524,6 +608,81 @@ void mfc_get_iovmm(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct dpb_table mfc_put_iovmm(ctx, dpb, mem_get_count, sub_view_index); } +void mfc_init_dpb_table(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + int index, plane; + + mutex_lock(&dec->dpb_mutex); + for (index = 0; index < MFC_MAX_DPBS; index++) { + for (plane = 0; plane < MFC_MAX_PLANES; plane++) { + dec->dpb[index].fd[plane] = -1; + dec->dpb[index].addr[plane] = 0; + dec->dpb[index].attach[plane] = NULL; + dec->dpb[index].dmabufs[plane] = NULL; + } + dec->dpb[index].new_fd = -1; + dec->dpb[index].mapcnt = 0; + dec->dpb[index].queued = 0; + } + mutex_unlock(&dec->dpb_mutex); +} + +void mfc_cleanup_iovmm(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + int i; + + mutex_lock(&dec->dpb_mutex); + + for (i = 0; i < MFC_MAX_DPBS; i++) { + dec->dpb[i].paddr = 0; + dec->dpb[i].ref = 0; + if (dec->dpb[i].mapcnt == 0) { + continue; + } else if (dec->dpb[i].mapcnt == 1) { + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, i); + } else { + mfc_ctx_err("[IOVMM] DPB[%d] %#llx invalid mapcnt %d\n", + i, dec->dpb[i].addr[0], dec->dpb[i].mapcnt); + MFC_TRACE_CTX("DPB[%d] %#llx invalid mapcnt %d\n", + i, dec->dpb[i].addr[0], dec->dpb[i].mapcnt); + } + } + + mutex_unlock(&dec->dpb_mutex); +} + +void mfc_cleanup_iovmm_except_used(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + int i; + + mutex_lock(&dec->dpb_mutex); + + for (i = 0; i < MFC_MAX_DPBS; i++) { + if (dec->dynamic_used & (1UL << i)) { + continue; + } else { + dec->dpb[i].paddr = 0; + dec->dpb[i].ref = 0; + if (dec->dpb[i].mapcnt == 0) { + continue; + } else if (dec->dpb[i].mapcnt == 1) { + dec->dpb_table_used &= ~(1UL << i); + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, i); + } else { + mfc_ctx_err("[IOVMM] DPB[%d] %#llx invalid mapcnt %d\n", + i, dec->dpb[i].addr[0], dec->dpb[i].mapcnt); + MFC_TRACE_CTX("DPB[%d] %#llx invalid mapcnt %d\n", + i, dec->dpb[i].addr[0], dec->dpb[i].mapcnt); + } + } + } + + mutex_unlock(&dec->dpb_mutex); +} + void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf) { /* Project that do not support iova reservation */ @@ -712,6 +871,34 @@ int mfc_iommu_map_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf return 0; } +void mfc_check_iova(struct mfc_dev *dev) +{ + struct mfc_platdata *pdata = dev->pdata; + struct mfc_ctx *ctx; + unsigned long total_iova = 0; + + if (!pdata->iova_threshold) + return; + + /* + * The number of extra dpb is 8 + * OMX: extra buffer 5, platform buffer 3 + * Codec2: platform buffer 8 + */ + list_for_each_entry(ctx, &dev->ctx_list, list) + total_iova += (ctx->raw_buf.total_plane_size * + (ctx->dpb_count + MFC_EXTRA_DPB + 3)) / SZ_1K; + + if (total_iova > (pdata->iova_threshold * SZ_1K)) + dev->skip_lazy_unmap = 1; + else + dev->skip_lazy_unmap = 0; + + mfc_dev_debug(2, "[LAZY_UNMAP] Now the IOVA for DPB is %lu/%uMB, LAZY_UNMAP %s\n", + total_iova / SZ_1K, pdata->iova_threshold, + dev->skip_lazy_unmap ? "disable" : "enable"); +} + /* DMA memory related helper functions */ static void mfc_memdev_release(struct device *dev) { diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h index 3deeb0d611a0..3bd40dd0a0ed 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h @@ -66,6 +66,35 @@ static inline size_t mfc_mem_get_sg_length(struct mfc_dev *dev, struct sg_table return size; } +static inline void mfc_mem_buf_prepare(struct vb2_buffer *vb, int stream) +{ + int i; + enum dma_data_direction dir; + struct dma_buf *dbuf; + + dir = V4L2_TYPE_IS_OUTPUT(vb->type) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE; + + for (i = 0; i < vb->num_planes; i++) { + dbuf = vb->planes[i].dbuf; + dma_buf_end_cpu_access(dbuf, dir); + } +} + +static inline void mfc_mem_buf_finish(struct vb2_buffer *vb, int stream) +{ + int i; + struct dma_buf *dbuf; + + if (V4L2_TYPE_IS_OUTPUT(vb->type)) + return; + + for (i = 0; i < vb->num_planes; i++) { + dbuf = vb->planes[i].dbuf; + dma_buf_begin_cpu_access(dbuf, DMA_FROM_DEVICE); + } +} + static inline void mfc_print_dpb_table(struct mfc_ctx *ctx) { struct mfc_dec *dec = ctx->dec_priv; @@ -95,16 +124,31 @@ static inline void mfc_print_dpb_table(struct mfc_ctx *ctx) dec->dpb[i].queued ? "Q" : "DQ"); } } + +struct vb2_mem_ops *mfc_mem_ops(void); + +int mfc_mem_get_user_shared_handle(struct mfc_ctx *ctx, + struct mfc_user_shared_handle *handle, char *name); +void mfc_mem_cleanup_user_shared_handle(struct mfc_ctx *ctx, + struct mfc_user_shared_handle *handle); + int mfc_mem_special_buf_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf); void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *special_buf); +void mfc_bufcon_put_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int plane); + void mfc_put_iovmm(struct mfc_ctx *ctx, struct dpb_table *dpb, int num_planes, int index); void mfc_get_iovmm(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct dpb_table *dpb); +void mfc_init_dpb_table(struct mfc_ctx *ctx); +void mfc_cleanup_iovmm(struct mfc_ctx *ctx); +void mfc_cleanup_iovmm_except_used(struct mfc_ctx *ctx); + void mfc_iova_pool_free(struct mfc_dev *dev, struct mfc_special_buf *buf); int mfc_iova_pool_alloc(struct mfc_dev *dev, struct mfc_special_buf *buf); int mfc_iova_pool_init(struct mfc_dev *dev); int mfc_iommu_map_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf); +void mfc_check_iova(struct mfc_dev *dev); int mfc_configure_dma_memory(struct mfc_dev *mfc_dev); void mfc_unconfigure_dma_memory(struct mfc_dev *mfc_dev); diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c new file mode 100644 index 000000000000..94a555c900d7 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_rate_calculate.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/err.h> +#include <linux/sort.h> + +#include "mfc_utils.h" + +#define COL_FRAME_RATE 0 +#define COL_FRAME_INTERVAL 1 + +#define MFC_MAX_INTERVAL (2 * USEC_PER_SEC) + +/* + * A framerate table determines framerate by the interval(us) of each frame. + * Framerate is not accurate, just rough value to separate overload section. + * Base line of each section are selected from middle value. + * 25fps(40000us), 40fps(25000us), 80fps(12500us) + * 144fps(6940us), 205fps(4860us), 320fps(3125us) + * + * interval(us) | 0 3125 4860 6940 12500 25000 40000 + * framerate | 480fps | 240fps | 180fps | 120fps | 60fps | 30fps | + * 24fps + */ +static unsigned long framerate_table[][2] = { + { 24000, 40000 }, + { 30000, 25000 }, + { 60000, 12500 }, + { 120000, 6940 }, + { 180000, 4860 }, + { 240000, 3125 }, + { 480000, 0 }, +}; + +/* + * display_framerate_table determines framerate by the queued interval. + * It supports 30fps, 60fps, 120fps as display framerate. + * Base line of each section is selected from middle value. + * 25fps(40000us), 40fps(25000us), 80fps(12500us) + * + * interval(us) | 12500 25000 40000 + * disp framerate | 120fps | 60fps | 30fps | 24fps + */ +static unsigned long display_framerate_table[][2] = { + { 24000, 40000 }, + { 30000, 25000 }, + { 60000, 12500 }, + { 120000, 0 }, +}; + +inline unsigned long mfc_rate_timespec64_diff(struct timespec64 *to, + struct timespec64 *from) +{ + unsigned long interval_nsec = (to->tv_sec * NSEC_PER_SEC + to->tv_nsec) + - (from->tv_sec * NSEC_PER_SEC + from->tv_nsec); + + if (interval_nsec <= 0) + interval_nsec = MFC_MAX_INTERVAL * 1000; + + return interval_nsec / 1000; +} + +static int __mfc_rate_ts_sort(const void *p0, const void *p1) +{ + const int *t0 = p0, *t1 = p1; + + /* ascending sort */ + if (*t0 < *t1) + return -1; + else if (*t0 > *t1) + return 1; + + return 0; +} + +static int __mfc_rate_get_ts_min_interval(struct mfc_ctx *ctx, struct mfc_ts_control *ts) +{ + int tmp[MAX_TIME_INDEX]; + + if (!ts->ts_is_full) + return 0; + + memcpy(&tmp[0], &ts->ts_interval_array[0], MAX_TIME_INDEX * sizeof(int)); + sort(tmp, MAX_TIME_INDEX, sizeof(int), __mfc_rate_ts_sort, NULL); + + return tmp[0]; +} + +static int __mfc_rate_get_ts_interval(struct mfc_ctx *ctx, struct mfc_ts_control *ts, int type) +{ + int tmp[MAX_TIME_INDEX]; + int n, i, val = 0, sum = 0; + + n = ts->ts_is_full ? MAX_TIME_INDEX : ts->ts_count; + + memcpy(&tmp[0], &ts->ts_interval_array[0], n * sizeof(int)); + sort(tmp, n, sizeof(int), __mfc_rate_ts_sort, NULL); + + if (type == MFC_TS_SRC) { + /* apply median filter for selecting ts interval */ + val = (n <= 2) ? tmp[0] : tmp[n / 2]; + } else if ((type == MFC_TS_DST_Q) || (type == MFC_TS_SRC_Q) || (type == MFC_TS_DST_DQ)) { + /* apply average for selecting ts interval except min,max */ + if (n < 3) + return 0; + for (i = 1; i < (n - 1); i++) + sum += tmp[i]; + val = sum / (n - 2); + } else { + mfc_ctx_err("[TS] Wrong timestamp type %d\n", type); + } + + if (ctx->dev->debugfs.debug_ts == 1) { + mfc_ctx_info("==============[%s%s%s][TS] interval (sort)==============\n", + (type & 0x1) ? "SRC" : "DST", (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : ""); + for (i = 0; i < n; i++) + mfc_ctx_info("[%s%s%s][TS] interval [%d] = %d\n", + (type & 0x1) ? "SRC" : "DST", + (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : "", i, tmp[i]); + mfc_ctx_info("[%s%s%s][TS] get interval %d\n", + (type & 0x1) ? "SRC" : "DST", + (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : "", val); + } + + return val; +} + +static unsigned long __mfc_rate_get_framerate_by_interval(int interval, int type) +{ + unsigned long (*table)[2]; + unsigned long i; + int size; + + /* if the interval is too big (2sec), framerate set to 0 */ + if (interval > MFC_MAX_INTERVAL || interval <= 0) + return 0; + + if (type == MFC_TS_SRC || type == MFC_TS_SRC_Q || type == MFC_TS_DST_DQ) { + table = framerate_table; + size = ARRAY_SIZE(framerate_table); + } else if (type == MFC_TS_DST_Q) { + table = display_framerate_table; + size = ARRAY_SIZE(display_framerate_table); + } else { + return 0; + } + + for (i = 0; i < size; i++) { + if (interval > table[i][COL_FRAME_INTERVAL]) + return table[i][COL_FRAME_RATE]; + } + + return 0; +} + +int mfc_rate_get_bps_section_by_bps(struct mfc_dev *dev, int kbps, int max_kbps) +{ + struct mfc_platdata *pdata = dev->pdata; + int i, max_freq_idx; + int freq_ratio, bps_interval, prev_interval = 0; + + max_freq_idx = pdata->num_mfc_freq - 1; + if (kbps > max_kbps) { + mfc_dev_debug(4, "[BPS] overspec bps %d > %d\n", kbps, max_kbps); + return max_freq_idx; + } + + for (i = 0; i < pdata->num_mfc_freq; i++) { + freq_ratio = pdata->mfc_freqs[i] * 100 / pdata->mfc_freqs[max_freq_idx]; + bps_interval = max_kbps * freq_ratio / 100; + mfc_dev_debug(4, "[BPS] MFC freq lv%d, %uKHz covered: %d ~ %dkbps (now: %dkbps)\n", + i, pdata->mfc_freqs[i], prev_interval, bps_interval, kbps); + if (kbps <= bps_interval) { + mfc_dev_debug(3, "[BPS] MFC freq lv%d, %uKHz is needed: %d ~ %dkbps\n", + i, pdata->mfc_freqs[i], + prev_interval, bps_interval); + return i; + } + prev_interval = bps_interval; + } + + /* Not changed the MFC freq according to BPS */ + return 0; +} + +/* Return the minimum interval between previous and next entry */ +static int __mfc_rate_get_interval(struct list_head *head, struct list_head *entry) +{ + unsigned long prev_interval = MFC_MAX_INTERVAL, next_interval = MFC_MAX_INTERVAL; + struct mfc_timestamp *prev_ts, *next_ts, *curr_ts; + int ret = 0; + + curr_ts = list_entry(entry, struct mfc_timestamp, list); + + if (entry->prev != head) { + prev_ts = list_entry(entry->prev, struct mfc_timestamp, list); + prev_interval = mfc_rate_timespec64_diff(&curr_ts->timestamp, + &prev_ts->timestamp); + if (prev_interval > MFC_MAX_INTERVAL) + prev_interval = MFC_MAX_INTERVAL; + } + + if (entry->next != head) { + next_ts = list_entry(entry->next, struct mfc_timestamp, list); + next_interval = mfc_rate_timespec64_diff(&next_ts->timestamp, + &curr_ts->timestamp); + if (next_interval > MFC_MAX_INTERVAL) + next_interval = MFC_MAX_INTERVAL; + } + + ret = (prev_interval < next_interval) ? prev_interval : next_interval; + return ret; +} + +static int __mfc_rate_add_timestamp(struct mfc_ctx *ctx, struct mfc_ts_control *ts, + struct timespec64 *time, struct list_head *head) +{ + int replace_entry = 0; + struct mfc_timestamp *curr_ts = &ts->ts_array[ts->ts_count]; + struct mfc_timestamp *adj_ts = NULL; + + if (ts->ts_is_full) { + /* Replace the entry if list of array[ts_count] is same as entry */ + if (&curr_ts->list == head) + replace_entry = 1; + else + list_del(&curr_ts->list); + } + + memcpy(&curr_ts->timestamp, time, sizeof(*time)); + if (!replace_entry) + list_add(&curr_ts->list, head); + curr_ts->interval = __mfc_rate_get_interval(&ts->ts_list, &curr_ts->list); + curr_ts->index = ts->ts_count; + + ts->ts_interval_array[ts->ts_count] = curr_ts->interval; + ts->ts_count++; + + if (ts->ts_count == MAX_TIME_INDEX) { + ts->ts_is_full = 1; + ts->ts_count %= MAX_TIME_INDEX; + } + + /* + * When timestamp is updated, the interval of adjacent timestamp can be changed. + * So, update this value of prev and next in list. + */ + if (curr_ts->list.next != &ts->ts_list) { + adj_ts = list_entry(curr_ts->list.next, struct mfc_timestamp, list); + adj_ts->interval = __mfc_rate_get_interval(&ts->ts_list, &adj_ts->list); + ts->ts_interval_array[adj_ts->index] = adj_ts->interval; + } + if (curr_ts->list.prev != &ts->ts_list) { + adj_ts = list_entry(curr_ts->list.prev, struct mfc_timestamp, list); + adj_ts->interval = __mfc_rate_get_interval(&ts->ts_list, &adj_ts->list); + ts->ts_interval_array[adj_ts->index] = adj_ts->interval; + } + + return 0; +} + +void mfc_rate_reset_ts_list(struct mfc_ts_control *ts) +{ + struct mfc_timestamp *temp_ts = NULL; + unsigned long flags; + + spin_lock_irqsave(&ts->ts_lock, flags); + + /* empty the timestamp queue */ + while (!list_empty(&ts->ts_list)) { + temp_ts = list_entry((&ts->ts_list)->next, struct mfc_timestamp, list); + list_del(&temp_ts->list); + } + + ts->ts_count = 0; + ts->ts_is_full = 0; + + spin_unlock_irqrestore(&ts->ts_lock, flags); +} + +static unsigned long __mfc_rate_get_fps_by_timestamp(struct mfc_ctx *ctx, + struct mfc_ts_control *ts, + struct timespec64 *time, int type) +{ + struct mfc_timestamp *temp_ts; + int found; + int index = 0; + int ts_is_full = ts->ts_is_full; + int interval = MFC_MAX_INTERVAL; + int min_interval = 0; + int time_diff; + unsigned long framerate; + unsigned long flags; + u64 current_time; + + spin_lock_irqsave(&ts->ts_lock, flags); + if (list_empty(&ts->ts_list)) { + __mfc_rate_add_timestamp(ctx, ts, time, &ts->ts_list); + spin_unlock_irqrestore(&ts->ts_lock, flags); + return __mfc_rate_get_framerate_by_interval(0, type); + } + found = 0; + list_for_each_entry_reverse(temp_ts, &ts->ts_list, list) { + time_diff = __mfc_timespec64_compare(time, &temp_ts->timestamp); + if (time_diff == 0) { + /* Do not add if same timestamp already exists */ + found = 1; + break; + } else if (time_diff > 0) { + /* Add this after temp_ts */ + __mfc_rate_add_timestamp(ctx, ts, time, &temp_ts->list); + found = 1; + break; + } + } + + if (!found) /* Add this at first entry */ + __mfc_rate_add_timestamp(ctx, ts, time, &ts->ts_list); + spin_unlock_irqrestore(&ts->ts_lock, flags); + + interval = __mfc_rate_get_ts_interval(ctx, ts, type); + framerate = __mfc_rate_get_framerate_by_interval(interval, type); + + if (ctx->dev->debugfs.debug_ts == 1) { + spin_lock_irqsave(&ts->ts_lock, flags); + /* Debug info */ + mfc_ctx_info("=================[%s%s%s][TS]===================\n", + (type & 0x1) ? "SRC" : "DST", (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : ""); + mfc_ctx_info("[%s%s%s][TS] New timestamp = %lld.%06ld, count = %d\n", + (type & 0x1) ? "SRC" : "DST", + (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : "", + time->tv_sec, time->tv_nsec, ts->ts_count); + + index = 0; + list_for_each_entry(temp_ts, &ts->ts_list, list) { + mfc_ctx_info("[%s%s][TS] [%d] timestamp [i:%d]: %lld.%06ld\n", + (type & 0x1) ? "SRC" : "DST", + (type & 0x2) ? "_Q" : "", + index, temp_ts->index, + temp_ts->timestamp.tv_sec, + temp_ts->timestamp.tv_nsec); + index++; + } + mfc_ctx_info("[%s%s%s][TS] Min interval = %d, It is %ld fps\n", + (type & 0x1) ? "SRC" : "DST", + (type & 0x2) ? "_Q" : "", + (type & 0x4) ? "_DQ" : "", + interval, framerate); + spin_unlock_irqrestore(&ts->ts_lock, flags); + } + + if (!ts->ts_is_full) { + if (ctx->dev->debugfs.debug_ts == 1) + mfc_ctx_info("[TS] ts doesn't full, keep %ld fps\n", ctx->framerate); + return ctx->framerate; + } + + if (!ts_is_full && type == MFC_TS_SRC) { + min_interval = __mfc_rate_get_ts_min_interval(ctx, ts); + if (min_interval) + ctx->max_framerate = + __mfc_rate_get_framerate_by_interval(min_interval, type); + else + ctx->max_framerate = 0; + + current_time = ktime_get_ns() / NSEC_PER_SEC; + if (current_time == time->tv_sec) + ctx->ktime_used = TRUE; + } + + return framerate; +} + +static int __mfc_rate_get_bps_section(struct mfc_ctx *ctx, u32 bytesused) +{ + struct mfc_dev *dev = ctx->dev; + struct list_head *head = &ctx->bitrate_list; + struct mfc_bitrate *temp_bitrate; + struct mfc_bitrate *new_bitrate = &ctx->bitrate_array[ctx->bitrate_index]; + int max_kbps; + unsigned long sum_size = 0, avg_kbits, fps; + int count = 0; + + if (ctx->bitrate_is_full) { + temp_bitrate = list_entry(head->next, struct mfc_bitrate, list); + list_del(&temp_bitrate->list); + } + + new_bitrate->bytesused = bytesused; + list_add_tail(&new_bitrate->list, head); + + list_for_each_entry(temp_bitrate, head, list) { + mfc_ctx_debug(4, "[BPS][%d] strm_size %d\n", count, temp_bitrate->bytesused); + sum_size += temp_bitrate->bytesused; + count++; + } + + if (count == 0) { + mfc_ctx_err("[BPS] There is no list for bps\n"); + return ctx->last_bps_section; + } + + ctx->bitrate_index++; + if (ctx->bitrate_index == MAX_TIME_INDEX) { + ctx->bitrate_is_full = 1; + ctx->bitrate_index %= MAX_TIME_INDEX; + } + + /* + * When there is a value of ts_is_full, + * we can trust fps(trusted fps calculated by timestamp diff). + * When fps information becomes reliable, + * we will start QoS handling by obtaining bps section. + */ + if (!ctx->src_ts.ts_is_full) + return 0; + + if (IS_MULTI_MODE(ctx)) + fps = ctx->last_framerate / 1000 / dev->num_core; + else + fps = ctx->last_framerate / 1000; + avg_kbits = ((sum_size * BITS_PER_BYTE) / count) / SZ_1K; + ctx->kbps = (int)(avg_kbits * fps); + max_kbps = dev->pdata->mfc_resource[ctx->codec_mode].max_kbps; + mfc_ctx_debug(3, "[BPS] %d kbps, average %lu Kbits per frame\n", ctx->kbps, avg_kbits); + + return mfc_rate_get_bps_section_by_bps(dev, ctx->kbps, max_kbps); +} + +void mfc_rate_update_bitrate(struct mfc_ctx *ctx, u32 bytesused) +{ + int bps_section; + + /* bitrate is updated */ + bps_section = __mfc_rate_get_bps_section(ctx, bytesused); + if (ctx->last_bps_section != bps_section) { + mfc_ctx_debug(2, "[BPS] bps section changed: %d -> %d\n", + ctx->last_bps_section, bps_section); + ctx->last_bps_section = bps_section; + ctx->update_bitrate = true; + } +} + +void mfc_rate_update_framerate(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + unsigned long framerate; + + /* 2) when src timestamp isn't full, only check operating framerate by user */ + if (!ctx->src_ts.ts_is_full) { + if (ctx->operating_framerate && ctx->operating_framerate > ctx->framerate) { + mfc_ctx_debug(2, "[QoS] operating fps changed: %ld\n", + ctx->operating_framerate); + mfc_rate_set_framerate(ctx, ctx->operating_framerate); + ctx->update_framerate = true; + return; + } + } else { + /* 3) get src framerate */ + framerate = ctx->last_framerate; + + /* 4) check display framerate */ + if (dev->pdata->display_framerate && + ctx->dst_q_ts.ts_is_full && ctx->dst_q_framerate > framerate) { + framerate = ctx->dst_q_framerate; + if (framerate != ctx->framerate) + mfc_ctx_debug(2, "[QoS] display fps %ld\n", framerate); + } + + /* 5) check operating framerate by user */ + if (ctx->operating_framerate && ctx->operating_framerate > framerate) { + framerate = ctx->operating_framerate; + if (framerate != ctx->framerate) + mfc_ctx_debug(2, "[QoS] operating fps %ld\n", framerate); + } + + /* 6) check non-real-time and undefined mode */ + if (ctx->rt == MFC_NON_RT || ctx->rt == MFC_RT_UNDEFINED) { + if (framerate < ctx->src_q_framerate) { + framerate = ctx->src_q_framerate; + if (framerate != ctx->framerate) + mfc_ctx_debug(2, + "[QoS][PRIO] (default) NRT src_q fps %ld\n", + framerate); + } + } + + if (ctx->operating_framerate == ctx->framerate && !ctx->check_src_ts_full) { + mfc_ctx_debug(2, "[QoS] src ts is full, update framerate for load balancing\n"); + ctx->check_src_ts_full = true; + ctx->update_framerate = true; + } + + if (framerate && framerate != ctx->framerate) { + mfc_ctx_debug(2, "[QoS] fps changed: %ld -> %ld, qos ratio: %d\n", + ctx->framerate, framerate, ctx->qos_ratio); + mfc_rate_set_framerate(ctx, framerate); + ctx->update_framerate = true; + } + } +} + +void mfc_rate_update_last_framerate(struct mfc_ctx *ctx, u64 timestamp) +{ + struct timespec64 time; + + time.tv_sec = timestamp / NSEC_PER_SEC; + time.tv_nsec = (timestamp - (time.tv_sec * NSEC_PER_SEC)); + + ctx->last_framerate = __mfc_rate_get_fps_by_timestamp(ctx, &ctx->src_ts, &time, MFC_TS_SRC); + if (ctx->last_framerate > MFC_MAX_FPS) + ctx->last_framerate = MFC_MAX_FPS; + + if (ctx->src_ts.ts_is_full) + ctx->last_framerate = (ctx->qos_ratio * ctx->last_framerate) / 100; +} + +void mfc_rate_update_bufq_framerate(struct mfc_ctx *ctx, int type) +{ + struct timespec64 time; + u64 timestamp; + + timestamp = ktime_get_ns(); + time.tv_sec = timestamp / NSEC_PER_SEC; + time.tv_nsec = timestamp - (time.tv_sec * NSEC_PER_SEC); + + if (type == MFC_TS_DST_Q) { + ctx->dst_q_framerate = __mfc_rate_get_fps_by_timestamp + (ctx, &ctx->dst_q_ts, &time, MFC_TS_DST_Q); + mfc_ctx_debug(5, "[QoS] dst_q_framerate = %lu\n", ctx->dst_q_framerate); + } + if (type == MFC_TS_DST_DQ) { + ctx->dst_dq_framerate = __mfc_rate_get_fps_by_timestamp + (ctx, &ctx->dst_dq_ts, &time, MFC_TS_DST_DQ); + mfc_ctx_debug(5, "[QoS] dst_dq_framerate = %lu\n", ctx->dst_dq_framerate); + } + if (type == MFC_TS_SRC_Q) { + ctx->src_q_framerate = __mfc_rate_get_fps_by_timestamp + (ctx, &ctx->src_q_ts, &time, MFC_TS_SRC_Q); + mfc_ctx_debug(5, "[QoS] src_q_framerate = %lu\n", ctx->src_q_framerate); + } +} + +void mfc_rate_reset_bufq_framerate(struct mfc_ctx *ctx) +{ + ctx->dst_q_framerate = 0; + ctx->dst_dq_framerate = 0; + ctx->src_q_framerate = 0; + + mfc_rate_reset_ts_list(&ctx->dst_q_ts); + mfc_rate_reset_ts_list(&ctx->src_q_ts); +} + +int mfc_rate_check_perf_ctx(struct mfc_ctx *ctx, int max_runtime) +{ + struct mfc_ts_control *ts; + struct timespec64 start_time, curr_time; + u64 timestamp, interval; + int op_fps, fps; + unsigned long flags; + + if (ctx->dev->debugfs.sched_perf_disable) + return 0; + + ts = &ctx->dst_dq_ts; + if (!ts->ts_is_full) + return 0; + + op_fps = ctx->operating_framerate; + if (op_fps == 0) { + op_fps = ctx->src_q_framerate; + mfc_ctx_debug(2, "[PRIO][rt %d] use fps: %d\n", ctx->rt, op_fps); + } + + /* Calculate interval from start to current time */ + timestamp = ktime_get_ns(); + curr_time.tv_sec = timestamp / NSEC_PER_SEC; + curr_time.tv_nsec = timestamp - (curr_time.tv_sec * NSEC_PER_SEC); + + spin_lock_irqsave(&ts->ts_lock, flags); + start_time = ts->ts_array[ts->ts_count].timestamp; + spin_unlock_irqrestore(&ts->ts_lock, flags); + + interval = mfc_rate_timespec64_diff(&curr_time, &start_time); + interval += max_runtime; + + fps = (((MAX_TIME_INDEX - 1) * 1000) / (interval / 1000)) * 1000; + mfc_ctx_debug(2, "[PRIO][rt %d] st %lld.%06ld, curr %lld.%06ld, interval %lld, fps %d\n", + ctx->rt, start_time.tv_sec, start_time.tv_nsec, + curr_time.tv_sec, curr_time.tv_nsec, interval, fps); + + if (fps > op_fps) { + mfc_ctx_debug(2, "[PRIO] PERF enough fps: %d, op_fps: %d\n", fps, op_fps); + return 1; + } + + mfc_ctx_debug(2, "[PRIO] PERF insufficient fps: %d, op_fps: %d\n", fps, op_fps); + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h new file mode 100644 index 000000000000..2452e6ee56dd --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_rate_calculate.h + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_RATE_CALCULATE_H +#define __MFC_RATE_CALCULATE_H __FILE__ + +#include "mfc_common.h" + +#define MFC_MIN_FPS (30000) +#define MFC_MAX_FPS (480000) +#define DEC_DEFAULT_FPS (480000) +#define ENC_DEFAULT_FPS (480000) +#define ENC_DEFAULT_CAM_CAPTURE_FPS (60000) + +inline unsigned long mfc_rate_timespec64_diff(struct timespec64 *to, + struct timespec64 *from); +void mfc_rate_reset_ts_list(struct mfc_ts_control *ts); +int mfc_rate_get_bps_section_by_bps(struct mfc_dev *dev, int kbps, int max_kbps); +void mfc_rate_update_bitrate(struct mfc_ctx *ctx, u32 bytesused); +void mfc_rate_update_framerate(struct mfc_ctx *ctx); +void mfc_rate_update_last_framerate(struct mfc_ctx *ctx, u64 timestamp); +void mfc_rate_update_bufq_framerate(struct mfc_ctx *ctx, int type); +void mfc_rate_reset_bufq_framerate(struct mfc_ctx *ctx); +int mfc_rate_check_perf_ctx(struct mfc_ctx *ctx, int max_runtime); + +static inline int __mfc_timespec64_compare(const struct timespec64 *lhs, + const struct timespec64 *rhs) +{ + if (lhs->tv_sec < rhs->tv_sec) + return -1; + if (lhs->tv_sec > rhs->tv_sec) + return 1; + return lhs->tv_nsec - rhs->tv_nsec; +} + +static inline void mfc_rate_reset_framerate(struct mfc_ctx *ctx) +{ + if (ctx->type == MFCINST_DECODER) + ctx->framerate = DEC_DEFAULT_FPS; + + mfc_ctx_debug(3, "[QoS] reset ctx->framrate: %lu\n", ctx->framerate); +} + +static inline void mfc_rate_reset_last_framerate(struct mfc_ctx *ctx) +{ + ctx->last_framerate = 0; +} + +static inline void mfc_rate_set_framerate(struct mfc_ctx *ctx, int rate) +{ + ctx->framerate = rate; + + mfc_ctx_debug(3, "[QoS] set ctx->framerate: %lu\n", ctx->framerate); +} + +static inline int mfc_rate_get_framerate(struct mfc_ctx *ctx) +{ + unsigned long framerate = ctx->last_framerate; + + if (!framerate) + framerate = ctx->framerate; + + if (ctx->operating_framerate > framerate) + return ctx->operating_framerate; + else + return framerate; +} + +static inline unsigned long mfc_rate_get_rt_framerate(struct mfc_ctx *ctx, enum mfc_real_time rt) +{ + unsigned long framerate; + + framerate = ctx->operating_framerate; + + if (rt == MFC_RT_UNDEFINED || rt == MFC_NON_RT) { + framerate = ctx->framerate; + } else { + if (ctx->src_ts.ts_is_full) + framerate = mfc_rate_get_framerate(ctx); + } + + if (framerate == 0) + framerate = MFC_MIN_FPS; + else if (framerate > MFC_MAX_FPS) + framerate = MFC_MAX_FPS; + + mfc_ctx_debug(3, "[QoS] rt framerate: %lu\n", framerate); + + return framerate; +} + +#endif /* __MFC_RATE_CALCULATE_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c new file mode 100644 index 000000000000..b0698b2bb0c0 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_utils.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_utils.h" +#include "mfc_mem.h" +#include "mfc_queue.h" + +static struct mfc_resolution mfc_res[] = { + { + .width = 0, + .height = 0, + }, + { + .width = 1920, + .height = 1088, + }, + { + .width = 4096, + .height = 2176, + }, + { + .width = 8192, + .height = 4352, + }, +}; + +int mfc_check_vb_with_fmt(struct mfc_fmt *fmt, struct vb2_buffer *vb) +{ + struct mfc_ctx *ctx = vb->vb2_queue->drv_priv; + int mem_planes; + + if (!fmt) + return -EINVAL; + + if (fmt->type & MFC_FMT_FRAME) + mem_planes = ctx->num_fd_frame; + else + mem_planes = fmt->mem_planes; + + if (mem_planes != vb->num_planes) { + mfc_ctx_err("plane number is different (%d != %d)\n", + mem_planes, vb->num_planes); + return -EINVAL; + } + + return 0; +} + +int mfc_check_resolution(struct mfc_ctx *ctx) +{ + int check_res = ctx->dev->pdata->support_check_res; + int max_width, max_height; + + if (!check_res) + return 0; + + max_width = mfc_res[check_res].width; + max_height = mfc_res[check_res].height; + + if ((ctx->crop_width > max_width && ctx->crop_height > max_height) || + (ctx->crop_width > max_height && ctx->crop_height > max_width)) { + mfc_ctx_err("Resolution is too big (%dx%d > %dx%d or %dx%d)\n", + ctx->crop_width, ctx->crop_height, + max_width, max_height, max_height, max_width); + return -EINVAL; + } + + return 0; +} + +static void __mfc_set_dec_stride(struct mfc_ctx *ctx, + struct mfc_raw_info *raw, + struct mfc_fmt *fmt) +{ + int stride_align, y_stride; + + stride_align = ctx->dev->pdata->stride_align; + y_stride = ALIGN(ctx->img_width, stride_align); + + switch (fmt->fourcc) { + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + raw->stride[0] = y_stride; + raw->stride[1] = ALIGN(y_stride >> 1, stride_align); + raw->stride[2] = ALIGN(y_stride >> 1, stride_align); + break; + case V4L2_PIX_FMT_NV12MT_16X16: + case V4L2_PIX_FMT_NV12MT: + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + raw->stride[0] = y_stride; + raw->stride[1] = y_stride; + raw->stride[2] = 0; + break; + default: + mfc_ctx_err("Invalid pixelformat : %s\n", fmt->name); + break; + } +} + +void mfc_set_linear_stride_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt) +{ + /* + * Decoder: Use stride alignment value defiend in DT. + * (Largest limitation among SoC IPs) + * Encoder: Use the stride value that the user set when s_fmt. + */ + if (ctx->type == MFCINST_DECODER) + __mfc_set_dec_stride(ctx, raw, fmt); +} + +void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt) +{ + int i; + int extra = MFC_LINEAR_BUF_SIZE; + int check_min_dpb_size = 1; + + mfc_set_linear_stride_size(ctx, raw, fmt); + + raw->total_plane_size = 0; + + for (i = 0; i < raw->num_planes; i++) { + raw->plane_size[i] = 0; + raw->plane_size_2bits[i] = 0; + } + + switch (fmt->fourcc) { + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) / 2 + extra; + break; + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) / 2 + extra; + raw->plane_size[2] = raw->stride[2] * ALIGN(ctx->img_height, 16) / 2 + extra; + break; + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) + extra; + break; + default: + mfc_ctx_err("Invalid pixelformat : %s\n", fmt->name); + break; + } + + /* + * The min DPB size returned by firmware may be larger than + * the DPB size calculated by the driver in the following situation. + * - Change 10bit mem_type at INIT_BUF. + * - Use single-fd format without extra bytes. + * In the above case, if the driver forcibly changes the DPB size, + * it fails due to buffer size error at V4L2 Qbuf. + * And when F/W really needs min DPB size in scenario like VP9 interframe DRC, + * if the driver does not force change the DPB size, + * No.57(INSUFFICIENT_DPB_SIZE) error occurs in F/W. + */ + if (fmt->mem_planes == 1) + check_min_dpb_size = 0; + + if (check_min_dpb_size) { + for (i = 0; i < raw->num_planes; i++) { + if (raw->plane_size[i] < ctx->min_dpb_size[i]) { + mfc_ctx_info("[FRAME] plane[%d] size %d / min size %d\n", + i, raw->plane_size[i], ctx->min_dpb_size[i]); + raw->plane_size[i] = ctx->min_dpb_size[i]; + } + } + } + + for (i = 0; i < raw->num_planes; i++) { + raw->total_plane_size += raw->plane_size[i]; + mfc_ctx_debug(2, "[FRAME] Plane[%d] size = %d, stride = %d\n", + i, raw->plane_size[i], raw->stride[i]); + } + mfc_ctx_debug(2, "[FRAME] total plane size: %d\n", raw->total_plane_size); + + if (IS_H264_DEC(ctx)) { + ctx->mv_size = DEC_MV_SIZE_MB(ctx->img_width, ctx->img_height); + ctx->mv_size = ALIGN(ctx->mv_size, 32); + } else { + ctx->mv_size = 0; + } +} + +void mfc_calc_base_addr(struct mfc_ctx *ctx, struct vb2_buffer *vb, + struct mfc_fmt *fmt) +{ + struct mfc_buf *buf = vb_to_mfc_buf(vb); + int i, idx, max_idx; + + if ((fmt->type & MFC_FMT_FRAME) && ctx->multi_view_enable) + max_idx = MFC_MV_BUF_IDX_MAX; + else + max_idx = 1; + + for (i = 0; i < max_idx; i++) { + /* It means there is no plane in the buffer. */ + if (ctx->view_buf_info[i].num_fd == 0) + continue; + + for (idx = 0; idx < ctx->view_buf_info[i].num_fd; idx++) + buf->addr[i][idx] = mfc_mem_get_daddr_vb + (vb, ctx->view_buf_info[i].offset + idx); + } + + for (i = 0; i < fmt->num_planes; i++) + mfc_ctx_debug(2, "[MEMINFO] plane[%d] addr %#llx\n", i, buf->addr[0][i]); +} + +void mfc_set_view_buf_info(struct mfc_ctx *ctx, + int mem_planes, + int num_fd_depth_map, + int num_fd_sub_view_meta) +{ + int offset = 0; + + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW0].offset = offset; + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW0].num_fd = mem_planes; + offset += mem_planes; + + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW0_DEPTH].offset = offset; + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW0_DEPTH].num_fd = num_fd_depth_map; + offset += num_fd_depth_map; + + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1].offset = offset; + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1].num_fd = mem_planes; + offset += mem_planes; + + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1_DEPTH].offset = offset; + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1_DEPTH].num_fd = num_fd_depth_map; + offset += num_fd_depth_map; + + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1_META].offset = offset; + ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1_META].num_fd = num_fd_sub_view_meta; + offset += num_fd_sub_view_meta; +} + +void mfc_core_idle_checker(struct timer_list *t) +{ + struct mfc_core *core = timer_container_of(core, t, mfc_idle_timer); + struct mfc_dev *dev = core->dev; + + mfc_core_debug(5, "[MFCIDLE] MFC HW idle checker is ticking!\n"); + + if (dev->move_ctx_cnt) { + MFC_TRACE_RM("[MFCIDLE] migration working\n"); + mfc_core_idle_checker_start_tick(core); + return; + } + + if (atomic_read(&core->qos_req_cur) == 0) { + mfc_core_debug(6, "[MFCIDLE] MFC QoS not started yet\n"); + mfc_core_idle_checker_start_tick(core); + return; + } + + if (core->sched->is_work(core)) { + MFC_TRACE_CORE("[MFCIDLE] there is work to do\n"); + mfc_core_debug(6, "[MFCIDLE] there is work to do\n"); + core->sched->queue_work(core); + mfc_core_idle_checker_start_tick(core); + return; + } + + if (!atomic_read(&core->hw_run_bits) && !atomic_read(&core->dev->queued_bits)) + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_RUNNING); + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + queue_work(core->mfc_idle_wq, &core->mfc_idle_work); +#endif +} diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h index 320dc96a40ed..dedfb049e6fc 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h @@ -12,7 +12,84 @@ #ifndef __MFC_UTILS_H #define __MFC_UTILS_H __FILE__ -#include "mfc_common.h" +#include "mfc_rate_calculate.h" +#include "mfc_format.h" + +/* bit operation */ +#define mfc_clear_bits(reg, mask, shift) ((reg) &= ~((mask) << (shift))) +#define mfc_set_bits(reg, mask, shift, value) ((reg) |= ((value) & (mask)) << (shift)) +#define mfc_clear_set_bits(reg, mask, shift, value) \ + do { \ + typeof(shift) s = shift; \ + typeof(mask) m = mask; \ + (reg) &= ~(m << s); \ + (reg) |= ((value) & m) << s; \ + } while (0) + +#define mfc_get_upper(x) (((unsigned long)(x) >> 32) & U32_MAX) +#define mfc_get_lower(x) ((x) & U32_MAX) + +#define MFC_FPS(x) ((x) / 1000) + +static inline void mfc_set_bit(int num, struct mfc_bits *data) +{ + unsigned long flags; + + spin_lock_irqsave(&data->lock, flags); + __set_bit(num, &data->bits); + spin_unlock_irqrestore(&data->lock, flags); +} + +static inline void mfc_clear_bit(int num, struct mfc_bits *data) +{ + unsigned long flags; + + spin_lock_irqsave(&data->lock, flags); + __clear_bit(num, &data->bits); + spin_unlock_irqrestore(&data->lock, flags); +} + +static inline int mfc_is_all_bits_cleared(struct mfc_bits *data) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&data->lock, flags); + ret = ((data->bits) == 0) ? 1 : 0; + spin_unlock_irqrestore(&data->lock, flags); + return ret; +} + +static inline void mfc_clear_all_bits(struct mfc_bits *data) +{ + unsigned long flags; + + spin_lock_irqsave(&data->lock, flags); + data->bits = 0; + spin_unlock_irqrestore(&data->lock, flags); +} + +static inline unsigned long mfc_get_bits(struct mfc_bits *data) +{ + unsigned long flags; + unsigned long ret; + + spin_lock_irqsave(&data->lock, flags); + ret = data->bits; + spin_unlock_irqrestore(&data->lock, flags); + return ret; +} + +static inline void mfc_create_bits(struct mfc_bits *data) +{ + spin_lock_init(&data->lock); + mfc_clear_all_bits(data); +} + +static inline void mfc_delete_bits(struct mfc_bits *data) +{ + mfc_clear_all_bits(data); +} static inline void mfc_core_clean_dev_int_flags(struct mfc_core *core) { @@ -65,6 +142,7 @@ static inline void mfc_core_change_fw_state(struct mfc_core *core, prev_stat, core->fw.status, set ? "set" : "clear", state); mfc_core_debug(2, "[F/W] normal status: %#x -> %#x (%s: %#x)\n", prev_stat, core->fw.status, set ? "set" : "clear", state); + } static inline enum mfc_node_type mfc_get_node_type(struct file *file) @@ -121,6 +199,27 @@ static inline void mfc_clear_mb_flag(struct mfc_buf *mfc_buf) mfc_buf->flag = 0; } +static inline void mfc_set_mb_flag(struct mfc_buf *mfc_buf, enum mfc_mb_flag f) +{ + mfc_buf->flag |= BIT(f); +} + +static inline int mfc_check_mb_flag(struct mfc_buf *mfc_buf, enum mfc_mb_flag f) +{ + if (mfc_buf->flag & BIT(f)) + return 1; + + return 0; +} + +int mfc_check_vb_with_fmt(struct mfc_fmt *fmt, struct vb2_buffer *vb); +int mfc_check_resolution(struct mfc_ctx *ctx); +void mfc_set_linear_stride_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt); +void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt); +void mfc_calc_base_addr(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct mfc_fmt *fmt); +void mfc_set_view_buf_info(struct mfc_ctx *ctx, int mem_planes, + int num_fd_depth_map, int num_fd_sub_view_meta); + static inline u32 mfc_dec_get_strm_size(struct mfc_ctx *ctx, struct mfc_buf *src_mb) { struct vb2_plane *vb_plane; @@ -157,6 +256,41 @@ static inline u32 mfc_dec_get_strm_size(struct mfc_ctx *ctx, struct mfc_buf *src return strm_size; } + +static inline int mfc_dec_get_strm_offset(struct mfc_ctx *ctx, struct mfc_buf *src_mb) +{ + struct vb2_plane *vb_plane; + struct mfc_dec *dec = ctx->dec_priv; + unsigned int offset; + + vb_plane = &src_mb->vb.vb2_buf.planes[0]; + offset = vb_plane->data_offset; + if (dec->consumed) + offset += dec->consumed; + + mfc_ctx_debug(2, "[STREAM] offset: %d (bytesused %d, data_offset %d, consumed %d)\n", + offset, vb_plane->bytesused, vb_plane->data_offset, dec->consumed); + + return offset; +} + +static inline int mfc_dec_status_decoding(unsigned int dst_frame_status) +{ + if (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_DISPLAY || + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY) + return 1; + return 0; +} + +static inline int mfc_dec_status_display(unsigned int dst_frame_status) +{ + if (dst_frame_status == MFC_REG_DEC_STATUS_DISPLAY_ONLY || + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_DISPLAY) + return 1; + + return 0; +} + /* Meerkat interval */ #define MEERKAT_TICK_INTERVAL 1000 /* After how many executions meerkat should assume lock up */ @@ -190,6 +324,20 @@ static inline void mfc_core_idle_update_hw_run(struct mfc_core *core, spin_unlock_irqrestore(&core->dev->idle_bits_lock, flags); } +static inline void mfc_idle_update_queued(struct mfc_dev *dev, + struct mfc_ctx *ctx) +{ + unsigned long flags; + int bits; + + spin_lock_irqsave(&dev->idle_bits_lock, flags); + + bits = atomic_read(&dev->queued_bits); + atomic_set(&dev->queued_bits, (bits | BIT(ctx->num))); + + spin_unlock_irqrestore(&dev->idle_bits_lock, flags); +} + static inline void mfc_core_change_idle_mode(struct mfc_core *core, enum mfc_idle_mode idle_mode) { @@ -206,4 +354,68 @@ static inline void mfc_ctx_change_idle_mode(struct mfc_ctx *ctx, MFC_TRACE_CTX("**[c:%d] idle mode : %d\n", ctx->num, idle_mode); ctx->idle_mode = idle_mode; } + +static inline void mfc_print_ctx_info(struct mfc_ctx *ctx) +{ + struct mfc_fmt *codec = NULL; + struct mfc_fmt *fmt = NULL; + + if (ctx->type == MFCINST_DECODER) { + codec = ctx->src_fmt; + fmt = ctx->dst_fmt; + } else { + codec = ctx->dst_fmt; + fmt = ctx->src_fmt; + } + + if (!codec) + codec = &mfc_formats[0]; + if (!fmt) + fmt = &mfc_formats[0]; + mfc_ctx_info("- %s%s, %s, %dx%d %lu fps(ts %lu fps, op %lu fps, rt %lu fps)", + codec->name, + ctx->multi_view_enable ? "(MV-HEVC)" : "", + fmt->name, + ctx->img_width, ctx->img_height, + MFC_FPS(ctx->framerate), + MFC_FPS(ctx->last_framerate), + MFC_FPS(ctx->operating_framerate), + MFC_FPS(mfc_rate_get_rt_framerate(ctx, ctx->rt))); + mfc_ctx_info("mb %lu(%d%%), main core %d, op_mode %d(stream %d), rt %d\n", + ctx->weighted_mb, ctx->load, + ctx->op_core_num[MFC_CORE_MAIN], + ctx->op_mode, ctx->stream_op_mode, ctx->rt); +} + +static inline void mfc_show_ctx_info(struct mfc_ctx *ctx) +{ + struct mfc_fmt *codec = NULL; + struct mfc_fmt *fmt = NULL; + + if (ctx->type == MFCINST_DECODER) { + codec = ctx->src_fmt; + fmt = ctx->dst_fmt; + } else { + codec = ctx->dst_fmt; + fmt = ctx->src_fmt; + } + + if (!codec) + codec = &mfc_formats[0]; + if (!fmt) + fmt = &mfc_formats[0]; + + mfc_ctx_debug(3, "- %s, %s, %dx%d %lu fps(ts %lu fps, op %lu fps, rt %lu fps)", + codec->name, + fmt->name, + ctx->img_width, ctx->img_height, + MFC_FPS(ctx->framerate), + MFC_FPS(ctx->last_framerate), + MFC_FPS(ctx->operating_framerate), + MFC_FPS(mfc_rate_get_rt_framerate(ctx, ctx->rt))); + mfc_ctx_debug(3, "mb %lu(%d%%), main core %d, op_mode %d(stream %d), rt %d\n", + ctx->weighted_mb, ctx->load, + ctx->op_core_num[MFC_CORE_MAIN], + ctx->op_mode, ctx->stream_op_mode, ctx->rt); +} #endif /* __MFC_UTILS_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035610epcas5p3c64bccc78b92b0bb907a73615103ebd3@epcas5p3.samsung.com>]
* [PATCH 12/29] media: mfc: Introduce QoS support and instance context handling [not found] ` <CGME20250930035610epcas5p3c64bccc78b92b0bb907a73615103ebd3@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Implement QoS support (load estimation, dynamic level adjustment, PM‑QoS & idle‑mode handling) - Add mfc_qos.c/h and integrate it into the Makefile - Introduce instance‑context allocation/release APIs (mfc_alloc_instance_context, mfc_release_instance_context) - Update driver code to use the new APIs and add debugging/trace hooks - Provide documentation/comments for the new functionality Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 1 + .../samsung/exynos-mfc/base/mfc_buf.c | 207 ++++ .../samsung/exynos-mfc/base/mfc_buf.h | 8 + .../samsung/exynos-mfc/base/mfc_qos.c | 965 ++++++++++++++++++ .../samsung/exynos-mfc/base/mfc_qos.h | 99 ++ 5 files changed, 1280 insertions(+) create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index bd5f80953bab..9def2686cd4e 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -21,5 +21,6 @@ exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o #Common base layer exynos_mfc-y += base/mfc_rate_calculate.o base/mfc_queue.o base/mfc_utils.o exynos_mfc-y += base/mfc_buf.o base/mfc_mem.o +exynos_mfc-y += base/mfc_qos.o #Tracing # exynos_mfc-y += trace/mfc_trace_points.o diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c index b8b140824aab..bd1baf34e0b0 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c @@ -88,6 +88,213 @@ int mfc_alloc_common_context(struct mfc_core *core) return ret; } +/* Release instance buffer */ +void mfc_release_instance_context(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + + mfc_debug_enter(); + + mfc_iova_pool_free(core->dev, &core_ctx->instance_ctx_buf); + + mfc_mem_special_buf_free(core->dev, &core_ctx->instance_ctx_buf); + + mfc_debug_leave(); +} + +/* Allocate memory for instance data buffer */ +int mfc_alloc_instance_context(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx_buf_size *buf_size; + + mfc_debug_enter(); + + buf_size = dev->variant->buf_size->ctx_buf; + + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: + core_ctx->instance_ctx_buf.size = buf_size->h264_dec_ctx; + break; + default: + core_ctx->instance_ctx_buf.size = 0; + mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode); + return -ENOMEM; + } + + core_ctx->instance_ctx_buf.buftype = MFCBUF_NORMAL; + + snprintf(core_ctx->instance_ctx_buf.name, + MFC_NUM_SPECIAL_BUF_NAME, + "MFC%d ctx%d instance", + core_ctx->core->id, + core_ctx->num); + if (mfc_mem_special_buf_alloc(dev, &core_ctx->instance_ctx_buf)) { + mfc_err("Allocating context buffer failed\n"); + return -ENOMEM; + } + + if (mfc_iova_pool_alloc(dev, &core_ctx->instance_ctx_buf)) { + mfc_err("[POOL] failed to get iova\n"); + mfc_release_instance_context(core_ctx); + return -ENOMEM; + } + + mfc_debug_leave(); + + return 0; +} + +static void __mfc_dec_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dec *dec = ctx->dec_priv; + + /* Codecs have different memory requirements */ + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + ctx->mv_buf.size = dec->mv_count * ctx->mv_size; + break; + default: + core_ctx->codec_buf.size = 0; + mfc_err("invalid codec type: %d\n", ctx->codec_mode); + break; + } + + mfc_debug(2, + "[MEMINFO] scratch: %zu, MV: %zu x count %d\n", + ctx->scratch_buf_size, + ctx->mv_size, + dec->mv_count); + if (dec->loop_filter_mpeg4) + mfc_debug(2, + "[MEMINFO] (loopfilter luma: %zu, chroma: %zu) x count %d\n", + ctx->loopfilter_luma_size, + ctx->loopfilter_chroma_size, + NUM_MPEG4_LF_BUF); +} + +/* Allocate codec buffers */ +int mfc_alloc_codec_buffers(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_dev *dev = core->dev; + struct mfc_ctx *ctx = core_ctx->ctx; + + mfc_debug_enter(); + + if (ctx->type == MFCINST_DECODER) { + __mfc_dec_calc_codec_buffer_size(core_ctx); + } else { + mfc_err("invalid type: %d\n", ctx->type); + return -EINVAL; + } + + core_ctx->codec_buf.buftype = MFCBUF_NORMAL; + ctx->mv_buf.buftype = MFCBUF_NORMAL; + + if (core_ctx->codec_buf.size > 0) { + snprintf(core_ctx->codec_buf.name, + MFC_NUM_SPECIAL_BUF_NAME, + "MFC%d ctx%d codec", + core->id, + core_ctx->num); + if (mfc_mem_special_buf_alloc(dev, &core_ctx->codec_buf)) { + mfc_err("Allocating codec buffer failed\n"); + return -ENOMEM; + } + core_ctx->codec_buffer_allocated = 1; + } else if (ctx->codec_mode == MFC_REG_CODEC_MPEG2_DEC) { + core_ctx->codec_buffer_allocated = 1; + } + + if (!ctx->mv_buffer_allocated && ctx->mv_buf.size > 0) { + snprintf(ctx->mv_buf.name, + MFC_NUM_SPECIAL_BUF_NAME, + "MFC%d ctx%d MV", + core->id, + ctx->num); + if (mfc_mem_special_buf_alloc(dev, &ctx->mv_buf)) { + mfc_err("Allocating MV buffer failed\n"); + return -ENOMEM; + } + ctx->mv_buffer_allocated = 1; + } + + mfc_debug_leave(); + + return 0; +} + +/* Release buffers allocated for codec */ +void mfc_release_codec_buffers(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + + if (core_ctx->codec_buffer_allocated) { + mfc_mem_special_buf_free(ctx->dev, &core_ctx->codec_buf); + core_ctx->codec_buffer_allocated = 0; + } + + if (ctx->mv_buffer_allocated) { + mfc_mem_special_buf_free(ctx->dev, &ctx->mv_buf); + ctx->mv_buffer_allocated = 0; + } + + mfc_release_scratch_buffer(core_ctx); +} + +int mfc_alloc_scratch_buffer(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_dev *dev = core->dev; + struct mfc_ctx *ctx = core_ctx->ctx; + + mfc_debug_enter(); + + if (core_ctx->scratch_buffer_allocated) { + mfc_mem_special_buf_free(dev, &core_ctx->scratch_buf); + core_ctx->scratch_buffer_allocated = 0; + mfc_debug(2, "[MEMINFO] Release the scratch buffer ctx[%d]\n", core_ctx->num); + } + + core_ctx->scratch_buf.buftype = MFCBUF_NORMAL; + + core_ctx->scratch_buf.size = ALIGN(ctx->scratch_buf_size, SZ_256); + if (core_ctx->scratch_buf.size > 0) { + snprintf(core_ctx->scratch_buf.name, + MFC_NUM_SPECIAL_BUF_NAME, + "MFC%d ctx%d scratch", + core->id, + core_ctx->num); + if (mfc_mem_special_buf_alloc(dev, &core_ctx->scratch_buf)) { + mfc_err("Allocating scratch_buf buffer failed\n"); + return -ENOMEM; + } + core_ctx->scratch_buffer_allocated = 1; + } + + mfc_debug_leave(); + + return 0; +} + +void mfc_release_scratch_buffer(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + + mfc_debug_enter(); + if (core_ctx->scratch_buffer_allocated) { + mfc_mem_special_buf_free(ctx->dev, &core_ctx->scratch_buf); + core_ctx->scratch_buffer_allocated = 0; + } + mfc_debug_leave(); +} + /* Allocation buffer of debug infor memory for FW debugging */ int mfc_alloc_dbg_info_buffer(struct mfc_core *core) { diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h index 8291e043b81a..6907cf6ac775 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h @@ -18,6 +18,14 @@ void mfc_release_common_context(struct mfc_core *core); int mfc_alloc_common_context(struct mfc_core *core); +void mfc_release_instance_context(struct mfc_core_ctx *core_ctx); +int mfc_alloc_instance_context(struct mfc_core_ctx *core_ctx); + +int mfc_alloc_codec_buffers(struct mfc_core_ctx *core_ctx); +void mfc_release_codec_buffers(struct mfc_core_ctx *core_ctx); +int mfc_alloc_scratch_buffer(struct mfc_core_ctx *core_ctx); +void mfc_release_scratch_buffer(struct mfc_core_ctx *core_ctx); + int mfc_alloc_firmware(struct mfc_core *core); int mfc_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf, diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c new file mode 100644 index 000000000000..f6548543f07c --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c @@ -0,0 +1,965 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_qos.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include <linux/err.h> +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ +#include <soc/samsung/freq-qos-tracer.h> +#endif + +#include "mfc_qos.h" +#include "mfc_utils.h" +#include "mfc_queue.h" + +static inline int __mfc_core_get_qos_steps(struct mfc_core *core, int table_type) +{ + return core->core_pdata->num_default_qos_steps; +} + +static inline struct mfc_qos *__mfc_core_get_qos_table(struct mfc_core *core, int table_type) +{ + return core->core_pdata->default_qos_table; +} + +static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned long mb) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_qos_weight *qos_weight = &ctx->dev->pdata->qos_weight; + u32 num_planes = ctx->dst_fmt->num_planes; + int weight = 1000; + unsigned long weighted_mb; + + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_DEC: + weight = (weight * 100) / qos_weight->weight_h264_hevc; + mfc_ctx_debug(3, "[QoS] h264, hevc codec, weight: %d\n", weight / 10); + if (num_planes == 3) { + weight = (weight * 100) / qos_weight->weight_3plane; + mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); + } + break; + default: + mfc_ctx_err("[QoS] wrong codec_mode (%d), no weight\n", ctx->codec_mode); + } + + if (dec) { + if (dec->num_of_tile_over_4) { + weight = (weight * 100) / qos_weight->weight_num_of_tile; + mfc_ctx_debug(3, "[QoS] num of tile >= 4, weight: %d\n", weight / 10); + } + if (dec->is_mbaff) { + weight = (weight * 100) / qos_weight->weight_mbaff; + mfc_ctx_debug(3, "[QoS] MBAFF, weight: %d\n", weight / 10); + } + } + + weighted_mb = (mb * weight) / 1000; + mfc_ctx_debug(3, "%s %d, %s %d, %s %d, 422format: %d (mb: %ld)\n", + "[QoS] weight:", weight / 10, + "codec:", ctx->codec_mode, + "num planes:", num_planes, + ctx->is_422, + weighted_mb); + + return weighted_mb; +} + +void mfc_qos_get_weighted_mb(struct mfc_ctx *ctx, enum mfc_real_time rt) +{ + unsigned long mb; + unsigned int max_mb = ctx->dev->core[MFC_DEC_DEFAULT_CORE]->core_pdata->max_mb; + + ctx->mb_width = WIDTH_MB(ctx->img_width); + ctx->mb_height = HEIGHT_MB(ctx->img_height); + mb = ctx->mb_width * ctx->mb_height * (mfc_rate_get_rt_framerate(ctx, rt) / 1000); + + /* Instance individual load regardless of operating in the multi core */ + ctx->weighted_mb = __mfc_qos_add_weight(ctx, mb); + ctx->load = ctx->weighted_mb * 100 / max_mb; + + mfc_ctx_debug(3, "[QoS] weighted_mb: %ld(load: %u)\n", + ctx->weighted_mb, ctx->load); +} + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ +enum { + MFC_QOS_ADD = 0, + MFC_QOS_UPDATE, + MFC_QOS_REMOVE, + MFC_QOS_BW, +}; + +enum { + MFC_PERF_BOOST_DVFS = BIT(0), + MFC_PERF_BOOST_MO = BIT(1), + MFC_PERF_BOOST_CPU = BIT(2), +}; + +void __mfc_qos_cpu_boost_enable(struct mfc_core *core) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + struct mfc_qos_boost *qos_boost_table = pdata->qos_boost_table; + struct cpufreq_policy *policy; + int i; + + for (i = 0; i < qos_boost_table->num_cluster; i++) { + policy = cpufreq_cpu_get(qos_boost_table->num_cpu[i]); + if (policy) { + freq_qos_tracer_add_request(&policy->constraints, + &core->qos_req_cluster[i], FREQ_QOS_MIN, + qos_boost_table->freq_cluster[i]); + mfc_core_debug(2, "[QoS][BOOST] CPU cluster[%d]: %d\n", + i, qos_boost_table->freq_cluster[i]); + } + } + + core->cpu_boost_enable = 1; +} + +void __mfc_qos_cpu_boost_disable(struct mfc_core *core) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + struct mfc_qos_boost *qos_boost_table = pdata->qos_boost_table; + int i; + + for (i = 0; i < qos_boost_table->num_cluster; i++) { + freq_qos_tracer_remove_request(&core->qos_req_cluster[i]); + mfc_core_debug(2, "[QoS][BOOST] CPU cluster[%d] off\n", i); + } + + core->cpu_boost_enable = 0; +} + +void mfc_qos_set_portion(struct mfc_core *core, struct mfc_ctx *ctx) +{ + int idx; + + /* + * When only it is single instance, + * there is an exact meaning in the qos portion. + */ + if (!ctx->mfc_qos_portion || core->num_inst > 1) + return; + + idx = atomic_read(&core->qos_req_cur) - 1; + if (idx == -1) + return; + + ctx->mfc_qos_portion[idx]++; +} + +void mfc_qos_get_portion(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_qos *qos_table; + int num_qos_steps; + int i, sum = 0; + int table_type; + + if (!ctx->mfc_qos_portion) + return; + + table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + + num_qos_steps = __mfc_core_get_qos_steps(core, table_type); + qos_table = __mfc_core_get_qos_table(core, table_type); + + for (i = 0; i < num_qos_steps; i++) { + sum += ctx->mfc_qos_portion[i]; + mfc_ctx_debug(2, "[QoS][portion] lv%d: %d frame, %d%% (type: %d, mfc: %d, int: %d, mif: %d, mo: %s)\n", + i, ctx->mfc_qos_portion[i], + ctx->mfc_qos_portion[i] * 100 / ctx->frame_cnt, + core->last_table_type, + qos_table[i].freq_mfc, qos_table[i].freq_int, + qos_table[i].freq_mif, qos_table[i].name); + } + mfc_ctx_debug(2, "[QoS][portion] total %d frame (recorded %d)\n", + ctx->frame_cnt, sum); +} + +bool mfc_qos_mb_calculate(struct mfc_core *core, struct mfc_core_ctx *core_ctx, + unsigned int processing_cycle, unsigned int frame_type) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct list_head *head = &core_ctx->mb_list; + struct mfc_mb_control *temp_mb; + struct mfc_mb_control *new_mb; + unsigned int avg_fps, need_fps, total_fps = 0; + unsigned long frame_time, drv_time, hw_mb, need_mb, avg_mb, margin_mb, total_mb = 0; + int table_type, num_qos_steps, cur_qos, count = 0, level_num; + bool update = false; + + if (!core->dev->pdata->dynamic_weight || + (core->dev->debugfs.feature_option & MFC_OPTION_USE_FIXED_WEIGHT)) + return update; + + if (ctx->frame_cnt < (MFC_MIN_FPS / 1000) || + ctx->framerate > MFC_MAX_FPS || + core->dev->num_inst > 1) { + core_ctx->dynamic_weight_level = 0; + core_ctx->dynamic_weight_started = 0; + return update; + } + + if (frame_type == 7) { + mfc_debug(4, "[QoS] Empty decoding\n"); + return update; + } + + mutex_lock(&core->qos_mutex); + + if (!core_ctx->dynamic_weight_started) { + mfc_debug(4, "[QoS] Clear MB list\n"); + + while (!list_empty(head)) { + temp_mb = list_entry(head->next, struct mfc_mb_control, list); + list_del(&temp_mb->list); + } + + core_ctx->mb_index = 0; + core_ctx->mb_is_full = 0; + core_ctx->mb_not_coded_time = 0; + core_ctx->dynamic_weight_level = 0; + core_ctx->dynamic_weight_started = 1; + core_ctx->mb_update_time = MFC_MAX_MB_TABLE; + } + + new_mb = &core_ctx->mb_table[core_ctx->mb_index]; + + /* setup macroblock table list */ + if (core_ctx->mb_is_full && !core_ctx->mb_not_coded_time) { + temp_mb = list_entry(head->next, struct mfc_mb_control, list); + list_del(&temp_mb->list); + } + + hw_mb = ((ctx->crop_width + 15) / 16) * ((ctx->crop_height + 15) / 16); + + if (IS_MULTI_STREAM(ctx)) + drv_time = MFC_2CORE_DRV_TIME; + else if (ctx->type == MFCINST_DECODER) + drv_time = MFC_DRV_TIME; + else + drv_time = 0; + + frame_time = processing_cycle / (core->last_mfc_freq / 1000) + drv_time; + if (core_ctx->mb_not_coded_time) { + mfc_debug(4, "[QoS] Add not coded time. %lu + %lu\n", + frame_time, core_ctx->mb_not_coded_time); + frame_time += core_ctx->mb_not_coded_time; + core_ctx->mb_not_coded_time = 0; + } else { + list_add_tail(&new_mb->list, head); + } + + if (frame_type == 0) { + mfc_debug(4, "[QoS] Not coded frame type. it accumulated to next frame\n"); + if (frame_time) + core_ctx->mb_not_coded_time = frame_time; + else + core_ctx->mb_not_coded_time = 1; + goto qos_end; + } + + if (frame_time) { + new_mb->mb_per_sec = (USEC_PER_SEC * hw_mb) / frame_time; + new_mb->fps = 1000000 / frame_time; + } else { + new_mb->mb_per_sec = 0; + new_mb->fps = 0; + } + + mfc_debug(4, "[QoS] hw_mb: %ld, cycle: %d, t: %ld, mb: %ld, fps: %d, freq: %d\n", + hw_mb, processing_cycle, frame_time, new_mb->mb_per_sec, + new_mb->fps, core->last_mfc_freq); + + mfc_debug(4, "[QoS] -------------- mb_table (MFC: %dKHz)\n", core->last_mfc_freq); + list_for_each_entry(temp_mb, head, list) { + mfc_debug(4, "[QoS][%d] %lu MB/sec, %u fps\n", + count, temp_mb->mb_per_sec, temp_mb->fps); + total_mb += temp_mb->mb_per_sec; + total_fps += temp_mb->fps; + count++; + } + + if (count == 0) { + mfc_err("[QoS] There is no list for MB\n"); + goto qos_end; + } + + core_ctx->mb_index++; + if (core_ctx->mb_index == MFC_MAX_MB_TABLE) { + core_ctx->mb_is_full = 1; + core_ctx->mb_index = 0; + } + + /* Skip additional updates until the changed QoS is reflected */ + if (core_ctx->mb_update_time) + core_ctx->mb_update_time--; + + /* Calculate macroblock average */ + if (ctx->disp_ratio) + need_fps = ((ctx->framerate / 1000) * ctx->disp_ratio) / 100; + else + need_fps = ctx->framerate / 1000; + if (IS_TWO_MODE2(ctx)) + need_fps = need_fps / core->dev->num_core; + need_mb = hw_mb * need_fps; + avg_mb = total_mb / count; + avg_fps = total_fps / count; + core_ctx->avg_runtime = avg_fps ? (USEC_PER_SEC / avg_fps) : 0; + + mfc_debug(2, "[QoS] MB/sec op: %lu, need: %lu, cur: %lu, fps op: %lu, need: %u cur: %u\n", + hw_mb * ctx->framerate / 1000, need_mb, avg_mb, + ctx->framerate / 1000, need_fps, avg_fps); + + /* Calculate dynamic macroblock weight, it can be minus value */ + if (ctx->type == MFCINST_DECODER) + margin_mb = MFC_DEC_MB_PER_TABLE; + else + margin_mb = MFC_ENC_MB_PER_TABLE; + + if (need_mb < margin_mb) + margin_mb = need_mb / 2; + else if ((need_mb > core->core_pdata->max_mb) || + (IS_MULTI_STREAM(ctx) && IS_MFC_HEAVY_PERF(ctx, need_fps))) + margin_mb = margin_mb * core->dev->num_core; + + if (ctx->type == MFCINST_DECODER) + table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + + num_qos_steps = __mfc_core_get_qos_steps(core, table_type); + + if (atomic_read(&core->qos_req_cur)) { + cur_qos = atomic_read(&core->qos_req_cur); + if (ctx->type == MFCINST_DECODER && + new_mb->mb_per_sec < need_mb && + cur_qos < num_qos_steps) { + level_num = ((need_mb - new_mb->mb_per_sec) + MFC_DEC_MB_PER_TABLE - 1) / + MFC_DEC_MB_PER_TABLE; + if (cur_qos + level_num <= num_qos_steps) + core_ctx->dynamic_weight_level = + core_ctx->dynamic_weight_level + level_num; + else + core_ctx->dynamic_weight_level = num_qos_steps - cur_qos; + mfc_debug(2, "[QoS] dec per frame perf is insufficient (weight level %d)\n", + core_ctx->dynamic_weight_level); + update = true; + } else if ((avg_mb <= need_mb) && + (cur_qos < num_qos_steps) && + !core_ctx->mb_update_time) { + core_ctx->dynamic_weight_level++; + mfc_debug(2, "[QoS] avg perf is insufficient (weight level %d)\n", + core_ctx->dynamic_weight_level); + update = true; + } else if ((avg_mb > need_mb + margin_mb) && + (cur_qos > 1) && + !core_ctx->mb_update_time) { + core_ctx->dynamic_weight_level--; + mfc_debug(2, "[QoS] perf is enough (weight level %d)\n", + core_ctx->dynamic_weight_level); + update = true; + } else if (!core_ctx->mb_update_time) { + mfc_debug(2, "[QoS] perf is suitable\n"); + } + } + + if (update) { + while (!list_empty(head)) { + temp_mb = list_entry(head->next, struct mfc_mb_control, list); + list_del(&temp_mb->list); + } + + core_ctx->mb_index = 0; + core_ctx->mb_is_full = 0; + core_ctx->mb_update_time = MFC_MAX_MB_TABLE; + + mfc_debug(2, "[QoS] dynamic weight level: %d\n", core_ctx->dynamic_weight_level); + } + +qos_end: + mutex_unlock(&core->qos_mutex); + + return update; +} + +static void __mfc_qos_operate(struct mfc_core *core, int opr_type, int table_type, int idx) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + struct mfc_qos *qos_table; + int freq_mfc; + + qos_table = __mfc_core_get_qos_table(core, table_type); + /* When removing QoS, do not update because the table_type is not accurate. */ + if (opr_type != MFC_QOS_REMOVE) + core->last_table_type = table_type; + + if (core->mfc_freq_by_bps > qos_table[idx].freq_mfc) + freq_mfc = core->mfc_freq_by_bps; + else + freq_mfc = qos_table[idx].freq_mfc; + + switch (opr_type) { + case MFC_QOS_ADD: + core->last_mfc_freq = freq_mfc; + if (pdata->mfc_freq_control) + exynos_pm_qos_add_request(&core->qos_req_mfc, pdata->pm_qos_id, + freq_mfc); + exynos_pm_qos_add_request(&core->qos_req_int, PM_QOS_DEVICE_THROUGHPUT, + qos_table[idx].freq_int); + exynos_pm_qos_add_request(&core->qos_req_mif, PM_QOS_BUS_THROUGHPUT, + qos_table[idx].freq_mif); + + atomic_set(&core->qos_req_cur, idx + 1); + mfc_core_debug(3, "[QoS] qos_req_cur: %d\n", atomic_read(&core->qos_req_cur) - 1); + MFC_TRACE_CORE("QoS add[%d] - mfc:%d(%s), int:%d, mif:%d\n", + idx, freq_mfc, pdata->mfc_freq_control ? "used" : "un-used", + qos_table[idx].freq_int, qos_table[idx].freq_mif); + mfc_core_debug(2, "[QoS] QoS add[%d] - mfc:%d(%s), int:%d, mif:%d\n", + idx, freq_mfc, pdata->mfc_freq_control ? "used" : "un-used", + qos_table[idx].freq_int, qos_table[idx].freq_mif); + break; + case MFC_QOS_UPDATE: + core->last_mfc_freq = freq_mfc; + if (pdata->mfc_freq_control) + exynos_pm_qos_update_request(&core->qos_req_mfc, freq_mfc); + exynos_pm_qos_update_request(&core->qos_req_int, qos_table[idx].freq_int); + exynos_pm_qos_update_request(&core->qos_req_mif, qos_table[idx].freq_mif); + + atomic_set(&core->qos_req_cur, idx + 1); + mfc_core_debug(3, "[QoS] qos_req_cur: %d\n", atomic_read(&core->qos_req_cur) - 1); + MFC_TRACE_CORE("QoS update[%d] - mfc:%d(%s), int:%d, mif:%d\n", + idx, freq_mfc, pdata->mfc_freq_control ? "used" : "un-used", + qos_table[idx].freq_int, qos_table[idx].freq_mif); + mfc_core_debug(2, "[QoS] QoS update[%d] - mfc:%d(%s), int:%d, mif:%d\n", + idx, freq_mfc, pdata->mfc_freq_control ? "used" : "un-used", + qos_table[idx].freq_int, qos_table[idx].freq_mif); + break; + case MFC_QOS_REMOVE: + core->last_mfc_freq = 0; + if (atomic_read(&core->qos_req_cur) == 0) { + MFC_TRACE_CORE("QoS already removed\n"); + mfc_core_debug(2, "[QoS] QoS already removed\n"); + break; + } + + mutex_lock(&core->pm_qos_mutex); + if (pdata->mfc_freq_control) + exynos_pm_qos_remove_request(&core->qos_req_mfc); + exynos_pm_qos_remove_request(&core->qos_req_int); + exynos_pm_qos_remove_request(&core->qos_req_mif); + + atomic_set(&core->qos_req_cur, 0); + mfc_core_debug(3, "[QoS] qos_req_cur: %d\n", atomic_read(&core->qos_req_cur) - 1); + MFC_TRACE_CORE("QoS remove\n"); + mfc_core_debug(2, "[QoS] QoS remove\n"); + mutex_unlock(&core->pm_qos_mutex); + break; + case MFC_QOS_BW: + break; + default: + mfc_core_err("[QoS] Unknown request for opr [%d]\n", opr_type); + break; + } +} + +static void __mfc_qos_set(struct mfc_core *core, struct mfc_ctx *ctx, + int table_type, int i) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + struct mfc_qos *qos_table; + int num_qos_steps; + int freq_mfc; + + num_qos_steps = __mfc_core_get_qos_steps(core, table_type); + qos_table = __mfc_core_get_qos_table(core, table_type); + + mfc_ctx_debug(2, "[QoS] %s table[%d] covered mb %d ~ %d (mfc: %d, int:%d, mif:%d)\n", + table_type ? "enc" : "default", i, qos_table[i].threshold_mb, + i == num_qos_steps - 1 ? pdata->max_mb : qos_table[i + 1].threshold_mb, + qos_table[i].freq_mfc, qos_table[i].freq_int, + qos_table[i].freq_mif); + + mfc_core_debug(3, "[QoS] qos_req_cur: %d\n", atomic_read(&core->qos_req_cur) - 1); + if (atomic_read(&core->qos_req_cur) == 0) { + __mfc_qos_operate(core, MFC_QOS_ADD, table_type, i); + } else { + /* + * 1) QoS level is changed + * 2) MFC freq should be high regardless of QoS level + */ + if (atomic_read(&core->qos_req_cur) != (i + 1)) { + __mfc_qos_operate(core, MFC_QOS_UPDATE, table_type, i); + } else { + if (core->mfc_freq_by_bps > qos_table[i].freq_mfc) + freq_mfc = core->mfc_freq_by_bps; + else + freq_mfc = qos_table[i].freq_mfc; + if (freq_mfc != core->last_mfc_freq) { + mfc_ctx_debug(2, "[QoS] mfc freq changed (last: %d, by bps: %d, QoS table: %d)\n", + core->last_mfc_freq, + core->mfc_freq_by_bps, + qos_table[i].freq_mfc); + __mfc_qos_operate(core, MFC_QOS_UPDATE, table_type, i); + } + } + } +} + +static inline unsigned long __mfc_qos_get_mb_per_second(struct mfc_core *core, + struct mfc_core_ctx *core_ctx, + unsigned int max_mb) +{ + struct mfc_dev *dev = core->dev; + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long mb_width, mb_height, fps, frame_mb, mb, qos_weighted_mb; + + mb_width = (ctx->crop_width + 15) / 16; + mb_height = (ctx->crop_height + 15) / 16; + frame_mb = mb_width * mb_height; + if (IS_MULTI_MODE(ctx)) + fps = ctx->framerate / 1000 / dev->num_core; + else + fps = ctx->framerate / 1000; + + /* If decoder resolution is larger than HD and smaller than FHD, apply FHD for perf */ + if (ctx->type == MFCINST_DECODER && frame_mb > MFC_HD_RES_MB && + frame_mb < MFC_FHD_RES_MB) { + mfc_debug(3, "[QoS] frame MB size is changed %lu -> %d (%dx%d)\n", + frame_mb, MFC_FHD_RES_MB, + ctx->crop_width, ctx->crop_height); + frame_mb = MFC_FHD_RES_MB; + } + + mb = frame_mb * fps; + qos_weighted_mb = __mfc_qos_add_weight(ctx, mb); + + mfc_debug(3, "[QoS] ctx[%d:%s] %d x %d @ %ld fps (mb: %ld), %dkbps\n", + ctx->num, ctx->type == MFCINST_ENCODER ? "ENC" : "DEC", + ctx->crop_width, ctx->crop_height, fps, mb, ctx->kbps); + + if (ctx->update_framerate) { + core_ctx->dynamic_weight_level = 0; + core_ctx->dynamic_weight_started = 0; + mfc_debug(4, "[QoS] clear dynamic weight, update_framerate: %d\n", + ctx->update_framerate); + } + + mfc_debug(4, "[QoS] weight (hw_mb: %lu)\n", qos_weighted_mb); + return qos_weighted_mb; +} + +void __mfc_qos_calculate(struct mfc_core *core, struct mfc_ctx *ctx, int delete) +{ + struct mfc_core_platdata *pdata = core->core_pdata; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_qos *qos_table; + struct mfc_ctx *qos_ctx; + struct mfc_core_ctx *qos_core_ctx; + unsigned long hw_mb = 0, total_mb = 0, total_fps = 0; + int total_bps = 0, mfc_freq_idx; + unsigned int fw_time, sw_time; + int i, qos_level, found = 0, dec_found = 0, heif_found = 0; + int table_type = MFC_QOS_TABLE_TYPE_DEFAULT, num_qos_steps; + + /* get the hw macroblock */ + list_for_each_entry(qos_core_ctx, &core->qos_queue, qos_list) { + if (delete && qos_core_ctx == core->core_ctx[ctx->num]) { + found = 1; + continue; + } + + qos_ctx = qos_core_ctx->ctx; + if (qos_ctx->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(3, "[QoS][MFCIDLE] skip idle ctx [%d]\n", qos_ctx->num); + continue; + } + if (qos_ctx->is_heif_mode) + heif_found += 1; + + if (qos_ctx->type == MFCINST_DECODER) + dec_found += 1; + hw_mb += __mfc_qos_get_mb_per_second(core, qos_core_ctx, pdata->max_mb); + total_fps += (qos_ctx->framerate / 1000); + total_bps += qos_ctx->kbps; + } + + if (found) + list_del(&core->core_ctx[ctx->num]->qos_list); + + if (dec_found) + table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + + num_qos_steps = __mfc_core_get_qos_steps(core, table_type); + qos_table = __mfc_core_get_qos_table(core, table_type); + + /* search the suitable qos table */ + for (i = num_qos_steps - 1; i >= 0; i--) { + fw_time = qos_table[i].time_fw; + sw_time = (MFC_DRV_TIME + fw_time); + + if ((total_fps * sw_time) >= 1000000) + total_mb = pdata->max_mb; + else + total_mb = ((1000000 * hw_mb) / (1000000 - (total_fps * sw_time))); + + mfc_ctx_debug(4, "%s %s %s[%d] %s %dus, %s %ld, %s %d, %s %ld, %s %ld\n", + "[QoS]", table_type ? "enc" : "default", + "table", i, + "fw_time:", fw_time, + "hw_mb:", hw_mb, + "sw_time:", sw_time, + "total_fps:", total_fps, + "total_mb:", total_mb); + + if (total_mb > qos_table[i].threshold_mb || total_mb == 0 || i == 0) + break; + } + + if (total_mb > pdata->max_mb) + mfc_ctx_debug(4, "[QoS] overspec mb %ld > %d\n", total_mb, pdata->max_mb); + + if (dec_found) { + /* search the suitable independent mfc freq using bps */ + mfc_freq_idx = mfc_rate_get_bps_section_by_bps + (core->dev, total_bps, core->dev->max_kbps); + core->mfc_freq_by_bps = core->dev->pdata->mfc_freqs[mfc_freq_idx]; + } else { + core->mfc_freq_by_bps = 0; + } + + if (delete && (list_empty(&core->qos_queue) || total_mb == 0)) { + if (core->cpu_boost_enable) + __mfc_qos_cpu_boost_disable(core); + __mfc_qos_operate(core, MFC_QOS_REMOVE, table_type, 0); + } else { + if (heif_found) { + qos_level = num_qos_steps - 1; + mfc_ctx_debug(2, "[QoS][BOOST] use max level for HEIF\n"); + if (!core->cpu_boost_enable) + __mfc_qos_cpu_boost_enable(core); + } else { + qos_level = i; + if (core_ctx->dynamic_weight_level) { + qos_level += core_ctx->dynamic_weight_level; + if (qos_level >= num_qos_steps) + qos_level = num_qos_steps - 1; + else if (qos_level < 0) + qos_level = 0; + mfc_ctx_debug(2, "[QoS] add dynamic weight level %d. table[%d]\n", + core_ctx->dynamic_weight_level, qos_level); + } + if (core->cpu_boost_enable) + __mfc_qos_cpu_boost_disable(core); + } + __mfc_qos_set(core, ctx, table_type, qos_level); + } +} + +void mfc_qos_on(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *qos_core_ctx; + int found = 0; + + if (core->core_ctx[ctx->num] && core->core_ctx[ctx->num]->state == MFCINST_FREE) { + mfc_ctx_info("[QoS] instance not started yet\n"); + return; + } + + mutex_lock(&core->qos_mutex); + list_for_each_entry(qos_core_ctx, &core->qos_queue, qos_list) + if (qos_core_ctx == core->core_ctx[ctx->num]) + found = 1; + + if (!found) + list_add_tail(&core->core_ctx[ctx->num]->qos_list, + &core->qos_queue); + + __mfc_qos_calculate(core, ctx, MFC_QOS_ADD); + + mutex_unlock(&core->qos_mutex); +} + +void mfc_qos_off(struct mfc_core *core, struct mfc_ctx *ctx) +{ + int table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + + mutex_lock(&core->qos_mutex); + + if (list_empty(&core->qos_queue)) { + if (atomic_read(&core->qos_req_cur) != 0) { + mfc_ctx_err("[QoS] MFC request count is wrong!\n"); + if (core->cpu_boost_enable) + __mfc_qos_cpu_boost_disable(core); + __mfc_qos_operate(core, MFC_QOS_REMOVE, table_type, 0); + } + goto out; + } + + if (ON_RES_CHANGE(core->core_ctx[ctx->num])) + goto out; + + __mfc_qos_calculate(core, ctx, MFC_QOS_REMOVE); + +out: + mutex_unlock(&core->qos_mutex); +} + +void mfc_qos_update(struct mfc_core *core, int on) +{ + struct mfc_platdata *pdata = core->dev->pdata; + struct mfc_platdata *dev_pdata = core->dev->pdata; + unsigned int mfc_freq; + int qos, i; + + if (core->dev->debugfs.feature_option & MFC_OPTION_DYNAMIC_QOS_DISABLE) + return; + + mfc_core_debug_enter(); + + mutex_lock(&core->qos_mutex); + + if ((atomic_read(&core->qos_req_cur) <= 1) || + (atomic_read(&core->qos_req_cur) > (dev_pdata->qos_ctrl_level + 1)) || + core->last_table_type != MFC_QOS_TABLE_TYPE_DEFAULT) { + mutex_unlock(&core->qos_mutex); + return; + } + + if (on) { + qos = atomic_read(&core->qos_req_cur) - 1; + mfc_freq = core->last_mfc_freq; + mfc_core_debug(3, "[QoS] ON: QoS update[%d], mfc freq %d\n", + qos, mfc_freq); + } else { + qos = 0; + mfc_freq = pdata->mfc_freqs[0]; + mfc_core_debug(3, "[QoS] OFF: QoS update[%d], mfc freq %d\n", + qos, mfc_freq); + } + + i = core->qos_ctrl_last_idx; + core->qos_ctrl[i].idx = qos; + core->qos_ctrl[i].table_type = core->last_table_type; + core->qos_ctrl[i].mfc_freq = mfc_freq; + core->qos_ctrl_last_idx++; + if (core->qos_ctrl_last_idx >= MAX_NUM_QOS_DYNAMIC) + core->qos_ctrl_last_idx = 0; + + mutex_unlock(&core->qos_mutex); + + queue_work(core->qos_ctrl_wq, &core->qos_ctrl_work); + + mfc_core_debug_leave(); +} + +void mfc_qos_ctrl_worker(struct work_struct *work) +{ + struct mfc_core *core; + struct mfc_core_platdata *pdata; + struct mfc_platdata *dev_pdata; + struct mfc_qos *qos_table; + int idx, i; + + core = container_of(work, struct mfc_core, qos_ctrl_work); + pdata = core->core_pdata; + dev_pdata = core->dev->pdata; + + mutex_lock(&core->qos_mutex); + + if (!core->qos_ctrl_last_idx) { + mutex_unlock(&core->qos_mutex); + return; + } + + i = core->qos_ctrl_last_idx; + do { + core->qos_ctrl_last_idx = 0; + + if ((atomic_read(&core->qos_req_cur) > (dev_pdata->qos_ctrl_level + 1)) || + atomic_read(&core->qos_req_cur) <= 1) { + mutex_unlock(&core->qos_mutex); + return; + } + + i--; + idx = core->qos_ctrl[i].idx; + qos_table = __mfc_core_get_qos_table(core, core->qos_ctrl[i].table_type); + + mutex_unlock(&core->qos_mutex); + + /* use pm_qos_mutex to reduce pm_qos_update latency */ + mutex_lock(&core->pm_qos_mutex); + if (atomic_read(&core->qos_req_cur) == 0) { + mutex_unlock(&core->pm_qos_mutex); + return; + } + + if (pdata->mfc_freq_control) + exynos_pm_qos_update_request + (&core->qos_req_mfc, core->qos_ctrl[i].mfc_freq); + + exynos_pm_qos_update_request(&core->qos_req_int, qos_table[idx].freq_int); + exynos_pm_qos_update_request(&core->qos_req_mif, qos_table[idx].freq_mif); + mfc_core_debug(3, "[QoS] WORKER: QoS update[%d], mfc freq %d\n", + idx, core->qos_ctrl[i].mfc_freq); + + mutex_unlock(&core->pm_qos_mutex); + + mutex_lock(&core->qos_mutex); + i = core->qos_ctrl_last_idx; + } while (i); + + mutex_unlock(&core->qos_mutex); +} + +void __mfc_qos_on_idle(struct mfc_core *core) +{ + struct mfc_ctx *ctx; + int i; + + mutex_lock(&core->dev->mfc_migrate_mutex); + if (!core->num_inst) { + mutex_unlock(&core->dev->mfc_migrate_mutex); + return; + } + + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (core->core_ctx[i]) { + ctx = core->core_ctx[i]->ctx; + mfc_qos_on(core, ctx); + break; + } + } + mutex_unlock(&core->dev->mfc_migrate_mutex); +} + +void __mfc_qos_off_all(struct mfc_core *core) +{ + struct mfc_core_ctx *qos_core_ctx, *tmp_core_ctx; + + mutex_lock(&core->qos_mutex); + if (list_empty(&core->qos_queue)) { + mfc_core_err("[QoS][MFCIDLE] MFC QoS list already empty (%d)\n", + atomic_read(&core->qos_req_cur)); + mutex_unlock(&core->qos_mutex); + return; + } + + /* Delete all of QoS list */ + list_for_each_entry_safe(qos_core_ctx, tmp_core_ctx, &core->qos_queue, qos_list) + list_del(&qos_core_ctx->qos_list); + + /* Select the opend ctx structure for QoS remove */ + if (core->cpu_boost_enable) + __mfc_qos_cpu_boost_disable(core); + __mfc_qos_operate(core, MFC_QOS_REMOVE, MFC_QOS_TABLE_TYPE_DEFAULT, 0); + mutex_unlock(&core->qos_mutex); +} +#else +bool mfc_qos_mb_calculate(struct mfc_core *core, struct mfc_core_ctx *core_ctx, + unsigned int processing_cycle, unsigned int frame_type) +{ + return false; +} +#endif + +void mfc_qos_idle_worker(struct work_struct *work) +{ + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_ctx *ctx; + int is_idle = 0, qos_num_inst = 0; + + core = container_of(work, struct mfc_core, mfc_idle_work); + + mutex_lock(&core->dev->mfc_mutex); + + mutex_lock(&core->idle_qos_mutex); + + /* Check idle mode for all context */ + mutex_lock(&core->qos_mutex); + list_for_each_entry(core_ctx, &core->qos_queue, qos_list) { + ctx = core_ctx->ctx; + qos_num_inst++; + if (((atomic_read(&core->hw_run_bits) & BIT(ctx->num)) == 0) && + ((atomic_read(&core->dev->queued_bits) & BIT(ctx->num)) == 0)) { + mfc_ctx_change_idle_mode(ctx, MFC_IDLE_MODE_IDLE); + mfc_debug(3, "[MFCIDLE] ctx[%d] is idle (hw %#x Q %#x)\n", ctx->num, + atomic_read(&core->hw_run_bits), + atomic_read(&core->dev->queued_bits)); + is_idle = 1; + } else { + mfc_ctx_change_idle_mode(ctx, MFC_IDLE_MODE_NONE); + } + } + mutex_unlock(&core->qos_mutex); + + if (core->idle_mode == MFC_IDLE_MODE_CANCEL) { + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_NONE); + mfc_core_debug(2, "[QoS][MFCIDLE] idle mode is canceled\n"); + goto ctx_idle; + } else if (core->idle_mode == MFC_IDLE_MODE_NONE) { + mfc_core_idle_checker_start_tick(core); + goto ctx_idle; + } + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + __mfc_qos_off_all(core); +#endif + if (qos_num_inst == 1) { + mfc_core_info("[QoS][MFCIDLE] go to idle mode (src %d(ready %d), dst %d, framecnt %d)\n", + mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + ctx->frame_cnt); + } else { + mfc_core_info("[QoS][MFCIDLE] go to idle mode\n"); + } + + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_IDLE); + mutex_unlock(&core->idle_qos_mutex); + mutex_unlock(&core->dev->mfc_mutex); + return; + +ctx_idle: + if (is_idle) { + mfc_core_debug(2, "[QoS][MFCIDLE] idle mode is for ctx\n"); +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + __mfc_qos_on_idle(core); +#endif + } + + mutex_unlock(&core->idle_qos_mutex); + mutex_unlock(&core->dev->mfc_mutex); +} + +bool mfc_qos_idle_trigger(struct mfc_core *core, struct mfc_ctx *ctx) +{ + bool update_idle = false; + + mutex_lock(&core->idle_qos_mutex); + if (core->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(2, "[QoS][MFCIDLE] restart QoS control\n"); + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_NONE); + update_idle = true; + } else if (core->idle_mode == MFC_IDLE_MODE_RUNNING) { + mfc_ctx_debug(2, "[QoS][MFCIDLE] restart QoS control, cancel idle\n"); + mfc_core_change_idle_mode(core, MFC_IDLE_MODE_CANCEL); + update_idle = true; + } + + if (ctx->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(2, "[QoS][MFCIDLE] restart QoS control for ctx\n"); + mfc_ctx_change_idle_mode(ctx, MFC_IDLE_MODE_NONE); + update_idle = true; + } + mutex_unlock(&core->idle_qos_mutex); + + return update_idle; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h new file mode 100644 index 000000000000..d9c0e2828bfa --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_qos.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_QOS_H +#define __MFC_QOS_H __FILE__ + +#include "mfc_common.h" + +#define MB_COUNT_PER_UHD_FRAME 32400 +#define MAX_FPS_PER_UHD_FRAME 120 +#define MIN_BW_PER_SEC 1 + +#define MFC_2CORE_DRV_TIME 1500 +#define MFC_DRV_TIME 500 +#define MFC_DEC_MB_PER_TABLE 650000 +#define MFC_ENC_MB_PER_TABLE 400000 + +/* It is the same value with ID_DEFAULT of exynos-bts.c */ +#define BTS_DEFAULT_SCEN_IDX 0 + +enum { + MFC_QOS_TABLE_TYPE_DEFAULT = 0, + MFC_QOS_TABLE_TYPE_ENCODER = 1, +}; + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ +void mfc_qos_on(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_qos_off(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_qos_update(struct mfc_core *core, int on); +void mfc_qos_ctrl_worker(struct work_struct *work); +void mfc_qos_set_portion(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_qos_get_portion(struct mfc_core *core, struct mfc_ctx *ctx); +#else + +#define mfc_qos_on(core, ctx) ({ \ + (void)core; /* Not used */ \ + (void)ctx; /* Not used */ \ + do {} while (0); \ +}) + +#define mfc_qos_off(core, ctx) ({ \ + (void)core; /* Not used */ \ + (void)ctx; /* Not used */ \ + do {} while (0); \ +}) + +#define mfc_qos_update(core, on) ({ \ + (void)core; /* Not used */ \ + (void)on; /* Not used */ \ + do {} while (0); \ +}) + +#define mfc_qos_ctrl_worker(work) ({ \ + (void)work; /* Not used */ \ + do {} while (0); \ +}) + +#define mfc_qos_set_portion(core, ctx) ({ \ + (void)core; /* Not used */ \ + (void)ctx; /* Not used */ \ + do {} while (0); \ +}) + +#define mfc_qos_get_portion(core, ctx) ({ \ + (void)core; /* Not used */ \ + (void)ctx; /* Not used */ \ + do {} while (0); \ +}) +#endif + +bool mfc_qos_mb_calculate(struct mfc_core *core, + struct mfc_core_ctx *core_ctx, + unsigned int processing_cycle, + unsigned int frame_type); + +void mfc_qos_idle_worker(struct work_struct *work); +bool mfc_qos_idle_trigger(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_qos_get_weighted_mb(struct mfc_ctx *ctx, enum mfc_real_time rt); + +static inline void mfc_qos_get_disp_ratio(struct mfc_ctx *ctx, int dec_cnt, int disp_cnt) +{ + int delta; + + delta = dec_cnt - disp_cnt; + ctx->disp_ratio = ((dec_cnt + delta) * 100) / disp_cnt; + if (ctx->disp_ratio > 100) + mfc_ctx_debug(2, "[QoS] need to more performance dec %d/disp %d, disp_ratio: x%d.%d\n", + dec_cnt, disp_cnt, + ctx->disp_ratio / 100, ctx->disp_ratio % 100); +} +#endif /* __MFC_QOS_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035616epcas5p3696fbcd8fbe66221433651290859e198@epcas5p3.samsung.com>]
* [PATCH 13/29] media: mfc: Add decoder core sync functions [not found] ` <CGME20250930035616epcas5p3696fbcd8fbe66221433651290859e198@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Add core command extensions and decoder‑specific commands. - Update core register APIs with helpers for processing‑cycle, DPB, scratch size, SEI, black‑bar detection, MVC IDs, profile, display delay, two‑core mode, and inline utilities for crop info, tag updates, migration address, and multi‑core context flush. - Refactor core synchronization: migration‑aware lock functions, wait‑queues to prevent races, targeted wake‑ups, and ready‑bit handling for header parsing, frame decoding, buffer setup, resolution changes, and two‑core DRC paths. - Add macros, helper functions, comments, and debug prints to support the new decoder‑side core coordination and upcoming multi‑core decoding. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/mfc_core_cmd.c | 288 +++++++++++++++ .../samsung/exynos-mfc/mfc_core_cmd.h | 9 + .../samsung/exynos-mfc/mfc_core_reg_api.c | 346 ++++++++++++++++++ .../samsung/exynos-mfc/mfc_core_reg_api.h | 214 +++++++++++ .../samsung/exynos-mfc/mfc_core_sync.c | 187 +++++++++- .../samsung/exynos-mfc/mfc_core_sync.h | 9 + 6 files changed, 1049 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c index 5be9fd086a93..fe7946bb49e7 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c @@ -87,6 +87,8 @@ void mfc_core_cmd_open_inst(struct mfc_core *core, struct mfc_ctx *ctx) MFC_CORE_WRITEL(core_ctx->instance_ctx_buf.daddr, MFC_REG_CONTEXT_MEM_ADDR); MFC_CORE_WRITEL(core_ctx->instance_ctx_buf.size, MFC_REG_CONTEXT_MEM_SIZE); + if (ctx->type == MFCINST_DECODER) + MFC_CORE_WRITEL(ctx->dec_priv->crc_enable, MFC_REG_D_CRC_CTRL); if (dev->debugfs.feature_option & MFC_OPTION_SET_MULTI_CORE_FORCE) { reg = MFC_CORE_READL(MFC_REG_DBG_INFO_ENABLE); @@ -135,6 +137,45 @@ void mfc_core_cmd_abort_inst(struct mfc_core *core, struct mfc_ctx *ctx) mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_NAL_ABORT); } +void mfc_core_cmd_move_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_MOVE_INSTANCE); +} + +void mfc_core_cmd_dpb_flush(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + u32 reg = 0; + + if (ON_RES_CHANGE(core_ctx)) + mfc_err("dpb flush on res change(state:%d)\n", + core_ctx->state); + + mutex_lock(&ctx->op_mode_mutex); + + /* + * NAL_START_OPTIONS[4] should set when every NAL_START/DPB_FLUSH, + * it will be cleared by F/W. + */ + reg = MFC_CORE_READL(MFC_REG_D_NAL_START_OPTIONS); + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + if (IS_MULTI_MODE(ctx) || ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2) + reg |= BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + else + reg |= (0 << MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + MFC_CORE_WRITEL(reg, MFC_REG_D_NAL_START_OPTIONS); + mfc_debug(3, "NAL_START_OPTIONS: %#x, op_mode: %d\n", reg, ctx->op_mode); + mutex_unlock(&ctx->op_mode_mutex); + + mfc_clean_core_ctx_int_flags(core_ctx); + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_DPB_FLUSH); +} + void mfc_core_cmd_cache_flush(struct mfc_core *core) { struct mfc_core_ctx *core_ctx = core->core_ctx[core->curr_core_ctx]; @@ -156,3 +197,250 @@ void mfc_core_cmd_cache_flush(struct mfc_core *core) mfc_core_clean_dev_int_flags(core); mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_CACHE_FLUSH); } + +/* Initialize decoding */ +void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + unsigned int reg = 0; + int fmo_aso_ctrl = 0; + + mfc_debug_enter(); + + mfc_debug(2, "inst_no: %d/%d\n", core_ctx->inst_no, MFC_REG_H2R_CMD_SEQ_HEADER); + mfc_debug(2, "BUFs: %llx\n", MFC_CORE_DMA_READL(MFC_REG_D_CPB_BUFFER_ADDR)); + + /* + * When user sets desplay_delay to 0, + * It works as "display_delay enable" and delay set to 0. + * If user wants display_delay disable, It should be + * set to negative value. + */ + if (dec->display_delay >= 0) { + reg |= BIT(MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT); + MFC_CORE_WRITEL(dec->display_delay, MFC_REG_D_DISPLAY_DELAY); + } + + /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ + reg |= ((fmo_aso_ctrl & MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK) + << MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT); + + reg |= ((dec->idr_decoding & MFC_REG_D_DEC_OPT_IDR_DECODING_MASK) + << MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT); + + /* conceal control to specific color */ + reg |= (0x4 << MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); + + /* Realloc buffer for resolution decrease case in NAL QUEUE mode */ + reg |= BIT(MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT); + + /* Parsing all including PPS */ + reg |= BIT(MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT); + + /* Enabe decoding order */ + if (dec->decoding_order || + (dev->debugfs.feature_option & MFC_OPTION_DECODING_ORDER)) + reg |= BIT(MFC_REG_D_DEC_OPT_DECODING_ORDER_ENABLE); + + MFC_CORE_WRITEL(reg, MFC_REG_D_DEC_OPTIONS); + + MFC_CORE_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); + + mfc_core_set_pixel_format(core, ctx, ctx->dst_fmt->fourcc); + + reg = 0; + /* Enable realloc interface if SEI is enabled */ + if (dec->sei_parse) + reg |= BIT(MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT); + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { + reg |= BIT(MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT); + reg |= BIT(MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT); + } + reg |= BIT(MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT); + + MFC_CORE_WRITEL(reg, MFC_REG_D_SEI_ENABLE); + mfc_debug(2, "SEI enable was set, 0x%x\n", MFC_CORE_READL(MFC_REG_D_SEI_ENABLE)); + + /* Enable metadata */ + reg = 0; + + MFC_CORE_WRITEL(reg, MFC_REG_METADATA_ENABLE); + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_SEQ_HEADER); + + mfc_debug_leave(); +} + +int mfc_core_cmd_dec_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + unsigned int reg = 0; + int ret; + + mfc_core_set_pixel_format(core, ctx, ctx->dst_fmt->fourcc); + + mfc_clean_core_ctx_int_flags(core_ctx); + ret = mfc_core_set_dec_codec_buffers(core_ctx); + if (ret) { + mfc_info("isn't enough codec buffer size, re-alloc!\n"); + + mfc_release_codec_buffers(core_ctx); + ret = mfc_alloc_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to allocate decoding buffers\n"); + return ret; + } + ret = mfc_core_set_dec_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to alloc frame mem\n"); + return ret; + } + } + + if (IS_MULTI_MODE(ctx)) { + reg |= ((ctx->subcore_inst_no & MFC_REG_RET_INSTANCE_ID_OF_MFC1_MASK) + << MFC_REG_RET_INSTANCE_ID_OF_MFC1_SHIFT); + reg |= (core_ctx->inst_no & MFC_REG_RET_INSTANCE_ID_MASK); + MFC_CORE_WRITEL(reg, MFC_REG_INSTANCE_ID); + } else { + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + } + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_INIT_BUFFERS); + + return ret; +} + +static int __mfc_set_scratch_dpb_buffer(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret; + + ret = mfc_alloc_scratch_buffer(core_ctx); + if (ret) { + mfc_err("Failed to allocate scratch buffers\n"); + return ret; + } + + /* set decoder DPB size, stride, scratch buffer */ + mfc_core_set_dec_dpb_and_scratch(core_ctx, core_ctx->scratch_buf.daddr); + + return 0; +} + +/* Decode a single frame */ +int mfc_core_cmd_dec_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, + int last_frame, int src_index) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec = ctx->dec_priv; + u32 reg = 0; + int ret = 0; + u32 timeout_value = MFC_TIMEOUT_VALUE; + unsigned long dynamic_set; + + if (dec->is_dynamic_dpb) + dynamic_set = core_ctx->dynamic_set; + else + dynamic_set = dec->dynamic_set; + + mfc_debug(2, "[MFC-%d][DPB] set dpb: %#lx, used: %#lx\n", + core->id, dynamic_set, dec->dynamic_used); + + reg = MFC_CORE_READL(MFC_REG_D_NAL_START_OPTIONS); + /* Black bar */ + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT); + reg |= ((dec->detect_black_bar & 0x1) << MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT); + if (core->dev->debugfs.feature_option & MFC_OPTION_BLACK_BAR_ENABLE) + reg |= BIT(MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT); + /* Scratch buf & DPB changes when interframe resolution change */ + if (dec->inter_res_change) { + ret = __mfc_set_scratch_dpb_buffer(core, ctx); + if (ret) + return ret; + reg |= BIT(MFC_REG_D_NAL_START_OPT_NEW_SCRATCH_SHIFT); + reg |= BIT(MFC_REG_D_NAL_START_OPT_NEW_DPB_SHIFT); + dec->inter_res_change = 0; + } else { + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_NEW_SCRATCH_SHIFT); + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_NEW_DPB_SHIFT); + } + + /* Operation core mode */ + mutex_lock(&ctx->op_mode_mutex); + + if ((ctx->stream_op_mode == MFC_OP_TWO_MODE1 || + ctx->stream_op_mode == MFC_OP_TWO_MODE2) && + ctx->op_mode != MFC_OP_SWITCH_BUT_MODE2) { + ctx->cmd_counter++; + mfc_debug(2, "[2CORE] cmd_counter : %d\n", ctx->cmd_counter); + } + + reg &= ~BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + if (IS_MULTI_MODE(ctx) || ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2) + reg |= BIT(MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + else + reg |= (0 << MFC_REG_D_NAL_START_OPT_TWO_MFC_ENABLE_SHIFT); + if (ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2) { + mfc_debug(2, "[2CORE] operate once op_mode %d\n", ctx->op_mode); + mfc_change_op_mode(ctx, MFC_OP_SWITCH_TO_SINGLE); + } else if (ctx->op_mode == MFC_OP_SWITCHING) { + mfc_err("[2CORE] It is a mode that can not operate\n"); + } else if (ctx->op_mode == MFC_OP_SWITCH_TO_SINGLE) { + ctx->last_op_core = core->id; + mfc_debug(2, "[2CORE] last_op_core of switch_to_single : %d\n", + ctx->last_op_core); + } + + /* If it is switched to single, interrupt lock is not needed. */ + if (IS_SWITCH_SINGLE_MODE(ctx)) + mfc_clear_core_intlock(ctx); + mutex_unlock(&ctx->op_mode_mutex); + MFC_CORE_WRITEL(reg, MFC_REG_D_NAL_START_OPTIONS); + mfc_debug(3, "NAL_START_OPTIONS: %#x, op_mode: %d\n", reg, ctx->op_mode); + + if (core->last_mfc_freq) + timeout_value = (core->last_mfc_freq * MFC_TIMEOUT_VALUE_IN_MSEC); + mfc_debug(2, "Last MFC Freq: %d, Timeout Value: %d\n", + core->last_mfc_freq, timeout_value); + + MFC_CORE_WRITEL(mfc_get_lower(dynamic_set), MFC_REG_D_DYNAMIC_DPB_FLAG_LOWER); + MFC_CORE_WRITEL(mfc_get_upper(dynamic_set), MFC_REG_D_DYNAMIC_DPB_FLAG_UPPER); + MFC_CORE_WRITEL(mfc_get_lower(dynamic_set), MFC_REG_D_AVAILABLE_DPB_FLAG_LOWER); + MFC_CORE_WRITEL(mfc_get_upper(dynamic_set), MFC_REG_D_AVAILABLE_DPB_FLAG_UPPER); + + MFC_CORE_WRITEL(dec->slice_enable, MFC_REG_D_SLICE_IF_ENABLE); + MFC_CORE_WRITEL(timeout_value, MFC_REG_TIMEOUT_VALUE); + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + + /* source index for 2core mode2 should set just before sent command */ + if (IS_TWO_MODE2(ctx) || IS_SWITCH_SINGLE_MODE(ctx)) { + mutex_lock(&ctx->op_mode_mutex); + mfc_debug(2, "[MFC-%d][STREAM] set cpb: %d, curr index: %d\n", + core->id, src_index, ctx->curr_src_index); + ctx->curr_src_index = src_index; + } + + /* + * Issue different commands to instance basing on whether it + * is the last frame or not. + */ + switch (last_frame) { + case 0: + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_NAL_START); + break; + case 1: + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_LAST_FRAME); + break; + } + + if (IS_TWO_MODE2(ctx) || IS_SWITCH_SINGLE_MODE(ctx)) + mutex_unlock(&ctx->op_mode_mutex); + + mfc_debug(2, "Decoding a usual frame\n"); + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h index 86b82d63f3b5..216d07c564ae 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h @@ -22,5 +22,14 @@ void mfc_core_cmd_wakeup(struct mfc_core *core); void mfc_core_cmd_open_inst(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_cmd_close_inst(struct mfc_core *core, struct mfc_ctx *ctx); void mfc_core_cmd_abort_inst(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_cmd_move_inst(struct mfc_core *core, struct mfc_ctx *ctx); + +void mfc_core_cmd_dpb_flush(struct mfc_core *core, struct mfc_ctx *ctx); void mfc_core_cmd_cache_flush(struct mfc_core *core); + +void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx); + +int mfc_core_cmd_dec_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_cmd_dec_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, + int last_frame, int src_index); #endif /* __MFC_CORE_CMD_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c index ec6699dbd451..6950b8451c3d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c @@ -42,3 +42,349 @@ void mfc_core_dbg_set_addr(struct mfc_core *core) MFC_CORE_WRITEL(core->dbg_info_buf.daddr, MFC_REG_DBG_BUFFER_ADDR); MFC_CORE_WRITEL(buf_size->dbg_info_buf, MFC_REG_DBG_BUFFER_SIZE); } + +unsigned int mfc_get_frame_error_type(struct mfc_ctx *ctx, unsigned int err) +{ + struct mfc_dev *dev = ctx->dev; + + if (!err) { + mfc_ctx_debug(4, "[FRAME] there is no error frame\n"); + return MFC_ERR_FRAME_NO_ERR; + } + + if (mfc_get_warn(err) == MFC_REG_ERR_BROKEN_LINK) { + mfc_ctx_debug(2, "[FRAME] Broken frame error (%d)\n", mfc_get_warn(err)); + return MFC_ERR_FRAME_BROKEN; + } else if (mfc_get_warn(err) == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED) { + mfc_ctx_debug(2, "[FRAME] Sync point frame error (%d), type %d\n", + mfc_get_warn(err), dev->pdata->display_err_type); + return dev->pdata->display_err_type; + } + + mfc_ctx_debug(2, "[FRAME] Concealment frame error (%d)\n", mfc_get_warn(err)); + return MFC_ERR_FRAME_CONCEALMENT; +} + +void mfc_core_set_dec_dpb_and_scratch(struct mfc_core_ctx *core_ctx, dma_addr_t scratch_addr) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw; + int i; + + raw = &ctx->raw_buf; + + MFC_CORE_WRITEL(dec->total_dpb_count, MFC_REG_D_NUM_DPB); + for (i = 0; i < raw->num_planes; i++) { + mfc_debug(2, "[FRAME] buf[%d] size: %d, stride: %d\n", + i, raw->plane_size[i], raw->stride[i]); + MFC_CORE_WRITEL(raw->plane_size[i], MFC_REG_D_FIRST_PLANE_DPB_SIZE + (i * 4)); + MFC_CORE_WRITEL(raw->stride[i], + MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE + (i * 4)); + } + + /* set scratch buffer */ + MFC_CORE_DMA_WRITEL(scratch_addr, MFC_REG_D_SCRATCH_BUFFER_ADDR); + MFC_CORE_WRITEL(ctx->scratch_buf_size, MFC_REG_D_SCRATCH_BUFFER_SIZE); + mfc_debug(2, "[FRAME] scratch buf addr: 0x%#llx size %ld\n", + scratch_addr, ctx->scratch_buf_size); +} + +/* Set decoding frame buffer */ +int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + unsigned int i; + size_t frame_size_mv; + dma_addr_t buf_addr; + int buf_size; + int align_gap; + unsigned int reg = 0; + + buf_addr = core_ctx->codec_buf.daddr; + buf_size = core_ctx->codec_buf.size; + + mfc_debug(2, "[MEMINFO] codec buf 0x%llx size: %d\n", buf_addr, buf_size); + mfc_debug(2, "Total DPB COUNT: %d, display delay: %d\n", + dec->total_dpb_count, dec->display_delay); + + if (core_ctx->codec_buffer_allocated && buf_size && + buf_size > core_ctx->codec_buf.dma_buf->size) { + mfc_info("[MEMINFO] Not enough codec buf size %d alloc size %zu\n", + buf_size, core_ctx->codec_buf.dma_buf->size); + return -ENOMEM; + } + + /* set decoder DPB size, stride, scratch buffer */ + mfc_core_set_dec_dpb_and_scratch(core_ctx, buf_addr); + buf_addr += ctx->scratch_buf_size; + buf_size -= ctx->scratch_buf_size; + + if (IS_H264_DEC(ctx)) + MFC_CORE_WRITEL(ctx->mv_size, MFC_REG_D_MV_BUFFER_SIZE); + + reg |= (dec->is_dynamic_dpb << MFC_REG_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT); + + /* 16byte align, It is valid only for VP9 */ + reg &= ~BIT(MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); + + reg &= ~BIT(MFC_REG_D_INIT_BUF_OPT_TWO_MODE_ENABLE_SHIFT); + if (IS_MULTI_MODE(ctx)) { + reg |= BIT(MFC_REG_D_INIT_BUF_OPT_TWO_MODE_ENABLE_SHIFT); + mfc_debug(2, "[2CORE] two mode(op_mode: %d) enable, reg %#x\n", + ctx->op_mode, reg); + } + + if (dev->pdata->support_mv_hevc) + reg |= BIT(MFC_REG_D_INIT_BUF_OPT_ENABLE_DECODE_VIEW1); + else + reg &= ~BIT(MFC_REG_D_INIT_BUF_OPT_ENABLE_DECODE_VIEW1); + MFC_CORE_WRITEL(reg, MFC_REG_D_INIT_BUFFER_OPTIONS); + + mfc_debug(2, "[MEMINFO] codec buf remained size: %d\n", buf_size); + if (buf_size < 0) { + mfc_debug(2, "[MEMINFO] Not enough memory has been allocated\n"); + return -ENOMEM; + } + + /* MV buffers */ + buf_addr = ctx->mv_buf.daddr; + buf_size = ctx->mv_buf.size; + mfc_debug(2, "[MEMINFO] MV buf 0x%llx size: %d\n", buf_addr, buf_size); + + frame_size_mv = ctx->mv_size; + MFC_CORE_WRITEL(dec->mv_count, MFC_REG_D_NUM_MV); + if (IS_H264_DEC(ctx)) { + if (ctx->mv_buffer_allocated && buf_size && + buf_size > ctx->mv_buf.dma_buf->size) { + mfc_info("[MEMINFO] Not enough MV buf size %d alloc size %zu\n", + buf_size, ctx->mv_buf.dma_buf->size); + return -ENOMEM; + } + + for (i = 0; i < dec->mv_count; i++) { + align_gap = buf_addr; + buf_addr = ALIGN(buf_addr, 16); + align_gap = buf_addr - align_gap; + buf_size -= align_gap; + + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_D_MV_BUFFER0 + i * 4); + buf_addr += frame_size_mv; + buf_size -= frame_size_mv; + } + } + + mfc_debug(2, "[MEMINFO] MV buf remained size: %d\n", buf_size); + if (buf_size < 0) { + mfc_debug(2, "[MEMINFO] Not enough memory has been allocated\n"); + return -ENOMEM; + } + + return 0; +} + +/* Set registers for decoding stream buffer */ +int mfc_core_set_dec_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, unsigned int start_num_byte, + unsigned int strm_size) +{ + size_t need_cpb_buf_size = 0, buf_size = 0; + dma_addr_t addr = 0; + struct vb2_buffer *vb = NULL; + + mfc_ctx_debug_enter(); + + if (mfc_buf) { + vb = &mfc_buf->vb.vb2_buf; + addr = mfc_buf->addr[0][0]; + + if (core->dev->pdata->stream_buf_limit) { + need_cpb_buf_size = ALIGN(strm_size + 511, STREAM_BUF_ALIGN); + buf_size = mfc_buf->sg_size; + } else { + need_cpb_buf_size = strm_size; + buf_size = vb->planes[0].dbuf->size; + } + + if (buf_size < need_cpb_buf_size) + mfc_ctx_info("Decrease buffer size: %zu(need) -> %zu(alloc)\n", + need_cpb_buf_size, buf_size); + + mfc_ctx_debug(2, "[BUFINFO] set src index: %d(%d), addr: 0x%08llx\n", + vb->index, mfc_buf->src_index, addr); + } + + mfc_ctx_debug(2, "[STREAM] strm_size, %#x, %d, offset, %#x, %u, need_buf_size, %zu, buf_size, %zu\n", + strm_size, strm_size, start_num_byte, start_num_byte, + need_cpb_buf_size, buf_size); + + if (strm_size == 0) + mfc_ctx_info("stream size is 0\n"); + + MFC_CORE_WRITEL(strm_size, MFC_REG_D_STREAM_DATA_SIZE); + MFC_CORE_DMA_WRITEL(addr, MFC_REG_D_CPB_BUFFER_ADDR); + MFC_CORE_WRITEL(buf_size, MFC_REG_D_CPB_BUFFER_SIZE); + MFC_CORE_WRITEL(start_num_byte, MFC_REG_D_CPB_BUFFER_OFFSET); + ctx->last_src_addr = addr; + + mfc_ctx_debug_leave(); + return 0; +} + +void mfc_core_set_dynamic_dpb(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *dst_mb) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw = &ctx->raw_buf; + int index_view = ctx->select_view == MFC_VIEW_ID_MAIN ? MFC_MV_BUF_IDX_VIEW0 + : MFC_MV_BUF_IDX_VIEW1; + /* offset about fd */ + int offset = ctx->view_buf_info[index_view].offset; + int dst_index; + int i; + + if (ctx->select_view == MFC_VIEW_ID_MAIN) + dst_index = dst_mb->dpb_index; + else + dst_index = dst_mb->dpb_index + MFC_MAX_DPBS / 2; + + /* for debugging about black bar detection */ + if ((MFC_FEATURE_SUPPORT(dev, dev->pdata->black_bar) && dec->detect_black_bar) || + (dev->debugfs.feature_option & MFC_OPTION_BLACK_BAR_ENABLE)) { + for (i = 0; i < raw->num_planes; i++) { + dec->frame_vaddr[i][dec->frame_cnt] = + vb2_plane_vaddr(&dst_mb->vb.vb2_buf, i); + dec->frame_daddr[i][dec->frame_cnt] = dst_mb->addr[0][i]; + dec->frame_size[i][dec->frame_cnt] = raw->plane_size[i]; + dec->index[i][dec->frame_cnt] = dst_index; + dec->fd[i][dec->frame_cnt] = dst_mb->vb.vb2_buf.planes[0].m.fd; + } + dec->frame_cnt++; + if (dec->frame_cnt >= 30) + dec->frame_cnt = 0; + } + + for (i = 0; i < raw->num_planes; i++) { + MFC_CORE_WRITEL(raw->plane_size[i], + MFC_REG_D_FIRST_PLANE_DPB_SIZE + i * 4); + MFC_CORE_DMA_WRITEL(dst_mb->addr[index_view][i], + MFC_REG_D_FIRST_PLANE_DPB0 + (i * 0x100 + dst_index * 4)); + ctx->last_dst_addr[i] = dst_mb->addr[index_view][i]; + mfc_debug(2, "%s[%d][%d], addr[%d]: 0x%08llx, fd: %d, size: %d%s %d, offset: %d\n", + "[BUFINFO][DPB] set dst index: ", dst_mb->vb.vb2_buf.index, + dst_mb->dpb_index, i, + dst_mb->addr[index_view][i], dst_mb->vb.vb2_buf.planes[offset + i].m.fd, + raw->plane_size[i], + ", index_view:", index_view, + offset); + } + + MFC_TRACE_CORE_CTX("Set dst[%d] fd: %d, %#llx / used %#lx\n", + dst_index, dst_mb->vb.vb2_buf.planes[offset].m.fd, + dst_mb->addr[index_view][0], dec->dynamic_used); +} + +void mfc_core_get_img_size(struct mfc_core *core, struct mfc_ctx *ctx, + enum mfc_get_img_size img_size) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned int w, h; + int i; + + w = ctx->img_width; + h = ctx->img_height; + + ctx->img_width = mfc_core_get_img_width(); + ctx->img_height = mfc_core_get_img_height(); + ctx->crop_width = ctx->img_width; + ctx->crop_height = ctx->img_height; + + for (i = 0; i < ctx->dst_fmt->num_planes; i++) + ctx->raw_buf.stride[i] = mfc_core_get_stride_size(i); + + mfc_ctx_debug(2, "[FRAME][DRC] resolution changed, %dx%d => %dx%d (stride: %d)\n", w, h, + ctx->img_width, ctx->img_height, ctx->raw_buf.stride[0]); + + if (img_size == MFC_GET_RESOL_SIZE) { + dec->disp_drc.width[dec->disp_drc.push_idx] = ctx->img_width; + dec->disp_drc.height[dec->disp_drc.push_idx] = ctx->img_height; + dec->disp_drc.disp_res_change++; + mfc_ctx_debug(3, "[DRC] disp_res_change[%d] count %d\n", + dec->disp_drc.push_idx, dec->disp_drc.disp_res_change); + dec->disp_drc.push_idx = (dec->disp_drc.push_idx + 1) % MFC_MAX_DRC_FRAME; + } else if (img_size == MFC_GET_RESOL_DPB_SIZE) { + ctx->scratch_buf_size = mfc_core_get_scratch_size(); + for (i = 0; i < ctx->dst_fmt->num_planes; i++) + ctx->min_dpb_size[i] = mfc_core_get_min_dpb_size(i); + + mfc_ctx_debug(2, "[FRAME][DRC] DPB count %d, %s %d(%#x) %s %d scratch %zu(%#zx)\n", + ctx->dpb_count, "min_dpb_size", ctx->min_dpb_size[0], + ctx->min_dpb_size[0], "min_dpb_size_2bits", + ctx->min_dpb_size_2bits[0], + ctx->scratch_buf_size, ctx->scratch_buf_size); + } +} + +void mfc_core_set_pixel_format(struct mfc_core *core, struct mfc_ctx *ctx, + unsigned int format) +{ + unsigned int reg = 0; + unsigned int pix_val; + unsigned int block_align = 0; + + switch (format) { + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV12MT_16X16: + case V4L2_PIX_FMT_NV16M: + pix_val = 0; + break; + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_NV61M: + pix_val = 1; + break; + case V4L2_PIX_FMT_YVU420M: + pix_val = 2; + break; + case V4L2_PIX_FMT_YUV420M: + pix_val = 3; + break; + case V4L2_PIX_FMT_ARGB32: + pix_val = 8; + break; + case V4L2_PIX_FMT_RGB24: + pix_val = 9; + break; + case V4L2_PIX_FMT_RGB565: + pix_val = 10; + break; + case V4L2_PIX_FMT_RGB32: + pix_val = 11; + break; + case V4L2_PIX_FMT_RGB32X: + pix_val = 12; + break; + case V4L2_PIX_FMT_BGR32: + pix_val = 13; + break; + default: + pix_val = 0; + break; + } + mfc_set_bits(reg, 0xf, 0, pix_val); + + /* for YUV format */ + if (pix_val < 4) + mfc_set_bits(reg, 0x3, 4, ctx->mem_type_10bit); + + mfc_set_bits(reg, 0x3, 10, block_align); + + MFC_CORE_WRITEL(reg, MFC_REG_PIXEL_FORMAT); + mfc_ctx_debug(2, "[FRAME] pix format: %d, mem_type_10bit: %d, (reg: %#x)\n", + pix_val, ctx->mem_type_10bit, reg); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h index a23d25edce5d..e7c28b2f2b5d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h @@ -13,6 +13,7 @@ #define __MFC_CORE_REG_API_H __FILE__ #include "base/mfc_regs.h" + #include "base/mfc_utils.h" /* version */ @@ -34,13 +35,226 @@ #define mfc_core_get_mfc_version() ((MFC_CORE_READL(MFC_REG_MFC_VERSION) \ >> MFC_REG_MFC_VER_SHFT) \ & MFC_REG_MFC_VER_MASK) +#define mfc_core_get_processing_cycle() MFC_CORE_READL(MFC_REG_PROCESSING_CYCLE) + +/* decoding & display information */ +#define mfc_core_get_dec_status() (MFC_CORE_READL(MFC_REG_D_DECODED_STATUS) \ + & MFC_REG_DEC_STATUS_DECODED_STATUS_MASK) +#define mfc_core_get_disp_status() (MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK) +#define mfc_core_get_res_change() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_RES_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_RES_CHANGE_MASK) +#define mfc_core_get_black_bar_detection() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_SHIFT) \ + & MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_MASK) +#define mfc_core_get_decoded_frame_cnt() MFC_CORE_READL(MFC_REG_D_DECODED_FRAME_COUNT) +#define mfc_core_get_display_frame_cnt() MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_COUNT) +#define mfc_core_get_dpb_change() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_MASK) +#define mfc_core_get_scratch_change() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK) +#define mfc_core_get_uncomp() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_UNCOMP_SHIFT) \ + & MFC_REG_DISP_STATUS_UNCOMP_MASK) +#define mfc_core_get_last_display() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_LAST_DISPLAY_FRAME_SHIFT) \ + & MFC_REG_DISP_STATUS_LAST_DISPLAY_FRAME_MASK) + +#define mfc_core_get_disp_frame_type() (MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_TYPE) \ + & MFC_REG_DISPLAY_FRAME_MASK) +#define mfc_core_get_dec_frame_type() (MFC_CORE_READL(MFC_REG_D_DECODED_FRAME_TYPE) \ + & MFC_REG_DECODED_FRAME_MASK) +#define mfc_core_get_disp_idr_flag() \ + ((MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_TYPE) \ + >> MFC_REG_DISPLAY_IDR_FLAG_SHIFT) \ + & MFC_REG_DISPLAY_IDR_FLAG_MASK) +#define mfc_core_get_dec_idr_flag() \ + ((MFC_CORE_READL(MFC_REG_D_DECODED_FRAME_TYPE) \ + >> MFC_REG_DECODED_IDR_FLAG_SHIFT) \ + & MFC_REG_DECODED_IDR_FLAG_MASK) +#define mfc_core_get_dec_temporal_id() \ + ((MFC_CORE_READL(MFC_REG_D_H264_INFO) \ + >> MFC_REG_D_H264_INFO_TEMPORAL_ID_SHIFT) \ + & MFC_REG_D_H264_INFO_TEMPORAL_ID_MASK) +#define mfc_core_get_interlace_type() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_TYPE) \ + >> MFC_REG_DISPLAY_TEMP_INFO_SHIFT) \ + & MFC_REG_DISPLAY_TEMP_INFO_MASK) +#define mfc_core_is_interlace_picture() ((MFC_CORE_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_INTERLACE_SHIFT)\ + & MFC_REG_DISP_STATUS_INTERLACE_MASK) +#define mfc_core_is_mbaff_picture() ((MFC_CORE_READL(MFC_REG_D_H264_INFO) \ + >> MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT)\ + & MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_MASK) + +#define mfc_core_get_img_width() MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_WIDTH) +#define mfc_core_get_img_height() MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_HEIGHT) +#define mfc_core_get_disp_y_addr() MFC_CORE_DMA_READL(MFC_REG_D_DISPLAY_LUMA_ADDR) +#define mfc_core_get_dec_y_addr() MFC_CORE_DMA_READL(MFC_REG_D_DECODED_LUMA_ADDR) +#define mfc_core_get_crc_luma() MFC_CORE_READL(MFC_REG_D_DISPLAY_FIRST_PLANE_CRC) +#define mfc_core_get_crc_chroma() MFC_CORE_READL(MFC_REG_D_DISPLAY_SECOND_PLANE_CRC) /* kind of interrupt */ #define mfc_core_get_int_err() MFC_CORE_READL(MFC_REG_ERROR_CODE) +/* additional information */ +#define mfc_core_get_consumed_stream() MFC_CORE_READL(MFC_REG_D_DECODED_NAL_SIZE) +#define mfc_core_get_dpb_count() MFC_CORE_READL(MFC_REG_D_MIN_NUM_DPB) +#define mfc_core_get_min_dpb_size(x) \ + MFC_CORE_READL(MFC_REG_D_MIN_FIRST_PLANE_DPB_SIZE + ((x) * 4)) +#define mfc_core_get_scratch_size() MFC_CORE_READL(MFC_REG_D_MIN_SCRATCH_BUFFER_SIZE) +#define mfc_core_get_stride_size(x) \ + MFC_CORE_READL(MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE + ((x) * 4)) + +#define mfc_core_get_mv_count() MFC_CORE_READL(MFC_REG_D_MIN_NUM_MV) #define mfc_core_get_inst_no() MFC_CORE_READL(MFC_REG_RET_INSTANCE_ID) +#define mfc_core_get_sei_avail() MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) +#define mfc_core_get_sei_content_light() \ + MFC_CORE_READL(MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI) +#define mfc_core_get_sei_mastering0() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0) +#define mfc_core_get_sei_mastering1() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1) +#define mfc_core_get_sei_mastering2() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2) +#define mfc_core_get_sei_mastering3() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3) +#define mfc_core_get_sei_mastering4() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4) +#define mfc_core_get_sei_mastering5() \ + MFC_CORE_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5) +#define mfc_core_get_sei_avail_frame_pack() (MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) \ + & MFC_REG_D_SEI_AVAIL_FRAME_PACK_MASK) +#define mfc_core_get_sei_avail_content_light() ((MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) \ + >> MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT) \ + & MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_MASK) +#define mfc_core_get_sei_avail_mastering_display() ((MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) \ + >> MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) \ + & MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK) + +#define mfc_core_get_video_signal_type() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) \ + & MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK) +#define mfc_core_get_colour_description() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT) \ + & MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK) + +#define mfc_core_get_black_bar_pos_x() ((MFC_CORE_READL(MFC_REG_D_BLACK_BAR_START_POS) \ + >> MFC_REG_D_BLACK_BAR_START_X_SHIFT) \ + & MFC_REG_D_BLACK_BAR_START_X_MASK) +#define mfc_core_get_black_bar_pos_y() ((MFC_CORE_READL(MFC_REG_D_BLACK_BAR_START_POS) \ + >> MFC_REG_D_BLACK_BAR_START_Y_SHIFT) \ + & MFC_REG_D_BLACK_BAR_START_Y_MASK) +#define mfc_core_get_black_bar_image_w() ((MFC_CORE_READL(MFC_REG_D_BLACK_BAR_IMAGE_SIZE) \ + >> MFC_REG_D_BLACK_BAR_IMAGE_W_SHIFT) \ + & MFC_REG_D_BLACK_BAR_IMAGE_W_MASK) +#define mfc_core_get_black_bar_image_h() ((MFC_CORE_READL(MFC_REG_D_BLACK_BAR_IMAGE_SIZE) \ + >> MFC_REG_D_BLACK_BAR_IMAGE_H_SHIFT) \ + & MFC_REG_D_BLACK_BAR_IMAGE_H_MASK) +#define mfc_core_get_mvc_disp_view_id() (MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ + & MFC_REG_D_MVC_VIEW_ID_DISP_MASK) +#define mfc_core_get_mvc_view_id_dec_order() ((MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ + >> MFC_REG_D_MVC_VIEW_ID_DEC_SHIFT) \ + & MFC_REG_D_MVC_VIEW_ID_DEC_MASK) +#define mfc_core_get_mvc_view_id_disp_order() (MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ + & MFC_REG_D_MVC_VIEW_ID_DISP_MASK) +#define mfc_core_get_mvc_right_view_id() ((MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ + >> MFC_REG_D_MVC_RIGHT_VIEW_ID_SHIFT) \ + & MFC_REG_D_MVC_RIGHT_VIEW_ID_MASK) +#define mfc_core_get_profile() (MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + & MFC_REG_D_DECODED_PIC_PROFILE_MASK) + +#define mfc_core_get_display_delay() \ + ((MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_DISPLAY_DELAY_SHIFT) \ + & MFC_REG_D_DISPLAY_DELAY_MASK) +#define mfc_core_get_two_core_mode() \ + ((MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_TWO_MFC_MODE_SHIFT) \ + & MFC_REG_D_TWO_MFC_MODE_MASK) +#define mfc_core_get_dec_used_flag() (((unsigned long)(MFC_CORE_READL \ + (MFC_REG_D_USED_DPB_FLAG_UPPER)) << 32) | \ + MFC_CORE_READL(MFC_REG_D_USED_DPB_FLAG_LOWER)) + +#define mfc_core_get_num_of_tile() ((MFC_CORE_READL(MFC_REG_D_DECODED_STATUS) \ + >> MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT) \ + & MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK) + +static inline void mfc_core_dec_get_crop_info(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + u32 left, right, top, bottom; + + left = MFC_CORE_READL(MFC_REG_D_DISPLAY_CROP_INFO1); + right = left >> MFC_REG_D_SHARED_CROP_RIGHT_SHIFT; + left = left & MFC_REG_D_SHARED_CROP_LEFT_MASK; + top = MFC_CORE_READL(MFC_REG_D_DISPLAY_CROP_INFO2); + bottom = top >> MFC_REG_D_SHARED_CROP_BOTTOM_SHIFT; + top = top & MFC_REG_D_SHARED_CROP_TOP_MASK; + + dec->cr_left = left; + dec->cr_right = right; + dec->cr_top = top; + dec->cr_bot = bottom; +} + +static inline void mfc_core_update_tag(struct mfc_core *core, struct mfc_ctx *ctx, + int tag) +{ + if (MFC_CORE_READL(MFC_REG_D_PICTURE_TAG) != tag) { + mfc_ctx_debug(2, "reused src's tag is different so update to %d\n", + tag); + MFC_CORE_WRITEL(tag, MFC_REG_D_PICTURE_TAG); + } +} + +static inline void mfc_core_set_migration_addr(struct mfc_core *core, struct mfc_ctx *ctx, + dma_addr_t fw_addr, dma_addr_t common_ctx_addr) +{ + struct mfc_special_buf *ctx_buf = NULL; + + ctx_buf = &core->common_ctx_buf; + + MFC_CORE_DMA_WRITEL(fw_addr, MFC0_REG_RISC_BASE_ADDR); + MFC_CORE_WRITEL(common_ctx_addr, MFC0_REG_COMMON_CONTEXT_MEM_ADDR); + MFC_CORE_WRITEL(ctx_buf->daddr, MFC1_REG_COMMON_CONTEXT_MEM_ADDR); + mfc_core_debug(2, "migration MFC0 FW base: %#llx, context: %#llx, MFC1 context: %#llx\n", + fw_addr, common_ctx_addr, ctx_buf->daddr); +} + +static inline void mfc_core_clear_main_core_context_flush_done(struct mfc_core *core) +{ + /* + * When op_mode is changed from single to multi, + * by calling NAL_START of both core simultaneously, + * FW can get the invalid information of main core. + * So, when switching op_mode to multi-core mode, + * clear the status of main core about this. + */ + MFC_CORE_WRITEL(0, MFC0_REG_CONTEXT_FLUSH_DONE); + MFC_TRACE_CORE("Clear MAIN_CORE_CONTEXT_FLUSH_DONE\n"); +} void mfc_core_dbg_enable(struct mfc_core *core); void mfc_core_dbg_disable(struct mfc_core *core); void mfc_core_dbg_set_addr(struct mfc_core *core); + +unsigned int mfc_get_frame_error_type(struct mfc_ctx *ctx, unsigned int err); + +void mfc_core_set_dec_dpb_and_scratch(struct mfc_core_ctx *core_ctx, dma_addr_t scratch_addr); +int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx); +int mfc_core_set_dec_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, unsigned int start_num_byte, + unsigned int buf_size); + +void mfc_core_set_dynamic_dpb(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *dst_vb); + +void mfc_core_get_img_size(struct mfc_core *core, struct mfc_ctx *ctx, + enum mfc_get_img_size img_size); +void mfc_core_set_pixel_format(struct mfc_core *core, struct mfc_ctx *ctx, + unsigned int format); #endif /* __MFC_CORE_REG_API_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c index de13cdb9c99a..e4b839eda2da 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c @@ -13,6 +13,9 @@ #include "mfc_core_hw_reg_api.h" +#include "base/mfc_qos.h" +#include "base/mfc_queue.h" + #define R2H_BIT(x) ({ \ typeof(x) _x = (x); \ (_x > 0) ? BIT(_x - 1) : 0; \ @@ -40,10 +43,26 @@ static inline unsigned int __mfc_r2h_bit_mask(int cmd) void mfc_get_corelock_ctx(struct mfc_ctx *ctx) { unsigned long flags; + unsigned int timeout = MFC_INT_TIMEOUT * MFC_INT_TIMEOUT_CNT; + int ret; spin_lock_irqsave(&ctx->corelock.lock, flags); - mfc_ctx_debug(3, "[CORELOCK] get_corelock: cnt %d\n", - ctx->corelock.cnt); + mfc_ctx_debug(3, "[CORELOCK] get_corelock: cnt %d, migrate %d\n", + ctx->corelock.cnt, ctx->corelock.migrate); + + if (ctx->corelock.migrate) { + spin_unlock_irqrestore(&ctx->corelock.lock, flags); + mfc_ctx_debug(2, "[CORELOCK] now migration... start waiting corelock\n"); + ret = wait_event_timeout(ctx->corelock.migrate_wq, + (ctx->corelock.migrate == 0), + msecs_to_jiffies(timeout)); + if (ret == 0) + mfc_ctx_err("[CORELOCK] waiting corelock for migration timed out\n"); + else + mfc_ctx_debug(2, "[CORELOCK] finished waiting corelock for migration\n"); + + spin_lock_irqsave(&ctx->corelock.lock, flags); + } ctx->corelock.cnt++; @@ -62,8 +81,57 @@ void mfc_release_corelock_ctx(struct mfc_ctx *ctx) else if (ctx->corelock.cnt < 0) mfc_ctx_err("[CORELOCK] wrong corelock cnt %d\n", ctx->corelock.cnt); - mfc_ctx_debug(3, "[CORELOCK] release_corelock: cnt %d\n", - ctx->corelock.cnt); + mfc_ctx_debug(3, "[CORELOCK] release_corelock: cnt %d, migrate %d\n", + ctx->corelock.cnt, ctx->corelock.migrate); + spin_unlock_irqrestore(&ctx->corelock.lock, flags); +} + +int mfc_get_corelock_migrate(struct mfc_ctx *ctx) +{ + unsigned long flags; + unsigned int timeout = MFC_INT_TIMEOUT * MFC_INT_TIMEOUT_CNT; + int ret; + + spin_lock_irqsave(&ctx->corelock.lock, flags); + ctx->corelock.migrate = 1; + mfc_ctx_debug(2, "[CORELOCK] get_corelock_migrate: cnt %d, migrate %d\n", + ctx->corelock.cnt, ctx->corelock.migrate); + + if (ctx->corelock.cnt) { + spin_unlock_irqrestore(&ctx->corelock.lock, flags); + mfc_ctx_debug(2, "[CORELOCK] start waiting corelock\n"); + ret = wait_event_timeout(ctx->corelock.wq, + (ctx->corelock.cnt == 0), + msecs_to_jiffies(timeout)); + if (ret == 0) { + spin_lock_irqsave(&ctx->corelock.lock, flags); + ctx->corelock.migrate = 0; + wake_up(&ctx->corelock.migrate_wq); + spin_unlock_irqrestore(&ctx->corelock.lock, flags); + mfc_ctx_err("[CORELOCK] waiting corelock timed out (%d)\n", + ctx->corelock.cnt); + return -EBUSY; + } + + mfc_ctx_debug(2, "[CORELOCK] finished waiting corelock\n"); + spin_lock_irqsave(&ctx->corelock.lock, flags); + } + + spin_unlock_irqrestore(&ctx->corelock.lock, flags); + + return 0; +} + +void mfc_release_corelock_migrate(struct mfc_ctx *ctx) +{ + unsigned long flags; + + spin_lock_irqsave(&ctx->corelock.lock, flags); + + ctx->corelock.migrate = 0; + mfc_ctx_debug(2, "[CORELOCK] wakeup migration wait\n"); + wake_up(&ctx->corelock.migrate_wq); + spin_unlock_irqrestore(&ctx->corelock.lock, flags); } @@ -188,3 +256,114 @@ void mfc_wake_up_core(struct mfc_core *core, unsigned int reason, core->int_err = err; wake_up(&core->cmd_wq); } + +/* Wake up context wait_queue */ +void mfc_wake_up_core_ctx(struct mfc_core_ctx *core_ctx, unsigned int reason, + unsigned int err) +{ + core_ctx->int_condition = 1; + core_ctx->int_reason = reason; + core_ctx->int_err = err; + wake_up(&core_ctx->cmd_wq); +} + +static int __mfc_dec_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + int is_ready = 0; + int src_buf_cnt, dst_buf_cnt; + + src_buf_cnt = mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue); + dst_buf_cnt = mfc_get_available_dpb_count(core_ctx); + + /* Context is to parse header */ + if (core_ctx->state == MFCINST_GOT_INST && src_buf_cnt) + is_ready = 1; + + /* Context is to decode a frame */ + else if ((core_ctx->state == MFCINST_RUNNING) && (ctx->wait_state == WAIT_NONE)) { + if (src_buf_cnt && dst_buf_cnt) + is_ready = 1; + } + + /* Context is to return last frame */ + else if (core_ctx->state == MFCINST_FINISHING && dst_buf_cnt) + is_ready = 1; + + /* Context is to set buffers */ + else if (core_ctx->state == MFCINST_HEAD_PARSED && + (ctx->wait_state == WAIT_NONE && dst_buf_cnt)) + is_ready = 1; + + /* Resolution change + * In the case of 2core DRC, state could be SWITCH_TO_SINGLE. + * After subcore deinit, state will be changed to SINGLE. + */ + else if ((core_ctx->state == MFCINST_RES_CHANGE_INIT || + core_ctx->state == MFCINST_RES_CHANGE_FLUSH || + core_ctx->state == MFCINST_RES_CHANGE_FLUSH_FINISHED) && dst_buf_cnt && + (IS_SINGLE_MODE(ctx) || ctx->op_mode == MFC_OP_SWITCH_TO_SINGLE)) + is_ready = 1; + + else if (core_ctx->state == MFCINST_RES_CHANGE_END && src_buf_cnt) + is_ready = 1; + + return is_ready; +} + +int mfc_ctx_ready_set_bit_raw(struct mfc_core_ctx *core_ctx, unsigned long *bits, bool set) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_ctx *ctx = core_ctx->ctx; + int is_ready = 0; + + /* If shutdown is called, do not try any cmd */ + if (core->shutdown) + return 0; + + mfc_debug(1, "[MFC-%d][c:%d] src = %d(ready = %d), dst = %d, state = %d, capstat = %d, waitstat = %d\n", + core->id, ctx->num, + mfc_get_queue_count(&ctx->buf_queue_lock, + &core_ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, + &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, + &ctx->dst_buf_queue), + core_ctx->state, ctx->capture_state, ctx->wait_state); + + is_ready = __mfc_dec_ctx_ready_set_bit(core_ctx); + + if (is_ready && set) { + /* if the ctx is ready and request set_bit, set the work_bit */ + __set_bit(ctx->num, bits); + } else if (!is_ready && !set) { + /* if the ctx is not ready and request clear_bit, clear the work_bit */ + __clear_bit(ctx->num, bits); + } else { + if (set) { + /* If the ctx is not ready, this is not included to S/W driver margin */ + mfc_debug(2, "ctx is not ready\n"); + } + } + + return is_ready; +} + +static int __mfc_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx, + struct mfc_bits *data, bool set) +{ + unsigned long flags; + int is_ready = 0; + + /* The ready condition check and set work_bit should be synchronized */ + spin_lock_irqsave(&data->lock, flags); + is_ready = mfc_ctx_ready_set_bit_raw(core_ctx, &data->bits, set); + spin_unlock_irqrestore(&data->lock, flags); + + return is_ready; +} + +int mfc_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx, struct mfc_bits *data) +{ + return __mfc_ctx_ready_set_bit(core_ctx, data, true); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h index 2c19819048de..94c1128b16cc 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h @@ -16,10 +16,19 @@ void mfc_get_corelock_ctx(struct mfc_ctx *ctx); void mfc_release_corelock_ctx(struct mfc_ctx *ctx); +int mfc_get_corelock_migrate(struct mfc_ctx *ctx); +void mfc_release_corelock_migrate(struct mfc_ctx *ctx); int mfc_wait_for_done_core(struct mfc_core *core, int command); int mfc_wait_for_done_core_ctx(struct mfc_core_ctx *core_ctx, int command); void mfc_wake_up_core(struct mfc_core *core, unsigned int reason, unsigned int err); +void mfc_wake_up_core_ctx(struct mfc_core_ctx *core_ctx, unsigned int reason, + unsigned int err); + int mfc_core_get_new_ctx(struct mfc_core *core); + +int mfc_ctx_ready_set_bit_raw(struct mfc_core_ctx *core_ctx, unsigned long *bits, bool set); +int mfc_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx, struct mfc_bits *data); + #endif /* __MFC_CORE_SYNC_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035619epcas5p1a3a8cd3e71442235e571c840a78286d8@epcas5p1.samsung.com>]
* [PATCH 14/29] media: mfc: Add buffer‑control framework [not found] ` <CGME20250930035619epcas5p1a3a8cd3e71442235e571c840a78286d8@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Add core buffer‑control module (mfc_core_buf_ctrl.c) with set/get/recover/restore ops. - Add context‑control layer (mfc_ctx_ctrl.c) defining V4L2 decoder controls and per‑buffer handling. - Export mfc_bufs_ops and mfc_ctrls_ops for integration with existing MFC core Provide flexible V4L2‑based management of hardware registers, including volatile/non‑volatile settings and buffer‑level restore/recovery. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 4 +- .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 160 +++++ .../samsung/exynos-mfc/mfc_ctx_ctrl.c | 666 ++++++++++++++++++ 3 files changed, 828 insertions(+), 2 deletions(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index 9def2686cd4e..19e38c886255 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -5,7 +5,7 @@ ccflags-y += -I$(srctree)/$(src) #Dev interface layer exynos_mfc-y += mfc.o #Dev control layer -exynos_mfc-y += mfc_rm.o mfc_debugfs.o +exynos_mfc-y += mfc_rm.o mfc_ctx_ctrl.o mfc_debugfs.o #Core interface layer exynos_mfc-y += mfc_core.o mfc_core_ops.o mfc_core_isr.o #Core control layer @@ -13,7 +13,7 @@ exynos_mfc-y += mfc_core_hwlock.o mfc_core_intlock.o mfc_core_run.o exynos_mfc-y += mfc_core_pm.o exynos_mfc-y += mfc_core_sync.o mfc_core_sched_prio.o #Core HW access layer -exynos_mfc-y += mfc_core_cmd.o +exynos_mfc-y += mfc_core_buf_ctrl.o mfc_core_cmd.o exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o #Plugin interface layer #Plugin control layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c new file mode 100644 index 000000000000..56dc3e734d02 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_buf_ctrl.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_reg_api.h" + +static int mfc_core_set_buf_ctrls(struct mfc_core *core, + struct mfc_ctx *ctx, struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + unsigned int value = 0; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) || !buf_ctrl->has_new) + continue; + + if (buf_ctrl->mode == MFC_CTRL_MODE_SFR) { + /* read old vlaue */ + value = MFC_CORE_READL(buf_ctrl->addr); + + /* save old vlaue for recovery */ + if (buf_ctrl->is_volatile) + buf_ctrl->old_val = + (value >> buf_ctrl->shft) & buf_ctrl->mask; + + /* write new value */ + value &= ~(buf_ctrl->mask << buf_ctrl->shft); + value |= + ((buf_ctrl->val & buf_ctrl->mask) + << buf_ctrl->shft); + MFC_CORE_WRITEL(value, buf_ctrl->addr); + } + + /* set change flag bit */ + if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) { + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value |= BIT(buf_ctrl->flag_shft); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + } + + buf_ctrl->has_new = 0; + buf_ctrl->updated = 1; + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG) + ctx->stored_tag = buf_ctrl->val; + + mfc_ctx_debug(6, + "[CTRLS] Set buffer control id: 0x%08x, val: %d (%#x)\n", + buf_ctrl->id, buf_ctrl->val, buf_ctrl->val); + } + + return 0; +} + +static int mfc_core_get_buf_ctrls(struct mfc_core *core, + struct mfc_ctx *ctx, struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + unsigned int value = 0; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_GET)) + continue; + + if (buf_ctrl->mode == MFC_CTRL_MODE_SFR) + value = MFC_CORE_READL(buf_ctrl->addr); + + value = (value >> buf_ctrl->shft) & buf_ctrl->mask; + + buf_ctrl->val = value; + buf_ctrl->has_new = 1; + + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_FRAME_ERROR_TYPE) + buf_ctrl->val = mfc_get_frame_error_type(ctx, value); + + mfc_ctx_debug(6, + "[CTRLS] Get buffer control id: 0x%08x, val: %d (%#x)\n", + buf_ctrl->id, buf_ctrl->val, buf_ctrl->val); + } + + return 0; +} + +static int mfc_core_recover_buf_ctrls(struct mfc_core *core, + struct mfc_ctx *ctx, + struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + unsigned int value = 0; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) || + !buf_ctrl->is_volatile || !buf_ctrl->updated) + continue; + + if (buf_ctrl->mode == MFC_CTRL_MODE_SFR) { + value = MFC_CORE_READL(buf_ctrl->addr); + value &= ~(buf_ctrl->mask << buf_ctrl->shft); + value |= + ((buf_ctrl->old_val & buf_ctrl->mask) + << buf_ctrl->shft); + MFC_CORE_WRITEL(value, buf_ctrl->addr); + } + + /* clear change flag bit */ + if (buf_ctrl->flag_mode == MFC_CTRL_MODE_SFR) { + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value &= ~BIT(buf_ctrl->flag_shft); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + } + + buf_ctrl->updated = 0; + mfc_ctx_debug(6, + "[CTRLS] Recover buffer control id: 0x%08x, old val: %d\n", + buf_ctrl->id, buf_ctrl->old_val); + } + + return 0; +} + +/* + * This function is used when you want to restore buffer ctrls. + * 1) NAL_Q stop: It is enqueued in the NAL_Q queue, + * but it must be restored because HW is not used. + * 2) DRC: The input buffer that caused the DRC was used for HW, but it must be reused. + */ +static int mfc_core_restore_buf_ctrls(struct mfc_ctx *ctx, + struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) || + !(buf_ctrl->updated)) + continue; + + buf_ctrl->has_new = 1; + buf_ctrl->updated = 0; + + mfc_ctx_debug(6, + "[CTRLS] Restore buffer control id: 0x%08x, val: %d\n", + buf_ctrl->id, buf_ctrl->val); + } + + return 0; +} + +struct mfc_bufs_ops mfc_bufs_ops = { + .core_set_buf_ctrls = mfc_core_set_buf_ctrls, + .core_get_buf_ctrls = mfc_core_get_buf_ctrls, + .core_recover_buf_ctrls = mfc_core_recover_buf_ctrls, + .core_restore_buf_ctrls = mfc_core_restore_buf_ctrls, +}; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c new file mode 100644 index 000000000000..8846230f1e20 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_ctx_ctrl.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "base/mfc_common.h" + +static struct mfc_ctrl_cfg mfc_dec_ctrl_list[] = { + { + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_PICTURE_TAG, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_RET_PICTURE_TAG_TOP, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_STATUS, + .mask = 0x7, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + /* CRC related definitions are based on non-H.264 type */ + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_FIRST_PLANE_CRC, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_SECOND_PLANE_CRC, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA1, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_THIRD_PLANE_CRC, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_LUMA, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_CHROMA, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_GENERATED, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_DISPLAY_STATUS, + .mask = 0x1, + .shft = 6, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_AVAIL, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_SEI_AVAIL, + .mask = 0x1, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRGMENT_ID, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_FRAME_PACK_ARRGMENT_ID, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_INFO, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_FRAME_PACK_SEI_INFO, + .mask = 0x3FFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_GRID_POS, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_FRAME_PACK_GRID_POS, + .mask = 0xFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_H264_MVC_VIEW_ID, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MVC_VIEW_ID, + .mask = 0xFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_PIC_AVERAGE_LIGHT, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI, + .mask = 0xFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_CONTENT_LIGHT, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI, + .mask = 0xFFFF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_DISPLAY_LUMINANCE, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_MIN_DISPLAY_LUMINANCE, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_MATRIX_COEFFICIENTS, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_FORMAT, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, + .mask = 0x7, + .shft = 26, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, + .mask = 0x1, + .shft = 25, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, + .mask = 0xFF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_TRANSFER_CHARACTERISTICS, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_WHITE_POINT, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_0, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_1, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_2, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_POC, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_D_RET_PICTURE_TIME_TOP, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_FRAME_ERROR_TYPE, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_ERROR_CODE, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* buffer additional information */ + .type = MFC_CTRL_TYPE_SRC, + .id = V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_NONE, + .flag_mode = MFC_CTRL_MODE_NONE, + }, + { /* buffer additional information */ + .type = MFC_CTRL_TYPE_DST, + .id = V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_NONE, + .flag_mode = MFC_CTRL_MODE_NONE, + } +}; + +#define NUM_DEC_CTRL_CFGS ARRAY_SIZE(mfc_dec_ctrl_list) + +static void mfc_ctrl_cleanup_ctx(struct mfc_ctx *ctx) +{ + struct mfc_ctx_ctrl *ctx_ctrl; + + while (!list_empty(&ctx->ctrls)) { + ctx_ctrl = list_entry((&ctx->ctrls)->next, + struct mfc_ctx_ctrl, list); + list_del(&ctx_ctrl->list); + kfree(ctx_ctrl); + } + + INIT_LIST_HEAD(&ctx->ctrls); +} + +static int __mfc_ctrl_init_ctx(struct mfc_ctx *ctx, struct mfc_ctrl_cfg *ctrl_list, int count) +{ + unsigned long i; + struct mfc_ctx_ctrl *ctx_ctrl; + + INIT_LIST_HEAD(&ctx->ctrls); + + for (i = 0; i < count; i++) { + ctx_ctrl = kzalloc(sizeof(*ctx_ctrl), GFP_KERNEL); + if (!ctx_ctrl) { + mfc_ctrl_cleanup_ctx(ctx); + + return -ENOMEM; + } + + ctx_ctrl->type = ctrl_list[i].type; + ctx_ctrl->id = ctrl_list[i].id; + ctx_ctrl->addr = ctrl_list[i].addr; + ctx_ctrl->set.has_new = 0; + ctx_ctrl->set.val = 0; + ctx_ctrl->get.has_new = 0; + ctx_ctrl->get.val = 0; + + list_add_tail(&ctx_ctrl->list, &ctx->ctrls); + } + + return 0; +} + +static int mfc_ctrl_init_ctx(struct mfc_ctx *ctx) +{ + if (ctx->type == MFCINST_DECODER) + return __mfc_ctrl_init_ctx(ctx, mfc_dec_ctrl_list, NUM_DEC_CTRL_CFGS); + + mfc_ctx_err("[CTRLS] invalid type %d\n", ctx->type); + return -EINVAL; +} + +static void mfc_ctrl_reset_buf(struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + + list_for_each_entry(buf_ctrl, head, list) { + buf_ctrl->has_new = 0; + buf_ctrl->val = 0; + buf_ctrl->old_val = 0; + buf_ctrl->updated = 0; + } +} + +static void __mfc_ctrl_cleanup_buf(struct list_head *head) +{ + struct mfc_buf_ctrl *buf_ctrl; + + while (!list_empty(head)) { + buf_ctrl = list_entry(head->next, + struct mfc_buf_ctrl, list); + list_del(&buf_ctrl->list); + kfree(buf_ctrl); + } + + INIT_LIST_HEAD(head); +} + +static int mfc_ctrl_cleanup_buf(struct mfc_ctx *ctx, enum mfc_ctrl_type type, unsigned int index) +{ + struct list_head *head; + + if (index >= MFC_MAX_BUFFERS) { + mfc_ctx_err("Per-buffer control index is out of range\n"); + return -EINVAL; + } + + if (type & MFC_CTRL_TYPE_SRC) { + if (!(test_and_clear_bit(index, ctx->src_ctrls_avail))) + return 0; + + head = &ctx->src_ctrls[index]; + } else if (type & MFC_CTRL_TYPE_DST) { + if (!(test_and_clear_bit(index, ctx->dst_ctrls_avail))) + return 0; + + head = &ctx->dst_ctrls[index]; + } else { + mfc_ctx_err("Control type mismatch. type : %d\n", type); + return -EINVAL; + } + + __mfc_ctrl_cleanup_buf(head); + + return 0; +} + +static int __mfc_ctrl_init_buf(struct mfc_ctx *ctx, struct mfc_ctrl_cfg *ctrl_list, + enum mfc_ctrl_type type, unsigned int index, int count) +{ + unsigned long i; + struct mfc_buf_ctrl *buf_ctrl; + struct list_head *head; + + if (index >= MFC_MAX_BUFFERS) { + mfc_ctx_err("Per-buffer control index is out of range\n"); + return -EINVAL; + } + + if (type & MFC_CTRL_TYPE_SRC) { + if (test_bit(index, ctx->src_ctrls_avail)) { + mfc_ctrl_reset_buf(&ctx->src_ctrls[index]); + + return 0; + } + + head = &ctx->src_ctrls[index]; + } else if (type & MFC_CTRL_TYPE_DST) { + if (test_bit(index, ctx->dst_ctrls_avail)) { + mfc_ctrl_reset_buf(&ctx->dst_ctrls[index]); + + return 0; + } + + head = &ctx->dst_ctrls[index]; + } else { + mfc_ctx_err("Control type mismatch. type : %d\n", type); + return -EINVAL; + } + + INIT_LIST_HEAD(head); + + for (i = 0; i < count; i++) { + if (!(type & ctrl_list[i].type)) + continue; + + buf_ctrl = kzalloc(sizeof(*buf_ctrl), GFP_KERNEL); + if (!buf_ctrl) { + __mfc_ctrl_cleanup_buf(head); + + return -ENOMEM; + } + + buf_ctrl->type = ctrl_list[i].type; + buf_ctrl->id = ctrl_list[i].id; + buf_ctrl->is_volatile = ctrl_list[i].is_volatile; + buf_ctrl->mode = ctrl_list[i].mode; + buf_ctrl->addr = ctrl_list[i].addr; + buf_ctrl->mask = ctrl_list[i].mask; + buf_ctrl->shft = ctrl_list[i].shft; + buf_ctrl->flag_mode = ctrl_list[i].flag_mode; + buf_ctrl->flag_addr = ctrl_list[i].flag_addr; + buf_ctrl->flag_shft = ctrl_list[i].flag_shft; + + list_add_tail(&buf_ctrl->list, head); + } + + mfc_ctrl_reset_buf(head); + + if (type & MFC_CTRL_TYPE_SRC) + set_bit(index, ctx->src_ctrls_avail); + else + set_bit(index, ctx->dst_ctrls_avail); + + return 0; +} + +static int mfc_ctrl_init_buf(struct mfc_ctx *ctx, enum mfc_ctrl_type type, unsigned int index) +{ + if (ctx->type == MFCINST_DECODER) + return __mfc_ctrl_init_buf(ctx, mfc_dec_ctrl_list, type, index, NUM_DEC_CTRL_CFGS); + + mfc_ctx_err("[CTRLS] invalid type %d\n", ctx->type); + return -EINVAL; +} + +static void mfc_ctrl_to_buf(struct mfc_ctx *ctx, struct list_head *head) +{ + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; + + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_SET) || + !ctx_ctrl->set.has_new) + continue; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET)) + continue; + + if (buf_ctrl->id == ctx_ctrl->id) { + buf_ctrl->has_new = 1; + buf_ctrl->val = ctx_ctrl->set.val; + + if (buf_ctrl->is_volatile) + buf_ctrl->updated = 0; + + ctx_ctrl->set.has_new = 0; + + break; + } + } + } +} + +static void mfc_ctrl_to_ctx(struct mfc_ctx *ctx, struct list_head *head) +{ + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; + + list_for_each_entry(buf_ctrl, head, list) { + if (!(buf_ctrl->type & MFC_CTRL_TYPE_GET) || !buf_ctrl->has_new) + continue; + + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_GET)) + continue; + + if (ctx_ctrl->id == buf_ctrl->id) { + if (ctx_ctrl->get.has_new) + mfc_ctx_debug(8, "Overwrite ctx_ctrl value id: %#x, val: %d\n", + ctx_ctrl->id, ctx_ctrl->get.val); + + ctx_ctrl->get.has_new = 1; + ctx_ctrl->get.val = buf_ctrl->val; + + buf_ctrl->has_new = 0; + } + } + } +} + +static int mfc_ctrl_get_buf_val(struct mfc_ctx *ctx, struct list_head *head, unsigned int id) +{ + struct mfc_buf_ctrl *buf_ctrl; + int value = 0; + + list_for_each_entry(buf_ctrl, head, list) { + if (buf_ctrl->id == id) { + value = buf_ctrl->val; + mfc_ctx_debug(6, "[CTRLS] Get buffer control id: 0x%08x, val: %d (%#x)\n", + buf_ctrl->id, value, value); + break; + } + } + + return value; +} + +static void mfc_ctrl_update_buf_val(struct mfc_ctx *ctx, struct list_head *head, + unsigned int id, int value) +{ + struct mfc_buf_ctrl *buf_ctrl; + + list_for_each_entry(buf_ctrl, head, list) { + if (buf_ctrl->id == id) { + buf_ctrl->val = value; + mfc_ctx_debug(6, "[CTRLS] Update buffer control id: 0x%08x, val: %d (%#x)\n", + buf_ctrl->id, buf_ctrl->val, buf_ctrl->val); + break; + } + } +} + +struct mfc_ctrls_ops mfc_ctrls_ops = { + .cleanup_ctx_ctrls = mfc_ctrl_cleanup_ctx, + .init_ctx_ctrls = mfc_ctrl_init_ctx, + .reset_buf_ctrls = mfc_ctrl_reset_buf, + .cleanup_buf_ctrls = mfc_ctrl_cleanup_buf, + .init_buf_ctrls = mfc_ctrl_init_buf, + .to_buf_ctrls = mfc_ctrl_to_buf, + .to_ctx_ctrls = mfc_ctrl_to_ctx, + .get_buf_ctrl_val = mfc_ctrl_get_buf_val, + .update_buf_val = mfc_ctrl_update_buf_val, +}; -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035623epcas5p3447703a70d34c96a719a3e92d0ff6d39@epcas5p3.samsung.com>]
* [PATCH 15/29] media: mfc: Add decoder resource‑management (RM) support and load‑balancing [not found] ` <CGME20250930035623epcas5p3447703a70d34c96a719a3e92d0ff6d39@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Introduce dynamic load‑balancing and core‑selection for MFC decoder. - Add complete RM infrastructure: real‑time QoS, multi‑core handling, core migration. - Implement per‑core load tracking and weighted‑MB calculation. - Refactor driver paths (open/close/setup/stop, buffer movement, Butler requests) to use the RM layer and improve error handling/cleanup. - Enables dual‑core utilization, real‑time priority support, and prepares the driver for upstream/mainline integration. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/mfc_rm.c | 2590 ++++++++++++++++- .../platform/samsung/exynos-mfc/mfc_rm.h | 52 + 2 files changed, 2568 insertions(+), 74 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c index a25a05642cf2..0a805464fbc9 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c @@ -16,127 +16,2569 @@ #include "mfc_core_hw_reg_api.h" #include "mfc_core_pm.h" +#include "base/mfc_qos.h" #include "base/mfc_buf.h" +#include "base/mfc_queue.h" #include "base/mfc_utils.h" #include "base/mfc_mem.h" +static void __mfc_rm_request_butler(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int i; + + if (ctx) { + /* main core first if it is working */ + for (i = 0; i < MFC_CORE_TYPE_NUM; i++) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + break; + + core = dev->core[ctx->op_core_num[i]]; + if (!core) { + mfc_ctx_err("[RM] There is no core[%d]\n", + ctx->op_core_num[i]); + return; + } + + core_ctx = core->core_ctx[ctx->num]; + if (core->sched->enqueue_work(core, core_ctx)) + core->core_ops->request_work(core, + MFC_WORK_BUTLER, ctx); + } + } else { + /* all of alive core */ + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + mfc_dev_debug(2, "[RM] There is no core[%d]\n", i); + continue; + } + + core->core_ops->request_work(core, MFC_WORK_BUTLER, NULL); + } + } +} + +static void __mfc_rm_update_core_load(struct mfc_ctx *ctx, int move_core, int multi_mode) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + int i; + + /* + * @move_core + * 0: no move of core. + * 1: update the load to the moving core, because have to move the main core. + */ + if (move_core) + core = dev->core[ctx->move_core_num[MFC_CORE_MAIN]]; + else + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + return; + } + + /* + * @multi_core + * 0: no multi core mode (single core). + * 1: update the load separately, because it works in multi core mode. + */ + if (mfc_rm_query_state(ctx, EQUAL_BIGGER, MFCINST_INIT)) { + if (multi_mode) { + for (i = 0; i < dev->num_core; i++) + dev->core[i]->total_mb += (ctx->weighted_mb / dev->num_core); + } else { + core->total_mb += ctx->weighted_mb; + } + } + + mfc_ctx_debug(3, "[RMLB] load(%lu) balanced to %s core-%d (total load: [0] %lu, [1] %lu)\n", + ctx->weighted_mb, + multi_mode ? "multi" : "single", core->id, + dev->core[0]->total_mb, dev->core[1]->total_mb); + MFC_TRACE_RM("[c:%d] load(%lu) balanced to %s core-%d (total load: [0] %lu, [1] %lu)\n", + ctx->num, ctx->weighted_mb, + multi_mode ? "multi" : "single", core->id, + dev->core[0]->total_mb, dev->core[1]->total_mb); +} + +static int __mfc_rm_get_core_num_by_load(struct mfc_dev *dev, struct mfc_ctx *ctx, + int default_core) +{ + struct mfc_core *core; + int total_load[MFC_NUM_CORE]; + int core_num, surplus_core; + int curr_load; + + if (default_core == MFC_DEC_DEFAULT_CORE) + surplus_core = MFC_SURPLUS_CORE; + else + surplus_core = MFC_DEC_DEFAULT_CORE; + mfc_ctx_debug(2, "[RMLB] default core-%d, surplus core-%d\n", + default_core, surplus_core); + + if (!dev->core[default_core]->total_mb && !dev->core[surplus_core]->total_mb) { + mfc_ctx_debug(2, "[RMLB] there is no instance, use the default core\n"); + return default_core; + } + + core = dev->core[default_core]; + total_load[default_core] = core->total_mb * 100 / core->core_pdata->max_mb; + core = dev->core[surplus_core]; + total_load[surplus_core] = core->total_mb * 100 / core->core_pdata->max_mb; + + curr_load = ctx->weighted_mb * 100 / core->core_pdata->max_mb; + mfc_ctx_debug(2, "[RMLB] load%s fixed (curr mb: %ld, load: %d%%)\n", + ctx->src_ts.ts_is_full ? " " : " not", ctx->weighted_mb, curr_load); + + if (dev->debugfs.core_balance) + dev->core_balance = dev->debugfs.core_balance; + else + dev->core_balance = dev->pdata->core_balance; + + /* 1) Default core: Default core has not yet been balanced */ + if ((total_load[default_core] + curr_load) <= dev->core_balance) { + core_num = default_core; + goto fix_core; + /* 2) Surplus core: Default core has been balanced already */ + } else if ((total_load[default_core] > dev->core_balance) && + (total_load[surplus_core] < dev->core_balance)) { + core_num = surplus_core; + goto fix_core; + } + + /* 3) Core with lower load */ + if (total_load[default_core] > total_load[surplus_core]) + core_num = surplus_core; + else + core_num = default_core; + +fix_core: + mfc_ctx_debug(2, "[RMLB] total load: [0] %ld(%d%%), [1] %ld(%d%%), curr_load: %ld(%d%%), select core: %d\n", + dev->core[0]->total_mb, total_load[0], + dev->core[1]->total_mb, total_load[1], + ctx->weighted_mb, curr_load, core_num); + MFC_TRACE_RM("[c:%d] load [0] %ld(%d) [1] %ld(%d) curr %ld(%d) select %d\n", + ctx->num, + dev->core[0]->total_mb, total_load[0], + dev->core[1]->total_mb, total_load[1], + ctx->weighted_mb, curr_load, core_num); + + return core_num; +} + +static int __mfc_rm_get_core_num(struct mfc_ctx *ctx, int curr_core_num) +{ + struct mfc_dev *dev = ctx->dev; + int core_num; + + /* Default core according to standard */ + core_num = ctx->op_core_type; + + if (dev->debugfs.core_balance) + dev->pdata->core_balance = dev->debugfs.core_balance; + + if (dev->pdata->core_balance == 100) { + mfc_ctx_debug(4, "[RMLB] do not want to load balancing\n"); + if (ctx->op_core_type == MFC_OP_CORE_ALL) + core_num = curr_core_num; + return core_num; + } + + /* Change core according to load */ + if (ctx->op_core_type == MFC_OP_CORE_ALL) + core_num = __mfc_rm_get_core_num_by_load(dev, ctx, MFC_DEC_DEFAULT_CORE); + + return core_num; +} + +static int __mfc_rm_move_core_open(struct mfc_ctx *ctx, int to_core_num, int from_core_num) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *to_core = dev->core[to_core_num]; + struct mfc_core *from_core = dev->core[from_core_num]; + int ret = 0; + + mfc_ctx_info("[RMLB] open core changed MFC%d -> MFC%d\n", + from_core_num, to_core_num); + MFC_TRACE_RM("[c:%d] open core changed MFC%d -> MFC%d\n", + ctx->num, from_core_num, to_core_num); + + ret = from_core->core_ops->instance_deinit(from_core, ctx); + if (ret) { + mfc_ctx_err("[RMLB] Failed to deinit\n"); + return ret; + } + + if (from_core->sched->is_work(from_core)) + from_core->sched->queue_work(from_core); + + ctx->op_core_num[MFC_CORE_MAIN] = to_core_num; + + ret = to_core->core_ops->instance_init(to_core, ctx); + if (ret) { + ctx->op_core_num[MFC_CORE_MAIN] = MFC_CORE_INVALID; + mfc_ctx_err("[RMLB] Failed to init\n"); + return ret; + } + + return ret; +} + +static int __mfc_rm_move_core_running(struct mfc_ctx *ctx, int to_core_num, int from_core_num) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *to_core; + struct mfc_core *from_core; + struct mfc_core *maincore; + struct mfc_core *subcore; + struct mfc_core_ctx *core_ctx; + int is_to_core = 0; + int ret = 0; + + ret = mfc_get_corelock_migrate(ctx); + if (ret < 0) { + mfc_ctx_err("[RMLB] failed to get corelock\n"); + return -EAGAIN; + } + + to_core = dev->core[to_core_num]; + from_core = dev->core[from_core_num]; + maincore = dev->core[MFC_CORE_MAIN]; + subcore = dev->core[MFC_CORE_SUB]; + if (!to_core || !from_core || !maincore || !subcore) { + mfc_ctx_err("The core is invalid(to: %p, from: %p, main: %p, sub: %p)\n", + to_core, from_core, maincore, subcore); + mfc_release_corelock_migrate(ctx); + return -EINVAL; + } + + core_ctx = from_core->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_err("there is no core_ctx\n"); + mfc_release_corelock_migrate(ctx); + return -EINVAL; + } + + /* 1. Change state on from_core */ + ret = mfc_core_get_hwlock_dev(maincore); + if (ret < 0) { + mfc_ctx_err("Failed to get hwlock of maincore\n"); + mfc_release_corelock_migrate(ctx); + return ret; + } + + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_err("Failed to get hwlock of subcore\n"); + goto err_state; + } + is_to_core = 1; + + if (core_ctx->state != MFCINST_RUNNING) { + mfc_debug(3, "[RMLB] it is not running state: %d\n", core_ctx->state); + goto err_state; + } + + if (IS_MULTI_MODE(ctx)) { + mfc_err("[RMLB] multi core mode couldn't migration, need to switch to single\n"); + goto err_state; + } + + mfc_change_state(core_ctx, MFCINST_MOVE_INST); + + /* 2. Cache flush on to_core */ + + if (from_core->sleep || to_core->sleep) { + mfc_err("Failed to move inst. Sleep was called\n"); + ret = -EAGAIN; + goto err_migrate; + } + + ret = to_core->core_ops->instance_move_to(to_core, ctx); + if (ret) { + mfc_err("Failed to instance move init\n"); + goto err_migrate; + } + + kfree(to_core->core_ctx[ctx->num]); + ctx->op_core_num[MFC_CORE_MAIN] = MFC_CORE_INVALID; + + /* 3. Enable the clock of to_core because from_core accesses to_core */ + mfc_core_pm_clock_on(to_core, 0); + + /* 4. Set F/W and ctx address on MFC1 */ + mfc_core_set_migration_addr(dev->core[1], ctx, dev->core[0]->fw_buf.daddr, + dev->core[0]->common_ctx_buf.daddr); + + /* 5. Move and close instance on from_core */ + ret = from_core->core_ops->instance_move_from(from_core, ctx); + if (ret) { + mfc_err("Failed to instance move\n"); + MFC_TRACE_RM("[c:%d] instance_move_from fail\n", ctx->num); + goto err_move; + } + mfc_debug(3, "[RMLB] move and close instance on from_core-%d\n", from_core->id); + MFC_TRACE_RM("[c:%d] move and close inst_no %d\n", ctx->num, core_ctx->inst_no); + + /* 6. Clean up */ + ctx->op_core_num[MFC_CORE_MAIN] = to_core->id; + to_core->core_ctx[ctx->num] = core_ctx; + core_ctx->core = to_core; + + from_core->sched->clear_work(from_core, core_ctx); + from_core->core_ctx[core_ctx->num] = 0; + mfc_core_pm_clock_off(to_core, 0); + + mfc_core_release_hwlock_dev(subcore); + mfc_core_release_hwlock_dev(maincore); + + mfc_change_state(core_ctx, MFCINST_RUNNING); + mfc_qos_on(to_core, ctx); + + mfc_release_corelock_migrate(ctx); + + mfc_debug(2, "[RMLB] ctx[%d] migration finished. op_core:%d\n", ctx->num, to_core->id); + + __mfc_rm_request_butler(dev, ctx); + + return 0; + +err_move: + mfc_core_pm_clock_off(to_core, 0); +err_migrate: + mfc_change_state(core_ctx, MFCINST_RUNNING); +err_state: + if (is_to_core) + mfc_core_release_hwlock_dev(subcore); + mfc_core_release_hwlock_dev(maincore); + + mfc_release_corelock_migrate(ctx); + + return ret; +} + +static struct mfc_core *__mfc_rm_switch_to_single_mode(struct mfc_ctx *ctx, int need_lock, + enum mfc_op_core_type op_core_type) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *maincore; + struct mfc_core *subcore; + struct mfc_core_ctx *core_ctx; + struct mfc_buf *src_mb = NULL; + int last_op_core, switch_single_core; + int ret; + + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + return NULL; + } + + core_ctx = maincore->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_err("[RM] There is no main core_ctx\n"); + return NULL; + } + + subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!subcore) { + mfc_info("[RM] There is no sub core for switch single, use main core\n"); + return maincore; + } + + core_ctx = subcore->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_info("[RM] There is no sub core_ctx for switch single, use main core\n"); + return maincore; + } + + ret = mfc_core_get_hwlock_dev(maincore); + if (ret < 0) { + mfc_err("Failed to get main core hwlock\n"); + return NULL; + } + + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_err("Failed to get sub core hwlock\n"); + mfc_core_release_hwlock_dev(maincore); + return NULL; + } + + if (need_lock) + mutex_lock(&ctx->op_mode_mutex); + + if (IS_SWITCH_SINGLE_MODE(ctx) || IS_SINGLE_MODE(ctx)) { + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + + /* + * This(Here) means that it has already been switched to single mode + * while waiting for op_mode_mutex. + * Select a new maincore because the maincore may have been different + * from the maincore before waiting. + */ + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) + mfc_err("[RM] There is no main core\n"); + if (need_lock) + mutex_unlock(&ctx->op_mode_mutex); + return maincore; + } + + mfc_change_op_mode(ctx, MFC_OP_SWITCHING); + + /* need to cleanup src buffer */ + mfc_return_buf_to_ready_queue(ctx, &maincore->core_ctx[ctx->num]->src_buf_queue, + &subcore->core_ctx[ctx->num]->src_buf_queue); + mfc_debug(2, "[RM] op_mode %d change to switch to single\n", ctx->stream_op_mode); + MFC_TRACE_RM("[c:%d] op_mode %d->4: Move src all\n", ctx->num, ctx->stream_op_mode); + + core_ctx = maincore->core_ctx[ctx->num]; + if (core_ctx->state == MFCINST_FINISHING) { + mfc_change_state(core_ctx, MFCINST_RUNNING); + } else if (core_ctx->state == MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET) { + mfc_change_state(core_ctx, MFCINST_RUNNING); + + core_ctx = subcore->core_ctx[ctx->num]; + mfc_change_state(core_ctx, MFCINST_RUNNING); + } + + /* + * Select switch to single core number + * If the op_core_type of the instance that caused switch_to_single + * is only MFC_OP_CORE_FIXED_(N), select the other core. + * Otherwise, select a lower load core. + */ + if (ctx->op_core_type == MFC_OP_CORE_FIXED_0) + switch_single_core = 0; + else if (ctx->op_core_type == MFC_OP_CORE_FIXED_1) + switch_single_core = 1; + else if (op_core_type == MFC_OP_CORE_FIXED_1) + switch_single_core = 0; + else if (op_core_type == MFC_OP_CORE_FIXED_0) + switch_single_core = 1; + else if (ctx->cmd_counter == 0) + switch_single_core = ctx->last_op_core; + else if ((ctx->stream_op_mode == MFC_OP_TWO_MODE2) && + (ctx->curr_src_index != -1)) + switch_single_core = ctx->curr_src_index % ctx->dev->num_core; + else + switch_single_core = __mfc_rm_get_core_num_by_load(dev, ctx, MFC_SURPLUS_CORE); + mfc_debug(2, "[RM] switch to single to core: %d\n", switch_single_core); + MFC_TRACE_RM("[c:%d] switch to single to core: %d\n", ctx->num, switch_single_core); + + mfc_rm_set_core_num(ctx, switch_single_core); + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) { + mfc_err("[RM] There is no main core\n"); + if (need_lock) + mutex_unlock(&ctx->op_mode_mutex); + return NULL; + } + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) { + mfc_err("[RM] There is no sub core\n"); + if (need_lock) + mutex_unlock(&ctx->op_mode_mutex); + return NULL; + } + + /* main core should have one src buffer */ + core_ctx = maincore->core_ctx[ctx->num]; + if (mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue) == 0) { + src_mb = mfc_get_move_buf(ctx, &core_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, + MFC_BUF_NO_TOUCH_USED, MFC_QUEUE_ADD_BOTTOM); + if (src_mb) { + mfc_debug(2, "[RM][BUFINFO] MFC-%d uses src index: %d(%d)\n", + maincore->id, src_mb->vb.vb2_buf.index, + src_mb->src_index); + MFC_TRACE_RM("[c:%d] MFC-%d uses src index: %d(%d)\n", + ctx->num, maincore->id, src_mb->vb.vb2_buf.index, + src_mb->src_index); + } + } else { + mfc_debug(2, "[RM][BUFINFO] MFC-%d has src buffer already\n", maincore->id); + } + + mfc_change_op_mode(ctx, MFC_OP_SWITCH_TO_SINGLE); + if (ctx->stream_op_mode == MFC_OP_TWO_MODE2 && (ctx->curr_src_index != -1)) { + last_op_core = ctx->curr_src_index % ctx->dev->num_core; + if (last_op_core != switch_single_core) { + mfc_debug(2, "[RM] last op core-%d but switch core-%d, should operate once with mode2\n", + last_op_core, switch_single_core); + mfc_change_op_mode(ctx, MFC_OP_SWITCH_BUT_MODE2); + } + } + + /* for check whether command is sent during switch to single */ + ctx->cmd_counter = 0; + + if (need_lock) + mutex_unlock(&ctx->op_mode_mutex); + + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + mfc_qos_off(subcore, ctx); + mfc_qos_on(maincore, ctx); + + mfc_debug(2, "[RM] switch single mode run with core%d\n", maincore->id); + + return maincore; +} + +static int __mfc_rm_check_multi_core_mode(struct mfc_dev *dev, enum mfc_op_core_type op_core_type) +{ + struct mfc_core *core = NULL; + struct mfc_core_ctx *core_ctx = NULL; + struct mfc_ctx *ctx = NULL; + int i; + + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (test_bit(i, &dev->multi_core_inst_bits)) { + MFC_TRACE_RM("[c:%d] multi core instance\n", i); + ctx = dev->ctx[i]; + if (!ctx) { + mfc_dev_err("[RM] There is no ctx\n"); + continue; + } + + if (!IS_MULTI_MODE(ctx)) { + mfc_ctx_debug(3, "[RM] already switched to single\n"); + continue; + } + + if (!mfc_rm_query_state(ctx, EQUAL, MFCINST_RUNNING) && + !mfc_rm_query_state(ctx, EQUAL, + MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET)) { + mfc_ctx_debug(2, "[RM] op_mode%d but setup of 2core is not yet done\n", + ctx->op_mode); + continue; + } + + /* multi mode instance should be switch to single mode */ + core = __mfc_rm_switch_to_single_mode(ctx, 1, op_core_type); + if (!core) + return -EINVAL; + + mfc_ctx_debug(2, "[RM][2CORE] switch single for multi instance op_mode: %d\n", + ctx->op_mode); + MFC_TRACE_RM("[c:%d] switch to single for multi inst\n", i); + + core_ctx = core->core_ctx[ctx->num]; + if (core->sched->enqueue_work(core, core_ctx)) + core->core_ops->request_work(core, MFC_WORK_BUTLER, ctx); + } + } + + return 0; +} + +static void __mfc_rm_move_buf_ready_set_bit(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core = NULL; + struct mfc_core_ctx *core_ctx = NULL; + struct mfc_buf *src_mb = NULL; + unsigned int num; + + mutex_lock(&ctx->op_mode_mutex); + + /* search for next running core */ + src_mb = mfc_get_buf(ctx, &ctx->src_buf_ready_queue, + MFC_BUF_NO_TOUCH_USED); + if (!src_mb) { + mfc_ctx_debug(3, "[RM][2CORE] there is no src buffer\n"); + mutex_unlock(&ctx->op_mode_mutex); + return; + } + + /* handle last frame with switch_to_single mode */ + if (mfc_check_mb_flag(src_mb, MFC_FLAG_LAST_FRAME)) { + ctx->serial_src_index = 0; + mfc_ctx_debug(2, "[RM][2CORE] EOS, reset serial src index\n"); + MFC_TRACE_RM("[c:%d] EOS: Reset serial src index\n", ctx->num); + + if (ctx->curr_src_index < src_mb->src_index - 1) { + mfc_ctx_debug(2, "[RM][2CORE] waiting src index %d, curr src index %d is working\n", + src_mb->src_index, + ctx->curr_src_index); + goto butler; + } + + core = __mfc_rm_switch_to_single_mode(ctx, 0, ctx->op_core_type); + if (!core) { + mutex_unlock(&ctx->op_mode_mutex); + return; + } + mfc_ctx_debug(2, "[RM][2CORE] switch single for LAST FRAME(EOS) op_mode: %d\n", + ctx->op_mode); + goto butler; + } + + if (ctx->curr_src_index == src_mb->src_index - 1) { + num = src_mb->src_index % dev->num_core; + core = dev->core[num]; + mfc_ctx_debug(2, "[RM][2CORE] src index %d(%d) run in MFC-%d, curr: %d\n", + src_mb->vb.vb2_buf.index, + src_mb->src_index, num, + ctx->curr_src_index); + } else { + mfc_ctx_debug(2, "[RM][2CORE] waiting src index %d, curr src index %d is working\n", + src_mb->src_index, + ctx->curr_src_index); + goto butler; + } + + /* move src buffer to src_buf_queue from src_buf_ready_queue */ + core_ctx = core->core_ctx[ctx->num]; + src_mb = mfc_get_move_buf(ctx, &core_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, + MFC_BUF_NO_TOUCH_USED, MFC_QUEUE_ADD_BOTTOM); + if (src_mb) { + mfc_debug(2, "[RM][BUFINFO] MFC-%d uses src index: %d(%d)\n", + core->id, src_mb->vb.vb2_buf.index, + src_mb->src_index); + MFC_TRACE_RM("[c:%d] READY: Move src[%d] to MFC-%d\n", + ctx->num, src_mb->src_index, core->id); + } + +butler: + mutex_unlock(&ctx->op_mode_mutex); + __mfc_rm_request_butler(dev, ctx); +} + +static void __mfc_rm_migrate_all_to_one_core(struct mfc_dev *dev) +{ + int i, ret, total_load[MFC_NUM_CORE]; + struct mfc_ctx *tmp_ctx, *ctx; + unsigned long flags; + int core_num, to_core_num, from_core_num; + int op_core_fixed0 = 0, op_core_fixed1 = 0; + int op_core0 = 0, op_core1 = 0; + + if (dev->move_ctx_cnt) { + mfc_dev_debug(4, "[RMLB] instance migration working yet, move_ctx: %d\n", + dev->move_ctx_cnt); + return; + } + + spin_lock_irqsave(&dev->ctx_list_lock, flags); + + if (list_empty(&dev->ctx_list)) { + mfc_dev_debug(2, "[RMLB] there is no ctx for load balancing\n"); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } + + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) { + if (!IS_SINGLE_MODE(tmp_ctx)) { + mfc_dev_info("[RMLB] there is multi core ctx:%d, op_mode :%d\n", + tmp_ctx->num, tmp_ctx->op_mode); + MFC_TRACE_RM("there is multi core ctx:%d, op_mode :%d\n", + tmp_ctx->num, tmp_ctx->op_mode); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } + + if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_0) + op_core_fixed0++; + else if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_1) + op_core_fixed1++; + + /* op main core */ + if (tmp_ctx->op_core_num[MFC_CORE_MAIN] == MFC_DEC_DEFAULT_CORE) + op_core0++; + else if (tmp_ctx->op_core_num[MFC_CORE_MAIN] == MFC_SURPLUS_CORE) + op_core1++; + mfc_dev_debug(3, "[RMLB] ctx[%d] op_core_type: %d (fixed0: %d, fixed1: %d)\n", + tmp_ctx->num, tmp_ctx->op_core_type, + op_core_fixed0, op_core_fixed1); + } + + if (op_core_fixed0 && op_core_fixed1) { + mfc_dev_info("[RMLB] all instance should be work with fixed core\n"); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } else if ((!op_core_fixed0 && !op_core_fixed1) && + ((op_core0 && !op_core1) || (!op_core0 && op_core1))) { + mfc_dev_debug(3, "[RMLB] all instance already worked in one core\n"); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } else if (op_core_fixed0 && !op_core_fixed1) { + core_num = MFC_OP_CORE_FIXED_0; + } else { + core_num = MFC_OP_CORE_FIXED_1; + } + + for (i = 0; i < dev->num_core; i++) { + total_load[i] = dev->core[i]->total_mb * 100 / dev->core[i]->core_pdata->max_mb; + mfc_dev_debug(3, "[RMLB] core-%d total load: %d%% (mb: %lu)\n", + i, total_load[i], dev->core[i]->total_mb); + dev->core[i]->total_mb = 0; + } + + mfc_dev_info("[RMLB] load balance all to core-%d for multi core mode instance\n", + core_num); + MFC_TRACE_RM("load balance all to core-%d\n", core_num); + dev->move_ctx_cnt = 0; + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) { + if (tmp_ctx->op_core_num[MFC_CORE_MAIN] != core_num) { + mfc_dev_debug(3, "[RMLB] ctx[%d] move to core-%d\n", + tmp_ctx->num, core_num); + MFC_TRACE_RM("[c:%d] move to core-%d (mb: %lu)\n", + tmp_ctx->num, core_num, tmp_ctx->weighted_mb); + tmp_ctx->move_core_num[MFC_CORE_MAIN] = core_num; + dev->move_ctx[dev->move_ctx_cnt++] = tmp_ctx; + __mfc_rm_update_core_load(tmp_ctx, 1, 0); + } else { + mfc_dev_debug(3, "[RMLB] ctx[%d] keep core%d (mb: %lu)\n", + tmp_ctx->num, core_num, tmp_ctx->weighted_mb); + __mfc_rm_update_core_load(tmp_ctx, 0, 0); + } + } + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + + /* + * For sequential work, migration is performed directly without queue_work. + * This is because switch_to_single() should get the hwlock + * after migration_to_one_core(). + */ + for (i = 0; i < dev->move_ctx_cnt; i++) { + mutex_lock(&dev->mfc_migrate_mutex); + ctx = dev->move_ctx[i]; + dev->move_ctx[i] = NULL; + + from_core_num = ctx->op_core_num[MFC_CORE_MAIN]; + to_core_num = ctx->move_core_num[MFC_CORE_MAIN]; + mfc_ctx_debug(2, "[RMLB] ctx[%d] will be moved MFC%d -> MFC%d\n", + ctx->num, from_core_num, to_core_num); + MFC_TRACE_RM("[c:%d] will be moved MFC%d -> MFC%d\n", + ctx->num, from_core_num, to_core_num); + ret = __mfc_rm_move_core_running(ctx, to_core_num, from_core_num); + if (ret) { + mfc_ctx_info("[RMLB] migration stopped by ctx[%d]\n", + ctx->num); + MFC_TRACE_RM("migration fail by ctx[%d]\n", ctx->num); + } + mutex_unlock(&dev->mfc_migrate_mutex); + } + + mfc_dev_debug(2, "[RMLB] all instance migration finished\n"); + dev->move_ctx_cnt = 0; +} + +static void __mfc_rm_guarantee_init_buf(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *maincore; + struct mfc_core *subcore; + struct mfc_core_ctx *core_ctx; + int ret; + bool need_call_init_buf_main = true; + bool need_call_init_buf_sub = true; + + /* Check only ready, do not set bit to work_bits */ + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + mfc_ctx_debug(3, "[RM] ctx is not ready for INIT_BUF\n"); + return; + } + + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + return; + } + + subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core for switch single\n"); + return; + } + + /* + * No other command should be sent + * while sending INIT_BUFFER command to 2 core in mode2 + */ + ret = mfc_core_get_hwlock_dev(maincore); + if (ret < 0) { + mfc_ctx_err("Failed to get main core hwlock\n"); + return; + } + + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_ctx_err("Failed to get sub core hwlock\n"); + mfc_core_release_hwlock_dev(maincore); + return; + } + + /* main core ready set bit*/ + core_ctx = maincore->core_ctx[ctx->num]; + if (!maincore->sched->enqueue_work(maincore, core_ctx)) { + if (core_ctx->state == MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET) { + mfc_ctx_debug(3, "init_buf was done between calling this func and here\n"); + need_call_init_buf_main = false; + } else { + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + return; + } + } + + /* sub core ready set bit*/ + core_ctx = subcore->core_ctx[ctx->num]; + if (IS_TWO_MODE2(ctx)) { + if (!subcore->sched->enqueue_work(subcore, core_ctx)) { + if (core_ctx->state == MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET) { + need_call_init_buf_sub = false; + } else { + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + return; + } + } + } + + /* + * In order not to perform MFC_OFF register control(HWACG) when multi core mode, + * synchronize MFC_OFF register to zero. + */ + mfc_core_mfc_on(maincore); + mfc_core_mfc_on(subcore); + + /* multi_core_inst_bits is set after completing SEQ_START on both cores */ + set_bit(ctx->num, &dev->multi_core_inst_bits); + + MFC_TRACE_RM("[c:%d] op_mode %d try INIT_BUFFER\n", ctx->num, ctx->op_mode); + mfc_debug(3, "[RM] op_mode %d try INIT_BUFFER\n", ctx->op_mode); + if (need_call_init_buf_main) { + ret = maincore->core_ops->instance_init_buf(maincore, ctx); + if (ret < 0) { + mfc_err("failed main core init buffer\n"); + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + return; + } + } + + if (IS_TWO_MODE2(ctx) && need_call_init_buf_sub) { + ret = subcore->core_ops->instance_init_buf(subcore, ctx); + if (ret < 0) { + mfc_err("failed sub core init buffer\n"); + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + return; + } + } + /* + * When mode1, sub core run without command but + * clk_enable is needed because clk mux set to OSC by clk_disable. + * Also, turn off the idle timer because hw_run_bits are not set. + */ + if (IS_TWO_MODE1(ctx)) { + mfc_change_state(core_ctx, MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET); + timer_delete(&subcore->mfc_idle_timer); + mfc_core_pm_clock_on(subcore, 0); + } + + if (dev->num_inst == 1) { + core_ctx = maincore->core_ctx[ctx->num]; + mfc_change_state(core_ctx, MFCINST_RUNNING); + + core_ctx = subcore->core_ctx[ctx->num]; + mfc_change_state(core_ctx, MFCINST_RUNNING); + } + + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + + mfc_debug(2, "[RM][2CORE] multi core mode setup done, check multi inst\n"); + MFC_TRACE_RM("[c:%d] mode2 setup done\n", ctx->num); + if (dev->num_inst > 1) { + /* + * If the load is already distributed in two cores, + * need to move to one core for multi core mode(8K) instance. + */ + if (IS_8K_RES(ctx) && dev->num_inst > 2) + __mfc_rm_migrate_all_to_one_core(dev); + __mfc_rm_check_multi_core_mode(dev, ctx->op_core_type); + + __mfc_rm_request_butler(dev, NULL); + } +} + +static void __mfc_rm_move_buf_request_work(struct mfc_ctx *ctx, enum mfc_request_work work) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int i; + + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_RUNNING)) { + /* search for next running core and running */ + __mfc_rm_move_buf_ready_set_bit(ctx); + } else if (mfc_rm_query_state(ctx, EQUAL, MFCINST_HEAD_PARSED)) { + __mfc_rm_guarantee_init_buf(ctx); + } else { + /* + * If it is not RUNNING, + * each core can work a given job individually. + */ + for (i = 0; i < MFC_CORE_TYPE_NUM; i++) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + break; + + core = dev->core[ctx->op_core_num[i]]; + if (!core) { + mfc_ctx_err("[RM] There is no core[%d]\n", + ctx->op_core_num[i]); + return; + } + mfc_ctx_debug(2, "[RM] request work to MFC-%d\n", core->id); + + core_ctx = core->core_ctx[ctx->num]; + if (!core_ctx || (core_ctx && core_ctx->state < MFCINST_GOT_INST)) + continue; + + if (core->sched->enqueue_work(core, core_ctx)) + if (core->core_ops->request_work(core, work, ctx)) + mfc_debug(3, "[RM] failed to request_work\n"); + } + } +} + +static void __mfc_rm_rearrange_cpb(struct mfc_core *maincore, struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *src_mb; + unsigned long flags; + + /* re-arrangement cpb for mode2 */ + mfc_debug(2, "[RM][2CORE] main core-%d src count %d\n", + maincore->id, core_ctx->src_buf_queue.count); + MFC_TRACE_RM("[c:%d] main core-%d src count %d\n", ctx->num, + maincore->id, core_ctx->src_buf_queue.count); + + mfc_move_buf_all(ctx, &ctx->src_buf_ready_queue, + &core_ctx->src_buf_queue, MFC_QUEUE_ADD_TOP); + + mfc_debug(2, "[RM][2CORE] ready %d maincore %d\n", + ctx->src_buf_ready_queue.count, + maincore->core_ctx[ctx->num]->src_buf_queue.count); + MFC_TRACE_RM("[c:%d] ready %d maincore %d\n", ctx->num, + ctx->src_buf_ready_queue.count, + maincore->core_ctx[ctx->num]->src_buf_queue.count); + + ctx->serial_src_index = 0; + ctx->curr_src_index = -1; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + if (!list_empty(&ctx->src_buf_ready_queue.head)) { + list_for_each_entry(src_mb, &ctx->src_buf_ready_queue.head, list) { + if (src_mb) { + mfc_debug(2, "[RM][2CORE] src index(%d) changed to %d\n", + src_mb->src_index, ctx->serial_src_index); + MFC_TRACE_RM("[c:%d] src index(%d) changed to %d\n", + ctx->num, src_mb->src_index, + ctx->serial_src_index); + src_mb->src_index = ctx->serial_src_index++; + src_mb->used = 0; + } + } + } else { + mfc_debug(2, "[RM][2CORE] there is no src in ready(%d)\n", + ctx->src_buf_ready_queue.count); + MFC_TRACE_RM("[c:%d] there is no src in ready(%d)\n", ctx->num, + ctx->src_buf_ready_queue.count); + } + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + +static int __mfc_rm_switch_to_multi_mode(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *maincore; + struct mfc_core *subcore; + struct mfc_core_ctx *core_ctx; + int ret; + struct mfc_core *changed_subcore; + + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + return -EINVAL; + } + + core_ctx = maincore->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_err("[RM] There is no main core_ctx\n"); + return -EINVAL; + } + + if (!maincore->sched->enqueue_work(maincore, core_ctx)) { + mfc_ctx_debug(2, "[RM] there is no work to do after switch_to_multi\n"); + MFC_TRACE_RM("no work after switch to multi\n"); + return -EINVAL; + } + + subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core for switch single\n"); + return -EINVAL; + } + + ret = mfc_core_get_hwlock_dev(maincore); + if (ret < 0) { + mfc_ctx_err("Failed to get main core hwlock\n"); + return -EINVAL; + } + + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_ctx_err("Failed to get sub core hwlock\n"); + mfc_core_release_hwlock_dev(maincore); + return -EINVAL; + } + + mutex_lock(&ctx->op_mode_mutex); + + if (ctx->op_mode == MFC_OP_SWITCH_BUT_MODE2) { + mfc_ctx_debug(2, "[RMLB] just go to mode2\n"); + } else { + if (!ctx->cmd_counter) { + mfc_ctx_err("It didn't worked on switch to single\n"); + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + mutex_unlock(&ctx->op_mode_mutex); + __mfc_rm_request_butler(ctx->dev, ctx); + return -EINVAL; + } + + mfc_change_op_mode(ctx, MFC_OP_SWITCHING); + __mfc_rm_rearrange_cpb(maincore, core_ctx); + } + + /* main core number of multi core mode should MFC-0 */ + mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); + + /* Change done, it will be work with multi core mode */ + mfc_change_op_mode(ctx, ctx->stream_op_mode); + mfc_ctx_debug(2, "[RM][2CORE] reset multi core op_mode: %d\n", ctx->op_mode); + + changed_subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!changed_subcore) { + mfc_ctx_err("[RM] There is no sub core for flushing context\n"); + return -EINVAL; + } + mfc_core_clear_main_core_context_flush_done(changed_subcore); + + /* for check whether command is sent during switch to multi */ + ctx->cmd_counter = 0; + + mutex_unlock(&ctx->op_mode_mutex); + + mfc_core_release_hwlock_dev(maincore); + mfc_core_release_hwlock_dev(subcore); + mfc_qos_on(maincore, ctx); + mfc_qos_on(subcore, ctx); + + __mfc_rm_move_buf_ready_set_bit(ctx); + + return 0; +} + +static void __mfc_rm_check_instance(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + int ret; + + if (!IS_MULTI_CORE_DEVICE(dev)) + return; + + if (dev->num_inst == 1 && IS_SWITCH_SINGLE_MODE(ctx)) { + /* + * If there is only one instance and it is still switch to single mode, + * switch to multi core mode again. + */ + ret = __mfc_rm_switch_to_multi_mode(ctx); + if (ret) + mfc_ctx_info("[RM] Keep switch to single mode\n"); + } else if (dev->num_inst > 1) { + /* + * If there are more than one instance and it is still multi core mode, + * switch to single mode. + */ + ret = __mfc_rm_check_multi_core_mode(dev, ctx->op_core_type); + if (ret < 0) + mfc_ctx_err("[RM] failed multi core instance switching\n"); + } +} + +void mfc_rm_migration_worker(struct work_struct *work) +{ + struct mfc_dev *dev; + struct mfc_ctx *ctx; + int to_core_num, from_core_num; + int i, ret = 0; + + dev = container_of(work, struct mfc_dev, migration_work); + + for (i = 0; i < dev->move_ctx_cnt; i++) { + mutex_lock(&dev->mfc_migrate_mutex); + ctx = dev->move_ctx[i]; + dev->move_ctx[i] = NULL; + + /* + * If one instance fails migration, + * the rest of instnaces will not migrate. + */ + if (ret || !ctx) { + MFC_TRACE_RM("migration fail\n"); + mutex_unlock(&dev->mfc_migrate_mutex); + continue; + } + + ret = mfc_get_corelock_migrate(ctx); + if (ret < 0) { + mfc_ctx_err("[RMLB] failed to get corelock\n"); + mutex_unlock(&dev->mfc_migrate_mutex); + return; + } + if (IS_SWITCH_SINGLE_MODE(ctx)) { + mutex_unlock(&dev->mfc_migrate_mutex); + mfc_ctx_debug(2, "[RMLB][2CORE] ctx[%d] will change op_mode: %d -> %d\n", + ctx->num, ctx->op_mode, ctx->stream_op_mode); + MFC_TRACE_RM("[c:%d] will change op_mode: %d -> %d\n", + ctx->num, ctx->op_mode, ctx->stream_op_mode); + ret = __mfc_rm_switch_to_multi_mode(ctx); + if (dev->move_ctx_cnt > 1) { + mfc_ctx_err("[RMLB] there shouldn't be another instance because of mode2\n"); + MFC_TRACE_RM("[c:%d] no another inst for mode2\n", ctx->num); + ret = -EINVAL; + } + mfc_release_corelock_migrate(ctx); + continue; + } else { + mfc_release_corelock_migrate(ctx); + } + + from_core_num = ctx->op_core_num[MFC_CORE_MAIN]; + to_core_num = ctx->move_core_num[MFC_CORE_MAIN]; + mfc_ctx_debug(2, "[RMLB] ctx[%d] will be moved MFC%d -> MFC%d\n", + ctx->num, from_core_num, to_core_num); + MFC_TRACE_RM("[c:%d] will be moved MFC%d -> MFC%d\n", + ctx->num, from_core_num, to_core_num); + ret = __mfc_rm_move_core_running(ctx, to_core_num, from_core_num); + if (ret) { + mfc_ctx_info("[RMLB] migration stopped by ctx[%d]\n", + ctx->num); + MFC_TRACE_RM("migration fail by ctx[%d]\n", ctx->num); + } + mutex_unlock(&dev->mfc_migrate_mutex); + } + + mfc_dev_debug(2, "[RMLB] all instance migration finished\n"); + dev->move_ctx_cnt = 0; + + __mfc_rm_request_butler(dev, NULL); +} + +static int __mfc_rm_load_delete(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx *mfc_ctx, *tmp_ctx; + + list_for_each_entry_safe(mfc_ctx, tmp_ctx, &dev->ctx_list, list) { + if (mfc_ctx == ctx) { + list_del(&mfc_ctx->list); + mfc_ctx_debug(3, "[RMLB] ctx[%d] is deleted from list\n", ctx->num); + MFC_TRACE_RM("[c:%d] load delete\n", ctx->num); + return 0; + } + } + + return 1; +} + +static int __mfc_rm_load_add(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx *tmp_ctx; + + /* list create */ + if (list_empty(&dev->ctx_list)) { + list_add(&ctx->list, &dev->ctx_list); + MFC_TRACE_RM("[c:%d] load add first\n", ctx->num); + return 1; + } + + /* If ctx has already added, delete for reordering */ + __mfc_rm_load_delete(ctx); + + /* dev->ctx_list is aligned in descending order of load */ + list_for_each_entry_reverse(tmp_ctx, &dev->ctx_list, list) { + if (tmp_ctx->weighted_mb > ctx->weighted_mb) { + list_add(&ctx->list, &tmp_ctx->list); + mfc_ctx_debug(3, "[RMLB] ctx[%d] is added to list\n", ctx->num); + MFC_TRACE_RM("[c:%d] load add\n", ctx->num); + return 0; + } + } + + /* add to the front of dev->list */ + list_add(&ctx->list, &dev->ctx_list); + mfc_ctx_debug(3, "[RMLB] ctx[%d] is added to list\n", ctx->num); + MFC_TRACE_RM("[c:%d] load add\n", ctx->num); + + return 0; +} + +static int __mfc_rm_check_load_balancing_condition(struct mfc_ctx *ctx, int load_add) +{ + struct mfc_dev *dev = ctx->dev; + int i; + + if (!IS_MULTI_CORE_DEVICE(dev)) { + mfc_ctx_debug(4, "[RMLB] it is not multi core device\n"); + return 1; + } + + if (!ctx->src_ts.ts_is_full && load_add == MFC_RM_LOAD_ADD) { + mfc_ctx_debug(2, "[RMLB] instance load is not yet fixed\n"); + return 1; + } + + if (dev->move_ctx_cnt || load_add == MFC_RM_LOAD_DELETE || + (dev->num_inst == 1 && load_add == MFC_RM_LOAD_ADD)) { + mfc_ctx_debug(4, "[RMLB] instance migration isn't need (num_inst: %d, move_ctx: %d)\n", + dev->num_inst, dev->move_ctx_cnt); + return 1; + } + + if (list_empty(&dev->ctx_list)) { + for (i = 0; i < dev->num_core; i++) + dev->core[i]->total_mb = 0; + mfc_ctx_debug(2, "[RMLB] there is no ctx for load balancing\n"); + return 1; + } + + return 0; +} + +void mfc_rm_load_balancing(struct mfc_ctx *ctx, int load_add) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx *tmp_ctx; + unsigned long flags; + int i, core_num, ret = 0; + + if (dev->pdata->core_balance == 100) { + mfc_ctx_debug(4, "[RMLB] do not want to load balancing\n"); + return; + } + + spin_lock_irqsave(&dev->ctx_list_lock, flags); + if (load_add == MFC_RM_LOAD_ADD) + ret = __mfc_rm_load_add(ctx); + else + ret = __mfc_rm_load_delete(ctx); + if (ret) { + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } + + /* check the MFC IOVA and control lazy unmap */ + mfc_check_iova(dev); + + /* check if load balancing is not required */ + if (__mfc_rm_check_load_balancing_condition(ctx, load_add)) { + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return; + } + + /* Clear total mb each core for load re-calculation */ + for (i = 0; i < dev->num_core; i++) + dev->core[i]->total_mb = 0; + + /* 1) Load balancing of instance with fixed core */ + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) { + if (tmp_ctx->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(3, "[RMLB][MFCIDLE] idle ctx[%d] excluded from load balancing\n", + tmp_ctx->num); + continue; + } + if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_0 || + tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_1) + __mfc_rm_update_core_load(tmp_ctx, 0, 0); + } + + /* 2) Load balancing of instance with not-fixed core */ + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) { + if (tmp_ctx->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(3, "[RMLB][MFCIDLE] idle ctx[%d] excluded from load balancing\n", + tmp_ctx->num); + continue; + } + if (tmp_ctx->op_core_type != MFC_OP_CORE_ALL) { + mfc_ctx_debug(3, "[RMLB] fixed core ctx[%d] can't be moved\n", + tmp_ctx->num); + continue; + } + + if (IS_MULTI_MODE(tmp_ctx)) { + __mfc_rm_update_core_load(tmp_ctx, 0, 1); + continue; + } else if (IS_SWITCH_SINGLE_MODE(tmp_ctx) && (dev->num_inst == 1)) { + mfc_ctx_debug(2, "[RMLB] ctx[%d] can be changed to mode%d\n", + tmp_ctx->num, tmp_ctx->stream_op_mode); + MFC_TRACE_RM("[c:%d] can be changed to mode%d\n", + tmp_ctx->num, tmp_ctx->stream_op_mode); + dev->move_ctx[dev->move_ctx_cnt++] = tmp_ctx; + __mfc_rm_update_core_load(tmp_ctx, 0, 1); + continue; + } + core_num = __mfc_rm_get_core_num_by_load(dev, tmp_ctx, MFC_DEC_DEFAULT_CORE); + if (IS_SWITCH_SINGLE_MODE(tmp_ctx) || + core_num == tmp_ctx->op_core_num[MFC_CORE_MAIN]) { + mfc_ctx_debug(3, "[RMLB] ctx[%d] keep core%d\n", tmp_ctx->num, + tmp_ctx->op_core_num[MFC_CORE_MAIN]); + __mfc_rm_update_core_load(tmp_ctx, 0, 0); + } else { + /* Instance should move */ + mfc_ctx_debug(3, "[RMLB] ctx[%d] move to core-%d\n", + tmp_ctx->num, core_num); + MFC_TRACE_RM("[c:%d] move to core-%d\n", tmp_ctx->num, core_num); + tmp_ctx->move_core_num[MFC_CORE_MAIN] = core_num; + dev->move_ctx[dev->move_ctx_cnt++] = tmp_ctx; + __mfc_rm_update_core_load(tmp_ctx, 1, 0); + } + } + + /* For debugging */ + mfc_ctx_debug(3, "[RMLB] ===================ctx list===================\n"); + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) + mfc_show_ctx_info(tmp_ctx); + + mfc_ctx_debug(3, "[RMLB] >>>> core balance %d%%\n", dev->core_balance); + for (i = 0; i < dev->num_core; i++) + mfc_ctx_debug(3, "[RMLB] >> MFC-%d total load: %lu%%\n", i, + dev->core[i]->total_mb * 100 / dev->core[i]->core_pdata->max_mb); + mfc_ctx_debug(3, "[RMLB] ==============================================\n"); + + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + + if (dev->move_ctx_cnt) + queue_work(dev->migration_wq, &dev->migration_work); +} + int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx) { struct mfc_core *core; - int i, ret; + int num_qos_steps; + int i, ret; + + mfc_ctx_debug_enter(); + + mfc_get_corelock_ctx(ctx); + + /* + * The FW memory for all cores is allocated in advance. + * (Only once at first time) + * Because FW base address should be the lowest address + * than all DVA that FW approaches. + */ + for (i = 0; i < dev->num_core; i++) { + core = dev->core[i]; + if (!core) { + mfc_ctx_err("[RM] There is no MFC-%d\n", i); + continue; + } + + if (!(core->fw.status & MFC_FW_ALLOC)) { + ret = mfc_alloc_firmware(core); + if (ret) + goto err_inst_init; + } + + if (!(core->fw.status & MFC_CTX_ALLOC)) { + ret = mfc_alloc_common_context(core); + if (ret) + goto err_inst_init; + } + } + + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; + if (ctx->type == MFCINST_DECODER) + ctx->op_core_num[MFC_CORE_MAIN] = MFC_DEC_DEFAULT_CORE; + else + ctx->op_core_num[MFC_CORE_MAIN] = MFC_ENC_DEFAULT_CORE; + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + ret = -EINVAL; + goto err_inst_init; + } + + mfc_ctx_debug(2, "[RM] init instance core-%d\n", + ctx->op_core_num[MFC_CORE_MAIN]); + ret = core->core_ops->instance_init(core, ctx); + if (ret) { + ctx->op_core_num[MFC_CORE_MAIN] = MFC_CORE_INVALID; + mfc_ctx_err("[RM] Failed to init\n"); + } + + /* + * QoS portion data should be allocated + * only once per instance after maincore is determined. + */ + num_qos_steps = core->core_pdata->num_default_qos_steps; + + ctx->mfc_qos_portion = vmalloc(sizeof(unsigned int) * num_qos_steps); + if (!ctx->mfc_qos_portion) + ret = -ENOMEM; + +err_inst_init: + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); + + return ret; +} + +int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core = NULL, *subcore; + int i, ret = 0; + + mfc_ctx_debug_enter(); + + mfc_get_corelock_ctx(ctx); + + /* reset original stream mode */ + mutex_lock(&ctx->op_mode_mutex); + if (IS_SWITCH_SINGLE_MODE(ctx)) { + mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); + mfc_change_op_mode(ctx, ctx->stream_op_mode); + } + mutex_unlock(&ctx->op_mode_mutex); + + if (IS_TWO_MODE1(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) + mfc_ctx_err("[RM] There is no sub core for clock off\n"); + else + mfc_core_pm_clock_off(subcore, 0); + } + + for (i = (MFC_CORE_TYPE_NUM - 1); i >= 0; i--) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + continue; + + core = dev->core[ctx->op_core_num[i]]; + if (!core) { + mfc_ctx_err("[RM] There is no core[%d]\n", + ctx->op_core_num[i]); + ret = -EINVAL; + goto err_inst_deinit; + } + + mfc_core_debug(2, "[RM] core%d will be deinit, ctx[%d]\n", + i, ctx->num); + ret = core->core_ops->instance_deinit(core, ctx); + if (ret) + mfc_core_err("[RM] Failed to deinit\n"); + } + + clear_bit(ctx->num, &dev->multi_core_inst_bits); + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; + +err_inst_deinit: + if (core) + mfc_qos_get_portion(core, ctx); + vfree(ctx->mfc_qos_portion); + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); + + return ret; +} + +int mfc_rm_instance_open(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core; + int ret = 0, core_num; + int is_corelock = 0; + + mfc_ctx_debug_enter(); + + ctx->op_core_type = dev->pdata->mfc_resource[ctx->codec_mode].op_core_type; + mfc_qos_get_weighted_mb(ctx, ctx->rt); + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + ret = -EINVAL; + goto err_inst_open; + } + + if (IS_MULTI_CORE_DEVICE(dev)) { + mfc_get_corelock_ctx(ctx); + is_corelock = 1; + + /* Core balance by both standard and load */ + core_num = __mfc_rm_get_core_num(ctx, core->id); + if (core_num != core->id) { + ret = __mfc_rm_move_core_open(ctx, core_num, core->id); + if (ret) + goto err_inst_open; + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + ret = -EINVAL; + goto err_inst_open; + } + } + + /* + * When there is instance of multi core mode, + * other instance should be open in MFC-0 + */ + ret = __mfc_rm_check_multi_core_mode(dev, ctx->op_core_type); + if (ret < 0) { + mfc_ctx_err("[RM] failed multi core instance switching\n"); + goto err_inst_open; + } + } + + ret = core->core_ops->instance_open(core, ctx); + if (ret) { + mfc_core_err("[RM] Failed to open\n"); + goto err_inst_open; + } + +err_inst_open: + if (is_corelock) + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); + + return ret; +} + +/* For 2core DRC. + * 1) CACHE_FLUSH(main) -> CLOSE_INST(sub) -> CACHE_FLUSH(sub) + * 2) Clear multi_core_inst_bits + * 3) Change state to MFCINST_RES_CHANGE_END + */ +static void __mfc_rm_handle_drc_sub_core_deinit(struct mfc_ctx *ctx) +{ + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_core *subcore; + int ret; + + mutex_lock(&ctx->op_mode_mutex); + + core = mfc_get_main_core(ctx->dev, ctx); + if (!core) + return; + + core_ctx = core->core_ctx[ctx->num]; + + subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!subcore) { + mutex_unlock(&ctx->op_mode_mutex); + return; + } + + if (IS_SINGLE_MODE(ctx)) { + mutex_unlock(&ctx->op_mode_mutex); + return; + } + + ctx->subcore_inst_no = MFC_NO_INSTANCE_SET; + ctx->op_core_num[MFC_CORE_SUB] = MFC_CORE_INVALID; + ctx->op_core_type = MFC_OP_CORE_ALL; + + ctx->stream_op_mode = MFC_OP_SINGLE; + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + + mfc_ctx_debug(2, "[RM][2CORE][DRC] DRC update op_mode: %d\n", ctx->op_mode); + + mutex_unlock(&ctx->op_mode_mutex); + + /* deinit subcore, this instance will be operate with single core */ + if (IS_TWO_MODE1(ctx)) + mfc_core_pm_clock_off(subcore, 0); + + /* If 2-core mode, cache_flush(MAIN) is needed + * after LAST_FRAME(MAIN) & before CLOSE_INST(SUB) + */ + core->core_ops->instance_cache_flush(core, ctx); + + ret = subcore->core_ops->instance_deinit(subcore, ctx); + + mutex_lock(&ctx->op_mode_mutex); + clear_bit(ctx->num, &ctx->dev->multi_core_inst_bits); + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_END); + mutex_unlock(&ctx->op_mode_mutex); + + if (ret) + mfc_core_err("[RM][2CORE][DRC] Failed to deinit\n"); +} + +static void __mfc_rm_inst_dec_dst_stop(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *maincore; + struct mfc_core *subcore; + struct mfc_core_ctx *core_ctx; + int ret; + + mfc_ctx_debug(3, "op_mode: %d\n", ctx->op_mode); + + mfc_get_corelock_ctx(ctx); + + if (IS_TWO_MODE2(ctx) || IS_SWITCH_SINGLE_MODE(ctx)) { + /* After sub core operation, dpb flush from main core */ + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core for switch single\n"); + goto err_dst_stop; + } + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_ctx_err("Failed to get sub core hwlock\n"); + goto err_dst_stop; + } + mfc_core_release_hwlock_dev(subcore); + + maincore = mfc_get_main_core(dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + goto err_dst_stop; + } + maincore->core_ops->instance_dpb_flush(maincore, ctx); + /* Check one more time, because sub core could be denit-ed by DRC */ + if (IS_TWO_MODE2(ctx) || IS_SWITCH_SINGLE_MODE(ctx)) { + /* If drc is running yet, we need to deinit first. */ + core_ctx = subcore->core_ctx[ctx->num]; + if (ON_RES_CHANGE(core_ctx)) + __mfc_rm_handle_drc_sub_core_deinit(ctx); + else + subcore->core_ops->instance_dpb_flush(subcore, ctx); + } + } else { + maincore = mfc_get_main_core(dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + goto err_dst_stop; + } + + maincore->core_ops->instance_dpb_flush(maincore, ctx); + } + + mfc_clear_core_intlock(ctx); + +err_dst_stop: + mfc_release_corelock_ctx(ctx); +} + +static void __mfc_core_cleanup_subcore_for_drc(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core *maincore, *subcore = 0; + + core = __mfc_rm_switch_to_single_mode(ctx, 1, MFC_OP_CORE_FIXED_1); + if (!core) { + mfc_ctx_err("[RM][2CORE] failed to switch to single for src_stop\n"); + return; + } + mfc_ctx_debug(2, "[RM][2CORE] switch single for src_stop, op_mode: %d\n", + ctx->op_mode); + + /* reset original stream mode */ + mutex_lock(&ctx->op_mode_mutex); + mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); + mfc_change_op_mode(ctx, ctx->stream_op_mode); + maincore = mfc_get_main_core(dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + goto release_op_mode_mutex; + } + + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core\n"); + goto release_op_mode_mutex; + } + + mutex_unlock(&ctx->op_mode_mutex); + + mfc_qos_on(maincore, ctx); + mfc_qos_on(subcore, ctx); + +release_op_mode_mutex: + mutex_unlock(&ctx->op_mode_mutex); +} + +static void __mfc_core_cancel_drc(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + + mfc_info("[DRC] DRC is running yet (state: %d) cancel DRC\n", core_ctx->state); + + mutex_lock(&ctx->drc_wait_mutex); + + if (!ctx->handle_drc_multi_mode) + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_END); + + ctx->wait_state &= ~(WAIT_STOP); + mfc_debug(2, "clear WAIT_STOP %d\n", ctx->wait_state); + MFC_TRACE_CORE_CTX("** DEC clear WAIT_STOP(wait_state %d)\n", + ctx->wait_state); + + if (ctx->wait_state != WAIT_G_FMT) { + ctx->wait_state = WAIT_G_FMT; + mfc_debug(2, "set WAIT_G_FMT only for inform to user that needs g_fmt\n"); + } + mutex_unlock(&ctx->drc_wait_mutex); +} + +static void __mfc_core_src_cleanup(struct mfc_core *maincore, struct mfc_core *subcore, + struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *maincore_ctx = maincore->core_ctx[ctx->num]; + struct mfc_core_ctx *subcore_ctx = 0; + int index = 0; + + /* Header parsed buffer is in src_buf_ready_queue */ + mfc_move_buf_all(ctx, &maincore_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, MFC_QUEUE_ADD_BOTTOM); + MFC_TRACE_CTX("Move all src to queue\n"); + dec->consumed = 0; + dec->has_multiframe = 0; + maincore_ctx->check_dump = 0; + ctx->curr_src_index = -1; + ctx->serial_src_index = 0; + + mfc_cleanup_queue(&ctx->buf_queue_lock, &maincore_ctx->src_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue); + + mfc_init_queue(&maincore_ctx->src_buf_queue); + mfc_init_queue(&ctx->src_buf_ready_queue); + + maincore->sched->clear_work(maincore, maincore_ctx); + + if (ON_RES_CHANGE(maincore_ctx)) + __mfc_core_cancel_drc(maincore, maincore_ctx); + + if (subcore) { + subcore_ctx = subcore->core_ctx[ctx->num]; + mfc_move_buf_all(ctx, &subcore_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, MFC_QUEUE_ADD_BOTTOM); + MFC_TRACE_CTX("Move all src(sub) to queue\n"); + + subcore_ctx->check_dump = 0; + + mfc_cleanup_queue(&ctx->buf_queue_lock, &subcore_ctx->src_buf_queue); + mfc_init_queue(&subcore_ctx->src_buf_queue); + + subcore->sched->clear_work(subcore, subcore_ctx); + + if (ON_RES_CHANGE(subcore_ctx)) + __mfc_core_cancel_drc(subcore, subcore_ctx); + } + + while (index < MFC_MAX_BUFFERS) { + index = find_next_bit(ctx->src_ctrls_avail, MFC_MAX_BUFFERS, index); + if (index < MFC_MAX_BUFFERS) + call_cop(ctx, reset_buf_ctrls, &ctx->src_ctrls[index]); + index++; + } + + if (maincore_ctx->state == MFCINST_FINISHING) + mfc_change_state(maincore_ctx, MFCINST_RUNNING); + + if (subcore_ctx && subcore_ctx->state == MFCINST_FINISHING) + mfc_change_state(subcore_ctx, MFCINST_RUNNING); + + mfc_ctx_debug(2, "decoder source stop sequence done\n"); +} + +static void __mfc_rm_inst_dec_src_stop(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *maincore; + struct mfc_core *subcore = 0; + struct mfc_core_ctx *maincore_ctx = 0, *subcore_ctx = 0; + int ret; + + mfc_ctx_debug(2, "op_mode: %d\n", ctx->op_mode); + + mfc_get_corelock_ctx(ctx); + + maincore = mfc_get_main_core(dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + goto release_corelock; + } + maincore_ctx = maincore->core_ctx[ctx->num]; + if (!maincore_ctx) { + mfc_ctx_err("[RM] There is no main core_ctx\n"); + goto release_corelock; + } + ret = mfc_core_get_hwlock_dev(maincore); + if (ret < 0) { + mfc_ctx_err("Failed to get hwlock of maincore\n"); + goto release_corelock; + } + + if (IS_TWO_MODE2(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core\n"); + goto release_hwlock_main; + } + subcore_ctx = subcore->core_ctx[ctx->num]; + if (!subcore_ctx) { + mfc_ctx_err("[RM] There is no sub core_ctx\n"); + goto release_hwlock_main; + } + ret = mfc_core_get_hwlock_dev(subcore); + if (ret < 0) { + mfc_ctx_err("Failed to get hwlock of subcore\n"); + goto release_hwlock_main; + } + } + + mutex_lock(&ctx->op_mode_mutex); + + __mfc_core_src_cleanup(maincore, subcore, ctx); + + if (maincore->state == MFCCORE_ERROR || maincore_ctx->state == MFCINST_ERROR || + (subcore_ctx && subcore_ctx->state == MFCINST_ERROR)) + goto release_op_mode_mutex; + + mutex_unlock(&ctx->op_mode_mutex); + + if (subcore) + mfc_core_release_hwlock_dev(subcore); + mfc_core_release_hwlock_dev(maincore); + + if (IS_TWO_MODE2(ctx) && !ON_RUNNING(maincore_ctx)) + __mfc_core_cleanup_subcore_for_drc(ctx); + + mfc_release_corelock_ctx(ctx); + + maincore->sched->enqueue_work(maincore, maincore_ctx); + if (maincore->sched->is_work(maincore)) + maincore->sched->queue_work(maincore); + return; + +release_op_mode_mutex: + mutex_unlock(&ctx->op_mode_mutex); + if (subcore) + mfc_core_release_hwlock_dev(subcore); +release_hwlock_main: + mfc_core_release_hwlock_dev(maincore); +release_corelock: + mfc_release_corelock_ctx(ctx); + + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue); + if (maincore_ctx) + mfc_cleanup_queue(&ctx->buf_queue_lock, &maincore_ctx->src_buf_queue); + if (subcore_ctx) + mfc_cleanup_queue(&ctx->buf_queue_lock, &subcore_ctx->src_buf_queue); +} + +void mfc_rm_instance_dec_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, + unsigned int type) +{ + mfc_ctx_debug_enter(); + + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + __mfc_rm_inst_dec_dst_stop(dev, ctx); + else if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + __mfc_rm_inst_dec_src_stop(dev, ctx); + + mfc_ctx_debug_leave(); +} + +int mfc_rm_subcore_seq_start(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; - mfc_ctx_debug_enter(); + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no sub core\n"); + return -EINVAL; + } + + core_ctx = core->core_ctx[ctx->num]; + + if (core->sched->enqueue_work(core, core_ctx)) + core->core_ops->request_work(core, MFC_WORK_BUTLER, ctx); + + mfc_debug(2, "[RM] waiting for header parsing of sub core\n"); + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + mfc_err("[RM] sub core header parsing failed\n"); + return -EAGAIN; + } + + mfc_change_op_mode(ctx, ctx->stream_op_mode); + mfc_qos_on(core, ctx); + + return 0; +} + +int mfc_rm_instance_setup(struct mfc_dev *dev, struct mfc_ctx *ctx) +{ + struct mfc_core *maincore, *core; + struct mfc_core_ctx *core_ctx, *maincore_ctx; + struct mfc_buf_queue *from_queue; + struct mfc_buf *src_mb = NULL; + int ret = 0; + + if (ctx->op_core_num[MFC_CORE_SUB] != MFC_CORE_INVALID) { + mfc_ctx_info("[RM] sub core already setup\n"); + return 0; + } + + mfc_rm_set_core_num(ctx, ctx->op_core_num[MFC_CORE_MAIN]); + + maincore = mfc_get_main_core(dev, ctx); + if (!maincore) { + mfc_ctx_err("[RM] There is no main core\n"); + return -EINVAL; + } + maincore_ctx = maincore->core_ctx[ctx->num]; + + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no sub core\n"); + return -EINVAL; + } + + ret = core->core_ops->instance_init(core, ctx); + if (ret) { + mfc_ctx_err("[RM] sub core init failed\n"); + goto fail_init; + } + core_ctx = core->core_ctx[ctx->num]; + + ret = core->core_ops->instance_open(core, ctx); + if (ret) { + mfc_err("[RM] sub core open failed\n"); + goto fail_open; + } + + if (ctx->type == MFCINST_DECODER) { + from_queue = &maincore_ctx->src_buf_queue; + + src_mb = mfc_get_buf(ctx, from_queue, MFC_BUF_NO_TOUCH_USED); + if (!src_mb) { + mfc_err("[RM] there is no header buffers\n"); + ret = -EAGAIN; + goto fail_open; + } + + mutex_lock(&ctx->op_mode_mutex); + /* When DRC case, it needs to rearrange src buffer for mode1,2 */ + if (ctx->wait_state) { + if (ctx->stream_op_mode == MFC_OP_TWO_MODE2) { + __mfc_rm_rearrange_cpb(maincore, maincore_ctx); + from_queue = &ctx->src_buf_ready_queue; + } + if (ctx->stream_op_mode == MFC_OP_TWO_MODE1) { + mfc_move_buf_all(ctx, &ctx->src_buf_ready_queue, + &maincore_ctx->src_buf_queue, MFC_QUEUE_ADD_TOP); + from_queue = &ctx->src_buf_ready_queue; + } + } + mutex_unlock(&ctx->op_mode_mutex); + + /* Move the header buffer to sub core */ + src_mb = mfc_get_move_buf(ctx, &core_ctx->src_buf_queue, from_queue, + MFC_BUF_NO_TOUCH_USED, MFC_QUEUE_ADD_TOP); + if (!src_mb) { + mfc_err("[RM] there is no header buffers\n"); + ret = -EAGAIN; + goto fail_open; + } else { + MFC_TRACE_RM("[c:%d] SETUP: Move src[%d] to queue\n", + ctx->num, src_mb->src_index); + } + + if (ctx->dec_priv->consumed) { + mfc_debug(2, "[STREAM][2CORE] src should be without consumed\n"); + ctx->dec_priv->consumed = 0; + } + } + + if (core->sched->enqueue_work(core, core_ctx)) + core->core_ops->request_work(core, MFC_WORK_BUTLER, ctx); + + mfc_debug(2, "[RM] waiting for header parsing of sub core\n"); + if (mfc_wait_for_done_core_ctx(core_ctx, + MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + mfc_err("[RM] sub core header parsing failed\n"); + ret = -EAGAIN; + goto fail_open; + } + + if (ctx->type == MFCINST_DECODER) { + /* Move back the header buffer to ready_queue */ + mfc_get_move_buf(ctx, &ctx->src_buf_ready_queue, + &core_ctx->src_buf_queue, + MFC_BUF_RESET_USED, MFC_QUEUE_ADD_TOP); + } + + /* main core number of multi core mode should MFC-0 */ + if (ctx->op_core_num[MFC_CORE_SUB] == MFC_DEC_DEFAULT_CORE) { + /* return src buffers of main&sub core to ready_queue */ + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_err("[RM] There is no sub core\n"); + return -EINVAL; + } + mfc_return_buf_to_ready_queue(ctx, &maincore->core_ctx[ctx->num]->src_buf_queue, + &core->core_ctx[ctx->num]->src_buf_queue); + + mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); + mfc_debug(2, "[RM] main core changed to MFC0\n"); + + maincore = mfc_get_main_core(ctx->dev, ctx); + if (!maincore) { + mfc_err("[RM] There is no main core\n"); + return -EINVAL; + } + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_err("[RM] There is no sub core\n"); + return -EINVAL; + } + + /* main core should have one src buffer */ + core_ctx = maincore->core_ctx[ctx->num]; + if (mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue) == 0) { + src_mb = mfc_get_move_buf(ctx, &core_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, + MFC_BUF_NO_TOUCH_USED, MFC_QUEUE_ADD_BOTTOM); + if (src_mb) { + mfc_debug(2, "[RM][BUFINFO] MFC-%d uses src index: %d(%d)\n", + maincore->id, src_mb->vb.vb2_buf.index, + src_mb->src_index); + MFC_TRACE_RM("[c:%d] MFC-%d uses src index: %d(%d)\n", + ctx->num, maincore->id, src_mb->vb.vb2_buf.index, + src_mb->src_index); + } + } else { + mfc_debug(2, "[RM][BUFINFO] MFC-%d has src buffer already\n", maincore->id); + } + + /* sub core inst_no is needed at INIT_BUF */ + ctx->subcore_inst_no = core->core_ctx[ctx->num]->inst_no; + mfc_debug(2, "[RM] sub core setup inst_no: %d\n", ctx->subcore_inst_no); + } else { + /* sub core inst_no is needed at INIT_BUF */ + ctx->subcore_inst_no = core_ctx->inst_no; + mfc_debug(2, "[RM] sub core setup inst_no: %d\n", ctx->subcore_inst_no); + } + + mfc_change_op_mode(ctx, ctx->stream_op_mode); + mfc_qos_on(core, ctx); + + return ret; + +fail_open: + if (core->core_ops->instance_deinit(core, ctx)) + mfc_ctx_err("[RMLB] Failed to deinit\n"); +fail_init: + ctx->op_core_num[MFC_CORE_SUB] = MFC_CORE_INVALID; + + return ret; +} + +void mfc_rm_request_work(struct mfc_dev *dev, enum mfc_request_work work, + struct mfc_ctx *ctx) +{ + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int is_corelock = 0; + + /* This is a request that may not be struct mfc_ctx */ + if (work == MFC_WORK_BUTLER) { + __mfc_rm_request_butler(dev, ctx); + return; + } + + if (!ctx) { + mfc_dev_err("[RM] ctx is needed (request work: %#x)\n", work); + return; + } + + if (mfc_rm_query_state(ctx, EQUAL_OR, MFCINST_RES_CHANGE_INIT) && !IS_SINGLE_MODE(ctx)) { + /* When 2-core DRC, switch_to_single is needed */ + __mfc_rm_switch_to_single_mode(ctx, 1, ctx->op_core_type); + } + + /* If 2core DRC, CACHE_FLUSH of main core and deinit of sub core are needed. + * If not 2core DRC, just change the state to MFCINST_RES_CHANGE_END. + */ + if (ctx->handle_drc_multi_mode && + mfc_rm_query_state(ctx, EQUAL_OR, MFCINST_RES_CHANGE_FLUSH_FINISHED)) + __mfc_rm_handle_drc_sub_core_deinit(ctx); + + if (IS_TWO_MODE2(ctx)) { + __mfc_rm_move_buf_request_work(ctx, work); + return; + } else if (IS_MODE_SWITCHING(ctx)) { + mfc_ctx_debug(3, "[RM] mode switching op_mode: %d\n", ctx->op_mode); + MFC_TRACE_RM("[c:%d] mode switching op_mode: %d\n", ctx->num, ctx->op_mode); + return; + } + + if (IS_TWO_MODE1(ctx)) { + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_HEAD_PARSED) || + mfc_rm_query_state(ctx, EQUAL_OR, + MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET)) { + __mfc_rm_guarantee_init_buf(ctx); + return; + } + } mfc_get_corelock_ctx(ctx); + is_corelock = 1; + + mutex_lock(&ctx->op_mode_mutex); + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mutex_unlock(&ctx->op_mode_mutex); + goto err_req_work; + } + + if (IS_TWO_MODE2(ctx) || IS_MODE_SWITCHING(ctx)) { + /* do not move the src buffer */ + mfc_ctx_debug(2, "[RM] mode was changed op_mode: %d\n", ctx->op_mode); + MFC_TRACE_RM("[c:%d] mode was changed op_mode: %d\n", ctx->num, ctx->op_mode); + mutex_unlock(&ctx->op_mode_mutex); + goto err_req_work; + } + + /* move src buffer to src_buf_queue from src_buf_ready_queue */ + core_ctx = core->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_err("[RM] core_ctx is NULL\n"); + mutex_unlock(&ctx->op_mode_mutex); + goto err_req_work; + } + mfc_move_buf_all(ctx, &core_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, MFC_QUEUE_ADD_BOTTOM); /* - * The FW memory for all cores is allocated in advance. - * (Only once at first time) - * Because FW base address should be the lowest address - * than all DVA that FW approaches. + * When op_mode is changed at that time, + * if the two cores are not RUNNING state, they are not ready. */ - for (i = 0; i < dev->num_core; i++) { - core = dev->core[i]; - if (!core) { - mfc_ctx_err("[RM] There is no MFC-%d\n", i); - continue; + if (IS_TWO_MODE1(ctx) && !mfc_rm_query_state(ctx, EQUAL_BIGGER, MFCINST_HEAD_PARSED)) { + mfc_ctx_debug(2, "[RM] request_work to run SEQ_START again for mode-1\n"); + } else if (IS_MULTI_MODE(ctx) && !mfc_rm_query_state(ctx, EQUAL_BIGGER, MFCINST_RUNNING)) { + mfc_ctx_debug(2, "[RM] op_mode%d set but not ready\n", ctx->op_mode); + MFC_TRACE_RM("[c:%d] op_mode%d set but not ready\n", ctx->num, ctx->op_mode); + mutex_unlock(&ctx->op_mode_mutex); + goto err_req_work; + } + + mutex_unlock(&ctx->op_mode_mutex); + + mutex_lock(&ctx->drc_wait_mutex); + if (ctx->wait_state == WAIT_G_FMT && + (mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue) > 0)) + mfc_dec_drc_find_del_buf(core_ctx); + mutex_unlock(&ctx->drc_wait_mutex); + + /* set core context work bit if it is ready */ + if (core->sched->enqueue_work(core, core_ctx)) + if (core->core_ops->request_work(core, work, ctx)) + mfc_ctx_debug(3, "[RM] failed to request_work\n"); + +err_req_work: + if (is_corelock) + mfc_release_corelock_ctx(ctx); +} + +void mfc_rm_qos_control(struct mfc_ctx *ctx, enum mfc_qos_control qos_control) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + bool update_idle = 0; + + mfc_get_corelock_ctx(ctx); + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_debug(2, "[RM] There is no main core\n"); + goto release_corelock; + } + + switch (qos_control) { + case MFC_QOS_ON: + mfc_qos_on(core, ctx); + if (IS_MULTI_MODE(ctx)) { + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no sub core\n"); + goto release_corelock; + } + + mfc_qos_on(core, ctx); } - if (!(core->fw.status & MFC_FW_ALLOC)) { - ret = mfc_alloc_firmware(core); - if (ret) - goto err_inst_init; + mfc_rm_load_balancing(ctx, MFC_RM_LOAD_ADD); + __mfc_rm_check_instance(ctx); + break; + case MFC_QOS_OFF: + mfc_qos_off(core, ctx); + if (IS_MULTI_MODE(ctx)) { + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no sub core\n"); + goto release_corelock; + } + + mfc_qos_off(core, ctx); } + break; + case MFC_QOS_TRIGGER: + update_idle = mfc_qos_idle_trigger(core, ctx); + if (ctx->update_framerate) + mfc_qos_get_weighted_mb(ctx, ctx->rt); + if (update_idle || ctx->update_bitrate || ctx->update_framerate) + mfc_qos_on(core, ctx); + if (IS_MULTI_MODE(ctx)) { + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no sub core\n"); + goto release_corelock; + } - if (!(core->fw.status & MFC_CTX_ALLOC)) { - ret = mfc_alloc_common_context(core); - if (ret) - goto err_inst_init; + update_idle = mfc_qos_idle_trigger(core, ctx); + if (update_idle || ctx->update_bitrate || ctx->update_framerate) + mfc_qos_on(core, ctx); } + + if (ctx->update_framerate) + mfc_rm_load_balancing(ctx, MFC_RM_LOAD_ADD); + + ctx->update_bitrate = false; + break; + default: + mfc_ctx_err("[RM] not supported QoS control type: %#x\n", + qos_control); } - mfc_change_op_mode(ctx, MFC_OP_SINGLE); - ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; - if (ctx->type == MFCINST_DECODER) - ctx->op_core_num[MFC_CORE_MAIN] = MFC_DEC_DEFAULT_CORE; - else - ctx->op_core_num[MFC_CORE_MAIN] = MFC_ENC_DEFAULT_CORE; +release_corelock: + mfc_release_corelock_ctx(ctx); +} + +int mfc_rm_query_state(struct mfc_ctx *ctx, enum mfc_inst_state_query query, + enum mfc_inst_state state) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + enum mfc_inst_state maincore_state = MFCINST_FREE; + enum mfc_inst_state subcore_state = MFCINST_FREE; + int maincore_condition = 0, subcore_condition = 0; + int ret = 0; + + mfc_get_corelock_ctx(ctx); core = mfc_get_main_core(dev, ctx); if (!core) { - mfc_ctx_err("[RM] There is no main core\n"); - ret = -EINVAL; - goto err_inst_init; + mfc_ctx_debug(3, "[RM] There is no main core\n"); + goto err_query_state; } - mfc_ctx_debug(2, "[RM] init instance core-%d\n", - ctx->op_core_num[MFC_CORE_MAIN]); - ret = core->core_ops->instance_init(core, ctx); - if (ret) { - ctx->op_core_num[MFC_CORE_MAIN] = MFC_CORE_INVALID; - mfc_ctx_err("[RM] Failed to init\n"); + core_ctx = core->core_ctx[ctx->num]; + maincore_state = core_ctx->state; + + if (IS_MULTI_MODE(ctx)) { + core = mfc_get_sub_core(dev, ctx); + if (!core) { + mfc_ctx_debug(4, "[RM] There is no sub core\n"); + goto err_query_state; + } + + core_ctx = core->core_ctx[ctx->num]; + if (!core_ctx) { + mfc_ctx_debug(4, "[RM] There is no sub core_ctx\n"); + goto err_query_state; + } + subcore_state = core_ctx->state; } -err_inst_init: - mfc_release_corelock_ctx(ctx); + switch (query) { + case EQUAL: + if (maincore_state == state) + maincore_condition = 1; + if (subcore_state == state) + subcore_condition = 1; + break; + case BIGGER: + if (maincore_state > state) + maincore_condition = 1; + if (subcore_state > state) + subcore_condition = 1; + break; + case SMALLER: + if (maincore_state < state) + maincore_condition = 1; + if (subcore_state < state) + subcore_condition = 1; + break; + case EQUAL_BIGGER: + if (maincore_state >= state) + maincore_condition = 1; + if (subcore_state >= state) + subcore_condition = 1; + break; + case EQUAL_SMALLER: + if (maincore_state <= state) + maincore_condition = 1; + if (subcore_state <= state) + subcore_condition = 1; + break; + case EQUAL_OR: + if (maincore_state == state || subcore_state == state) { + maincore_condition = 1; + subcore_condition = 1; + } + break; + default: + mfc_err("[RM] not supported state query type: %d\n", query); + goto err_query_state; + } - mfc_ctx_debug_leave(); + if (IS_MULTI_MODE(ctx)) { + if (maincore_condition && subcore_condition) + ret = 1; + else + mfc_debug(2, "[RM] multi core main core state: %d, sub core state: %d\n", + maincore_state, subcore_state); + } else { + if (maincore_condition) + ret = 1; + else + mfc_debug(2, "[RM] single core main core state: %d\n", + maincore_state); + } + +err_query_state: + mfc_release_corelock_ctx(ctx); return ret; } -int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx) +static int __mfc_rm_check_real_time_resource(struct mfc_ctx *ctx) { - struct mfc_core *core = NULL, *subcore; - int i, ret = 0; + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx *tmp_ctx; + struct mfc_ctx *rt_ctx[MFC_NUM_CONTEXTS]; + unsigned long flags; + unsigned long fix_rt_mb[MFC_NUM_CORE], all_rt_mb = 0; + unsigned long fix_rt_mb_sum = 0, max_avail_mb = 0; + int i, cnt = 0; - mfc_ctx_debug_enter(); + for (i = 0; i < dev->num_core; i++) { + max_avail_mb += dev->core[i]->core_pdata->max_mb; + fix_rt_mb[i] = 0; + } - mfc_get_corelock_ctx(ctx); + /* 1. Calculation of RT instance load in operation */ + spin_lock_irqsave(&dev->ctx_list_lock, flags); + list_for_each_entry(tmp_ctx, &dev->ctx_list, list) { + if (tmp_ctx == ctx) { + mfc_ctx_debug(4, "[RT] already reserved resource\n"); + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); + return 0; + } + if (tmp_ctx->rt != MFC_RT) { + mfc_ctx_debug(4, "[RM][c:%d] This is not RT (%d)\n", + tmp_ctx->num, tmp_ctx->rt); + continue; + } + if (tmp_ctx->idle_mode == MFC_IDLE_MODE_IDLE) { + mfc_ctx_debug(3, "[RT][MFCIDLE] idle ctx[%d] excluded\n", tmp_ctx->num); + continue; + } + /* + * - fix_rt_mb[]: RT MB that must operate in a fixed core + * - all_rt_mb: RT MB that operable in all cores + */ + if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_0 || + tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_1) + fix_rt_mb[tmp_ctx->op_core_type] += tmp_ctx->weighted_mb; + else + all_rt_mb += tmp_ctx->weighted_mb; + rt_ctx[cnt++] = tmp_ctx; + mfc_show_ctx_info(tmp_ctx); + } + spin_unlock_irqrestore(&dev->ctx_list_lock, flags); - /* reset original stream mode */ - mutex_lock(&ctx->op_mode_mutex); - if (IS_SWITCH_SINGLE_MODE(ctx)) { - mfc_rm_set_core_num(ctx, MFC_DEC_DEFAULT_CORE); - mfc_change_op_mode(ctx, ctx->stream_op_mode); + mfc_ctx_debug(3, "[RM] ===== RT MB in operation\n"); + for (i = 0; i < dev->num_core; i++) { + fix_rt_mb_sum += fix_rt_mb[i]; + mfc_ctx_debug(3, "[RM] core%d RT MB %lu / %u\n", + i, fix_rt_mb[i], dev->core[i]->core_pdata->max_mb); } - mutex_unlock(&ctx->op_mode_mutex); + mfc_ctx_debug(3, "[RM] other RT MB %lu / %lu\n", all_rt_mb, max_avail_mb - fix_rt_mb_sum); - if (IS_TWO_MODE1(ctx)) { - subcore = mfc_get_sub_core(dev, ctx); - if (!subcore) - mfc_ctx_err("[RM] There is no sub core for clock off\n"); - else - mfc_core_pm_clock_off(subcore, 0); + /* 2. Adds current instance load */ + if (ctx->op_core_type == MFC_OP_CORE_FIXED_0 || + ctx->op_core_type == MFC_OP_CORE_FIXED_1) { + fix_rt_mb[ctx->op_core_type] += ctx->weighted_mb; + } else { + /* Only one instance can be operated in multi core mode */ + if (dev->num_inst == 1 && + (ctx->type == MFCINST_DECODER && IS_MULTI_MODE_RES(ctx))) { + for (i = 0; i < dev->num_core; i++) + fix_rt_mb[i] += (ctx->weighted_mb / 2); + } else { + all_rt_mb += ctx->weighted_mb; + } } - for (i = (MFC_CORE_TYPE_NUM - 1); i >= 0; i--) { - if (ctx->op_core_num[i] == MFC_CORE_INVALID) + mfc_ctx_debug(2, "[RM] ===== RT MB after adding curr load %lu\n", ctx->weighted_mb); + fix_rt_mb_sum = 0; + for (i = 0; i < dev->num_core; i++) { + fix_rt_mb_sum += fix_rt_mb[i]; + mfc_ctx_debug(2, "[RM] core%d RT MB %lu / %u\n", + i, fix_rt_mb[i], dev->core[i]->core_pdata->max_mb); + } + mfc_ctx_debug(3, "[RM] other RT MB %lu / %lu\n", all_rt_mb, max_avail_mb - fix_rt_mb_sum); + + /* 3. Check whether the current RT ctx resource reservation */ + for (i = 0; i < dev->num_core; i++) { + if (fix_rt_mb[i] > dev->core[i]->core_pdata->max_mb) { + mfc_ctx_info("[RM] core%d RT resource is full for %lu (mb %lu / %u)\n", + i, ctx->weighted_mb, fix_rt_mb[i], + dev->core[i]->core_pdata->max_mb); + goto fail_reserve; + } + } + + if ((all_rt_mb + fix_rt_mb_sum) > max_avail_mb) { + mfc_ctx_info("[RM] RT resource is full for %lu, fixed %lu + others %lu (mb %lu / %lu)\n", + ctx->weighted_mb, fix_rt_mb_sum, all_rt_mb, + fix_rt_mb_sum + all_rt_mb, max_avail_mb); + goto fail_reserve; + } + + /* 4. Add reserved resource to load list */ + mfc_rm_load_balancing(ctx, MFC_RM_LOAD_ADD); + mfc_ctx_debug(2, "[RM] RT resource is reserved for %lu, fixed %lu + others %lu (mb %lu / %lu)\n", + ctx->weighted_mb, fix_rt_mb_sum, all_rt_mb, + fix_rt_mb_sum + all_rt_mb, max_avail_mb); + + return 0; + +fail_reserve: + for (i = 0; i < cnt; i++) { + if (!rt_ctx[i]) continue; + mfc_print_ctx_info(rt_ctx[i]); + } + mfc_ctx_info(":: Current instance\n"); + mfc_print_ctx_info(ctx); + return -EBUSY; +} - core = dev->core[ctx->op_core_num[i]]; - if (!core) { - mfc_ctx_err("[RM] There is no core[%d]\n", - ctx->op_core_num[i]); - ret = -EINVAL; - goto err_inst_deinit; +void mfc_rm_update_real_time(struct mfc_ctx *ctx) +{ + struct mfc_core *core; + int cur_rt, cur_prio, new_rt, new_prio, ret; + + mfc_ctx_debug_enter(); + + new_prio = ctx->user_prio; + + if (ctx->operating_framerate > 0) { + if (new_prio == 0) { + new_rt = MFC_RT; + } else if (new_prio >= 1) { + new_rt = MFC_RT_CON; + } else { + /* Undefined is handled like RT_LOW (priority 1) */ + new_prio = 1; + new_rt = MFC_RT_LOW; } + } else { + if (new_prio == 0) { + /* In case of google photo app, user sets priority 0 */ + new_prio = 1; + new_rt = MFC_RT_LOW; + } else if (new_prio >= 1) { + new_rt = MFC_NON_RT; + } else { + /* Undefined is handled like RT_LOW (priority 1) */ + new_prio = 1; + new_rt = MFC_RT_UNDEFINED; + } + } - mfc_core_debug(2, "[RM] core%d will be deinit, ctx[%d]\n", - i, ctx->num); - ret = core->core_ops->instance_deinit(core, ctx); - if (ret) - mfc_core_err("[RM] Failed to deinit\n"); + mfc_ctx_debug(2, "[PRIO] update rt: %d -> %d, operating fps: %lu, prio: %d->%d\n", + ctx->rt, new_rt, (ctx->operating_framerate / 1000), + ctx->prio, new_prio); + + mfc_qos_get_weighted_mb(ctx, new_rt); + + if (new_rt == MFC_RT) { + ret = __mfc_rm_check_real_time_resource(ctx); + if (ret) { + new_prio = 1; + mfc_ctx_debug(2, "[PRIO] RT resource is full so update prio: %d->%d\n", + ctx->prio, new_prio); + } } - clear_bit(ctx->num, &dev->multi_core_inst_bits); - mfc_change_op_mode(ctx, MFC_OP_SINGLE); - ctx->op_core_type = MFC_OP_CORE_NOT_FIXED; + if (new_rt != ctx->rt || new_prio != ctx->prio) { + cur_rt = ctx->rt; + cur_prio = ctx->prio; + core = mfc_get_main_core_lock(ctx->dev, ctx); + if (core) { + ret = core->sched->change_prio_work(core, ctx, cur_rt, + cur_prio, new_rt, new_prio); + } else { + mfc_ctx_err("[PRIO] There is no main core\n"); + ret = -EINVAL; + } + if (ret) { + ctx->prio = new_prio; + ctx->rt = new_rt; + } -err_inst_deinit: - mfc_release_corelock_ctx(ctx); + if (!IS_SINGLE_MODE(ctx)) { + core = mfc_get_sub_core_lock(ctx->dev, ctx); + if (core) + core->sched->change_prio_work(core, ctx, cur_rt, + cur_prio, new_rt, new_prio); + else + mfc_ctx_err("[PRIO] There is no sub core\n"); + } + } mfc_ctx_debug_leave(); - - return ret; } diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h index 8f9e7494057e..b73ef905718a 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h @@ -18,6 +18,40 @@ #define MFC_RM_LOAD_ADD 1 #define MFC_RM_LOAD_DELETE_UPDATE 2 +static inline struct mfc_core *mfc_get_main_core_lock(struct mfc_dev *dev, + struct mfc_ctx *ctx) +{ + struct mfc_core *core; + + mfc_get_corelock_ctx(ctx); + + if (ctx->op_core_num[MFC_CORE_MAIN] == MFC_CORE_INVALID) + core = NULL; + else + core = dev->core[ctx->op_core_num[MFC_CORE_MAIN]]; + + mfc_release_corelock_ctx(ctx); + + return core; +} + +static inline struct mfc_core *mfc_get_sub_core_lock(struct mfc_dev *dev, + struct mfc_ctx *ctx) +{ + struct mfc_core *core; + + mfc_get_corelock_ctx(ctx); + + if (ctx->op_core_num[MFC_CORE_SUB] == MFC_CORE_INVALID) + core = NULL; + else + core = dev->core[ctx->op_core_num[MFC_CORE_SUB]]; + + mfc_release_corelock_ctx(ctx); + + return core; +} + static inline struct mfc_core *mfc_get_main_core(struct mfc_dev *dev, struct mfc_ctx *ctx) { @@ -50,7 +84,25 @@ static inline void mfc_rm_set_core_num(struct mfc_ctx *ctx, int main_core_num) ctx->op_core_num[MFC_CORE_SUB]); } +/* load balancing */ +void mfc_rm_migration_worker(struct work_struct *work); +void mfc_rm_load_balancing(struct mfc_ctx *ctx, int load_add); + /* core ops */ int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx); int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx); +int mfc_rm_instance_open(struct mfc_dev *dev, struct mfc_ctx *ctx); +void mfc_rm_instance_dec_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, + unsigned int type); +int mfc_rm_subcore_seq_start(struct mfc_dev *dev, struct mfc_ctx *ctx); +int mfc_rm_instance_setup(struct mfc_dev *dev, struct mfc_ctx *ctx); +void mfc_rm_request_work(struct mfc_dev *dev, enum mfc_request_work work, + struct mfc_ctx *ctx); + +/* utils */ +void mfc_rm_qos_control(struct mfc_ctx *ctx, enum mfc_qos_control qos_control); +int mfc_rm_query_state(struct mfc_ctx *ctx, enum mfc_inst_state_query query, + enum mfc_inst_state state); + +void mfc_rm_update_real_time(struct mfc_ctx *ctx); #endif /* __MFC_RM_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035628epcas5p1c0ebecf84b6b9c17aa291b097e411df0@epcas5p1.samsung.com>]
* [PATCH 16/29] media: mfc: Enhance HW‑lock handling, scheduling and error recovery [not found] ` <CGME20250930035628epcas5p1c0ebecf84b6b9c17aa291b097e411df0@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Enable HW‑lock migration across cores and centralize lock acquisition for better load‑balancing and dynamic resolution. - Refactor decoder run‑path helpers to streamline init, per‑frame, and final‑frame processing with dynamic DPB management. - Add IRQ‑level lock handler that deals with pre‑empted contexts, waiting queues, QoS updates and work scheduling, reducing race conditions. - Expand QoS tracking and black‑bar detection with detailed debug output. - Consolidate error handling into a dedicated ISR‑invoked path, improving recovery reliability and logging. - Update headers/comments and add missing declarations for new helpers. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/mfc_core_hwlock.c | 364 +++++ .../samsung/exynos-mfc/mfc_core_hwlock.h | 8 + .../samsung/exynos-mfc/mfc_core_isr.c | 1353 ++++++++++++++++- .../samsung/exynos-mfc/mfc_core_isr.h | 3 + .../samsung/exynos-mfc/mfc_core_run.c | 145 ++ .../samsung/exynos-mfc/mfc_core_run.h | 4 + .../platform/samsung/exynos-mfc/mfc_rm.c | 1 + 7 files changed, 1877 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c index 4de836543e82..0b594429fd59 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c @@ -19,8 +19,10 @@ #include "mfc_core_cmd.h" #include "mfc_core_hw_reg_api.h" +#include "base/mfc_queue.h" #include "base/mfc_utils.h" #include "base/mfc_sched.h" +#include "base/mfc_qos.h" static inline void __mfc_print_hwlock(struct mfc_core *core) { @@ -291,6 +293,221 @@ void mfc_core_release_hwlock_ctx(struct mfc_core_ctx *core_ctx) spin_unlock_irqrestore(&core->hwlock.lock, flags); } +void mfc_core_move_hwlock_ctx(struct mfc_core *to_core, struct mfc_core *from_core, + struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_listable_wq *listable_wq; + bool is_move = false; + + if (from_core->hwlock.bits & (1UL << core_ctx->num)) + is_move = true; + + list_for_each_entry(listable_wq, &from_core->hwlock.waiting_list, list) { + if (!listable_wq->core_ctx) + continue; + + if (listable_wq->core_ctx->num == core_ctx->num) + is_move = true; + } + + if (is_move) { + mfc_debug(2, "There is a waiting module to moving core%d\n", + from_core->id); + MFC_TRACE_RM("[c:%d] hwlock wait in moving core%d\n", + ctx->num, from_core->id); + /* remove waiting list from from_core->hwlock */ + core_ctx->core = from_core; + __mfc_remove_listable_wq_ctx(core_ctx); + + /* add waiting list to to_core->hwlock */ + core_ctx->core = to_core; + list_add_tail(&core_ctx->hwlock_wq.list, &to_core->hwlock.waiting_list); + to_core->hwlock.wl_count++; + to_core->hwlock.owned_by_irq = 1; + mfc_info("hwlock waiting module moved MFC%d -> MFC%d\n", + from_core->id, to_core->id); + MFC_TRACE_RM("[c:%d] hwlock module move %d -> %d\n", + ctx->num, from_core->id, to_core->id); + } +} + +static inline void __mfc_yield_hwlock(struct mfc_core *core, + struct mfc_core_ctx *core_ctx) +{ + mfc_core_release_hwlock_ctx(core_ctx); + + /* Trigger again if other instance's work is waiting */ + if (core->sched->is_work(core)) + core->sched->queue_work(core); +} + +/* + * Should be called with hwlock.lock + */ +static inline void __mfc_transfer_hwlock_ctx_protected(struct mfc_core *core, + int ctx_index) +{ + core->hwlock.dev = 0; + core->hwlock.bits = 0; + set_bit(ctx_index, &core->hwlock.bits); +} + +/* + * Should be called with hwlock.lock + * + * Return value description + * >=0: succeeded to get hwlock_bit for the context, index of new context + * -1, -EINVAL: failed to get hwlock_bit for a context + */ +static int __mfc_try_to_get_new_ctx_protected(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + int ret = 0; + int index; + struct mfc_ctx *new_ctx; + + if (core->shutdown) { + mfc_core_info("Couldn't lock HW. Shutdown was called\n"); + return -EINVAL; + } + + if (core->sleep) { + mfc_core_info("Couldn't lock HW. Sleep was called\n"); + return -EINVAL; + } + + /* Check whether hardware is not running */ + if (core->hwlock.bits != 0 || core->hwlock.dev != 0) { + /* This is perfectly ok, the scheduled ctx should wait */ + mfc_core_debug(2, "Couldn't lock HW\n"); + return -1; + } + + /* Choose the context to run */ + index = core->sched->pick_next_work(core); + if (index < 0) { + /* This is perfectly ok, the scheduled ctx should wait + * No contexts to run + */ + mfc_core_debug(2, "No ctx is scheduled to be run\n"); + ret = -1; + return ret; + } + + new_ctx = dev->ctx[index]; + if (!new_ctx) { + mfc_core_err("no mfc context to run\n"); + ret = -1; + return ret; + } + + set_bit(new_ctx->num, &core->hwlock.bits); + ret = index; + + return ret; +} + +/* + * Should be called without hwlock holding + * + * Try to run an operation on hardware + */ +void mfc_core_try_run(struct mfc_core *core) +{ + int new_ctx_index; + int ret; + unsigned long flags; + + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't run HW. It's Error state\n"); + return; + } + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + new_ctx_index = __mfc_try_to_get_new_ctx_protected(core); + if (new_ctx_index < 0) { + mfc_core_debug(2, "Failed to get new context to run\n"); + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); + return; + } + + core->hwlock.owned_by_irq = 1; + + __mfc_print_hwlock(core); + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + ret = mfc_core_just_run(core, new_ctx_index); + if (ret) + __mfc_yield_hwlock(core, core->core_ctx[new_ctx_index]); +} + +static int __mfc_just_run_dec(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + + switch (core_ctx->state) { + case MFCINST_FINISHING: + ret = mfc_core_run_dec_last_frames(core, ctx); + break; + case MFCINST_RUNNING: + ret = mfc_core_run_dec_frame(core, ctx); + break; + case MFCINST_INIT: + mfc_core_cmd_open_inst(core, ctx); + break; + case MFCINST_RETURN_INST: + ret = mfc_core_cmd_close_inst(core, ctx); + break; + case MFCINST_GOT_INST: + ret = mfc_core_run_dec_init(core, ctx); + break; + case MFCINST_HEAD_PARSED: + if (core_ctx->codec_buffer_allocated == 0) { + ctx->clear_work_bit = 1; + mfc_err("codec buffer is not allocated\n"); + ret = -EAGAIN; + break; + } + if (ctx->wait_state != WAIT_NONE) { + mfc_err("wait_state(%d) is not ready\n", ctx->wait_state); + ret = -EAGAIN; + break; + } + ret = mfc_core_cmd_dec_init_buffers(core, ctx); + break; + case MFCINST_RES_CHANGE_INIT: + ret = mfc_core_run_dec_last_frames(core, ctx); + break; + case MFCINST_RES_CHANGE_FLUSH: + ret = mfc_core_run_dec_last_frames(core, ctx); + break; + case MFCINST_RES_CHANGE_END: + mfc_debug(2, "[DRC] Finished remaining frames after resolution change\n"); + ctx->capture_state = QUEUE_FREE; + mfc_debug(2, "[DRC] Will re-init the codec\n"); + ret = mfc_core_run_dec_init(core, ctx); + break; + case MFCINST_DPB_FLUSHING: + mfc_core_cmd_dpb_flush(core, ctx); + break; + case MFCINST_MOVE_INST: + mfc_core_cmd_move_inst(core, ctx); + break; + default: + mfc_info("can't try command(decoder just_run), state : %d\n", + core_ctx->state); + ret = -EAGAIN; + } + + return ret; +} + /* Run an operation on hardware */ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) { @@ -321,6 +538,12 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) core->next_ctx_idx = -1; } + /* Got context to run in ctx */ + mfc_debug(2, "src: %d(ready: %d), dst: %d, state: %d, dpb_count = %d\n", + mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + core_ctx->state, ctx->dpb_count); mfc_debug(2, "core_ctx->state = %d\n", core_ctx->state); /* Last frame has already been sent to MFC * Now obtaining frames from MFC buffer @@ -332,5 +555,146 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) else core->continue_clock_on = false; + if (ctx->type == MFCINST_DECODER) { + ret = __mfc_just_run_dec(core, ctx); + } else { + mfc_err("invalid context type: %d\n", ctx->type); + ret = -EAGAIN; + } + + if (ret) { + /* + * Clear any reserved F/W cache flush for next ctx, + * as this will be newly decided in Prediction code. + */ + core->cache_flush_flag = 0; + core->last_cmd_has_cache_flush = 0; + + /* + * Check again the ctx condition and clear work bits + * if ctx is not available. + */ + if (core->sched->dequeue_work(core, core_ctx) == 0) + ctx->clear_work_bit = 0; + if (ctx->clear_work_bit) { + core->sched->clear_work(core, core_ctx); + ctx->clear_work_bit = 0; + } + + mfc_core_pm_clock_off(core, 1); + } + return ret; } + +void mfc_core_hwlock_handler_irq(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int new_ctx_index; + unsigned long flags; + int ret, need_butler = 0; + + if (core->state == MFCCORE_ERROR) { + mfc_info("[MSR] Couldn't lock HW. It's Error state\n"); + return; + } + + spin_lock_irqsave(&core->hwlock.lock, flags); + __mfc_print_hwlock(core); + + /* For handling DRC, when state is RES_CHANGE_INIT or RES_CHANGE_FLUSH, + * we need to make need_butler = 1. Then, rm_request_work will be called. + */ + if ((IS_MULTI_MODE(ctx) && + (core_ctx->state == MFCINST_RUNNING || + core_ctx->state == MFCINST_RES_CHANGE_INIT)) || + (ctx->handle_drc_multi_mode && + (core_ctx->state == MFCINST_RES_CHANGE_FLUSH || + core_ctx->state == MFCINST_RES_CHANGE_FLUSH_FINISHED))) + need_butler = 1; + + if (core->hwlock.owned_by_irq) { + if (core->preempt_core_ctx > MFC_NO_INSTANCE_SET) { + mfc_debug(2, "There is a preempt_core_ctx\n"); + core->continue_clock_on = true; + mfc_wake_up_core_ctx(core_ctx, reason, err); + new_ctx_index = core->preempt_core_ctx; + mfc_debug(2, "preempt_core_ctx is : %d\n", new_ctx_index); + __mfc_transfer_hwlock_ctx_protected(core, new_ctx_index); + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + ret = mfc_core_just_run(core, new_ctx_index); + if (ret) { + core->continue_clock_on = false; + __mfc_yield_hwlock(core, core->core_ctx[new_ctx_index]); + } + } else if (!list_empty(&core->hwlock.waiting_list)) { + mfc_debug(2, "There is a waiting module for hwlock\n"); + core->continue_clock_on = false; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + mfc_core_pm_clock_off(core, 1); + mfc_wake_up_core_ctx(core_ctx, reason, err); + mfc_core_release_hwlock_ctx(core_ctx); + core->sched->queue_work(core); + } else { + mfc_debug(2, "No preempt_ctx and no waiting module\n"); + new_ctx_index = core->sched->pick_next_work(core); + if (new_ctx_index < 0) { + mfc_debug(2, "No ctx to run\n"); + /* No contexts to run */ + core->continue_clock_on = false; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + mfc_core_pm_clock_off(core, 1); + mfc_wake_up_core_ctx(core_ctx, reason, err); + mfc_core_release_hwlock_ctx(core_ctx); + core->sched->queue_work(core); + } else { + mfc_debug(2, "There is a ctx to run\n"); + core->continue_clock_on = true; + mfc_wake_up_core_ctx(core_ctx, reason, err); + + /* If cache flush command is needed or there is OTF handle, + * handler should stop + */ + if (!need_butler) { + mfc_debug(2, "Work to do successively (next ctx: %d)\n", + new_ctx_index); + __mfc_transfer_hwlock_ctx_protected(core, new_ctx_index); + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + ret = mfc_core_just_run(core, new_ctx_index); + if (ret) { + core->continue_clock_on = false; + __mfc_yield_hwlock(core, + core->core_ctx[new_ctx_index]); + } + } else { + spin_unlock_irqrestore(&core->hwlock.lock, flags); + mfc_core_release_hwlock_ctx(core_ctx); + } + } + } + } else { + mfc_debug(2, "hwlock is NOT owned by irq\n"); + core->continue_clock_on = false; + + spin_unlock_irqrestore(&core->hwlock.lock, flags); + + mfc_core_pm_clock_off(core, 1); + mfc_wake_up_core_ctx(core_ctx, reason, err); + core->sched->queue_work(core); + } + + if (need_butler) + queue_work(core->dev->butler_wq, &core->dev->butler_work); + + __mfc_print_hwlock(core); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h index 35f34f306d7d..156809eafede 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h @@ -68,5 +68,13 @@ int mfc_core_get_hwlock_ctx(struct mfc_core_ctx *core_ctx); void mfc_core_release_hwlock_dev(struct mfc_core *core); void mfc_core_release_hwlock_ctx(struct mfc_core_ctx *core_ctx); + +void mfc_core_move_hwlock_ctx(struct mfc_core *to_core, struct mfc_core *from_core, + struct mfc_core_ctx *core_ctx); + +void mfc_core_try_run(struct mfc_core *core); int mfc_core_just_run(struct mfc_core *core, int new_ctx_index); +void mfc_core_hwlock_handler_irq(struct mfc_core *core, struct mfc_ctx *ctx, + unsigned int reason, unsigned int err); + #endif /* __MFC_CORE_HWLOCK_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c index 4c6f531ffc02..94cc3c4dfdc5 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c @@ -18,7 +18,38 @@ #include "mfc_core_hw_reg_api.h" #include "mfc_core_reg_api.h" +#include "base/mfc_rate_calculate.h" +#include "base/mfc_qos.h" + +#include "base/mfc_queue.h" #include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" + +static inline enum vb2_buffer_state __mfc_get_buf_state(unsigned int err) +{ + switch (err) { + case MFC_REG_ERR_NO_KEY_FRAME: + case MFC_REG_ERR_NO_VALID_SEQ_HDR: + case MFC_REG_ERR_NO_VALID_PIC_HDR: + case MFC_REG_ERR_NO_VALID_REF_FOR_SKIP: + case MFC_REG_ERR_UNSUPPORTED_FEATURE: + case MFC_REG_ERR_UNSUPPORTED_RESOLUTION: + case MFC_REG_ERR_HEADER_NOT_FOUND: + case MFC_REG_ERR_INVALID_NAL_TYPE: + case MFC_REG_ERR_SEQUENCE_HEADER_ERROR: + case MFC_REG_ERR_PICTURE_HEADER_ERROR: + case MFC_REG_ERR_SLICE_HEADER_ERROR: + case MFC_REG_ERR_MISSING_FIRST_FIELD: + case MFC_REG_ERR_SLICE_COUNT_IS_OVER_ASO: + case MFC_REG_ERR_TILE_HEADER_ERROR: + case MFC_REG_ERR_MAX_VIEW_NUM_OVER: + case MFC_REG_ERR_MFC_TIMEOUT: + return VB2_BUF_STATE_ERROR; + default: + return VB2_BUF_STATE_DONE; + } +} static inline int __mfc_core_is_err_condition(unsigned int err) { @@ -35,10 +66,1216 @@ static inline int __mfc_core_is_err_condition(unsigned int err) } } +static inline void mfc_handle_force_change_status(struct mfc_core_ctx *core_ctx) +{ + if (core_ctx->state != MFCINST_ABORT && + core_ctx->state != MFCINST_HEAD_PARSED && + core_ctx->state != MFCINST_RES_CHANGE_FLUSH && + core_ctx->state != MFCINST_RES_CHANGE_FLUSH_FINISHED) + mfc_change_state(core_ctx, MFCINST_RUNNING); +} + +static void __mfc_handle_black_bar_info(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct v4l2_rect new_black_bar; + int black_bar_info; + struct mfc_dec *dec = ctx->dec_priv; + + black_bar_info = mfc_core_get_black_bar_detection(); + mfc_ctx_debug(3, "[BLACKBAR] type: %#x\n", black_bar_info); + + if (black_bar_info == MFC_REG_DISP_STATUS_BLACK_BAR) { + new_black_bar.left = mfc_core_get_black_bar_pos_x(); + new_black_bar.top = mfc_core_get_black_bar_pos_y(); + new_black_bar.width = mfc_core_get_black_bar_image_w(); + new_black_bar.height = mfc_core_get_black_bar_image_h(); + } else if (black_bar_info == MFC_REG_DISP_STATUS_BLACK_SCREEN) { + new_black_bar.left = -1; + new_black_bar.top = -1; + new_black_bar.width = ctx->img_width; + new_black_bar.height = ctx->img_height; + } else if (black_bar_info == MFC_REG_DISP_STATUS_NOT_DETECTED) { + new_black_bar.left = 0; + new_black_bar.top = 0; + new_black_bar.width = ctx->img_width; + new_black_bar.height = ctx->img_height; + } else { + mfc_ctx_err("[BLACKBAR] Not supported type: %#x\n", black_bar_info); + dec->black_bar_updated = 0; + return; + } + + if (new_black_bar.left == dec->black_bar.left && + new_black_bar.top == dec->black_bar.top && + new_black_bar.width == dec->black_bar.width && + new_black_bar.height == dec->black_bar.height) { + mfc_ctx_debug(4, "[BLACKBAR] information was not changed\n"); + dec->black_bar_updated = 0; + return; + } + + dec->black_bar = new_black_bar; + dec->black_bar_updated = 1; +} + +static unsigned int __mfc_handle_frame_field(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned int interlace_type = 0, is_interlace = 0; + unsigned int field; + + if (IS_H264_DEC(ctx)) { + dec->is_mbaff = mfc_core_is_mbaff_picture(); + is_interlace = mfc_core_is_interlace_picture(); + } + + if (is_interlace) { + interlace_type = mfc_core_get_interlace_type(); + if (interlace_type) + field = V4L2_FIELD_INTERLACED_TB; + else + field = V4L2_FIELD_INTERLACED_BT; + } else if (dec->is_mbaff) { + field = V4L2_FIELD_INTERLACED_TB; + } else { + field = V4L2_FIELD_NONE; + } + + if (is_interlace || dec->is_mbaff) + mfc_ctx_debug(2, "[INTERLACE] is_interlace: %d (type : %d), is_mbaff: %d, field: %#x\n", + is_interlace, interlace_type, dec->is_mbaff, field); + + return field; +} + +static struct mfc_buf *__mfc_handle_last_frame(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *dst_mb; + int index, i; + + mfc_ctx_debug(2, "DQ empty DPB with stored tag\n"); + + dst_mb = mfc_get_del_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) { + mfc_ctx_err("there is no dst buffer for EOS tag\n"); + return NULL; + } + + mfc_ctx_debug(2, "Cleaning up buffer: [%d][%d]\n", + dst_mb->vb.vb2_buf.index, dst_mb->dpb_index); + + index = dst_mb->vb.vb2_buf.index; + + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, i, 0); + + dst_mb->vb.sequence = (++ctx->sequence); + dst_mb->vb.field = __mfc_handle_frame_field(core, ctx); + mfc_clear_mb_flag(dst_mb); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, ctx->stored_tag); + + mutex_lock(&dec->dpb_mutex); + + index = dst_mb->dpb_index; + dec->dpb[index].queued = 0; + clear_bit(index, &dec->queued_dpb); + dec->display_index = dst_mb->dpb_index; + + mutex_unlock(&dec->dpb_mutex); + mfc_ctx_debug(2, "[DPB] Cleand up index [%d][%d], used_flag = %#lx, queued = %#lx\n", + dst_mb->vb.vb2_buf.index, dst_mb->dpb_index, + dec->dynamic_used, dec->queued_dpb); + + return dst_mb; +} + +static void __mfc_handle_frame_unused_output(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *mfc_buf = NULL; + unsigned int index; + + while (1) { + mfc_buf = mfc_get_del_buf(ctx, &ctx->err_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!mfc_buf) + break; + + index = mfc_buf->vb.vb2_buf.index; + + mfc_clear_mb_flag(mfc_buf); + mfc_buf->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_ERROR); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, + MFC_REG_DEC_STATUS_DECODING_ONLY); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, UNUSED_TAG); + + dec->ref_buf[dec->refcnt].fd[0] = mfc_buf->vb.vb2_buf.planes[0].m.fd; + dec->refcnt++; + + vb2_buffer_done(&mfc_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + mfc_ctx_debug(2, "[DPB] dst index [%d][%d] fd: %d is buffer done (not used)\n", + mfc_buf->vb.vb2_buf.index, mfc_buf->dpb_index, + mfc_buf->vb.vb2_buf.planes[0].m.fd); + } +} + +static void __mfc_handle_ref_info(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, unsigned int err) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct dec_dpb_ref_info *ref_info = NULL; + int i; + + if (!mfc_buf) { + for (i = 0; i < dec->refcnt; i++) + mfc_ctx_debug(2, "[REFINFO] Released FD = %d will update with display buffer\n", + dec->ref_buf[i].fd[0]); + return; + } + + ref_info = &dec->ref_info[mfc_buf->vb.vb2_buf.index]; + for (i = 0; i < dec->refcnt; i++) + ref_info->dpb[i].fd[0] = dec->ref_buf[i].fd[0]; + if (dec->refcnt != MFC_MAX_BUFFERS) + ref_info->dpb[i].fd[0] = MFC_INFO_INIT_FD; + dec->refcnt = 0; + + mfc_ctx_debug(2, "[DPB] dst index [%d][%d] fd: %d is buffer done\n", + mfc_buf->vb.vb2_buf.index, mfc_buf->dpb_index, + mfc_buf->vb.vb2_buf.planes[0].m.fd); + vb2_buffer_done(&mfc_buf->vb.vb2_buf, mfc_get_warn(err) ? + VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); +} + +static void __mfc_handle_frame_all_extracted(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_buf *dst_mb; + int index, i, is_first = 1; + + mfc_debug(2, "Decided to finish\n"); + ctx->sequence++; + + if (core_ctx->state == MFCINST_RES_CHANGE_FLUSH) + is_first = 0; + + while (1) { + dst_mb = mfc_get_del_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) + break; + + mfc_debug(2, "Cleaning up buffer: [%d][%d]\n", + dst_mb->vb.vb2_buf.index, dst_mb->dpb_index); + + index = dst_mb->vb.vb2_buf.index; + + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, i, 0); + + dst_mb->vb.sequence = (ctx->sequence++); + dst_mb->vb.field = __mfc_handle_frame_field(core, ctx); + mfc_clear_mb_flag(dst_mb); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + if (is_first) { + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, ctx->stored_tag); + is_first = 0; + } else { + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, DEFAULT_TAG); + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_VIDEO_H264_SEI_FP_AVAIL, 0); + } + + mutex_lock(&dec->dpb_mutex); + + index = dst_mb->dpb_index; + dec->dpb[index].queued = 0; + clear_bit(index, &dec->queued_dpb); + + mutex_unlock(&dec->dpb_mutex); + + vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + mfc_debug(2, "[DPB] Cleand up index = %d, used_flag = %#lx, queued = %#lx\n", + index, dec->dynamic_used, dec->queued_dpb); + } + + /* dequeue unused DPB */ + __mfc_handle_frame_unused_output(core, ctx); + + mfc_handle_force_change_status(core_ctx); + mfc_debug(2, "After cleanup\n"); + + mfc_cleanup_iovmm_except_used(ctx); + mfc_print_dpb_table(ctx); +} + +static void __mfc_handle_frame_copy_timestamp(struct mfc_core_ctx *core_ctx, + dma_addr_t dec_y_addr) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_buf *dst_mb, *src_mb; + + /* Get the source buffer */ + src_mb = mfc_get_buf(ctx, &core_ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!src_mb) { + mfc_err("[TS] no src buffers\n"); + return; + } + + dst_mb = mfc_find_buf(ctx, &ctx->dst_buf_queue, dec_y_addr); + if (dst_mb) + dst_mb->vb.vb2_buf.timestamp = src_mb->vb.vb2_buf.timestamp; +} + +static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int err) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_buf *dst_mb = NULL; + dma_addr_t dspl_y_addr; + unsigned int frame_type; + unsigned int dst_frame_status; + unsigned int is_video_signal_type = 0, is_colour_description = 0; + unsigned int is_content_light = 0, is_display_colour = 0; + unsigned int i, idr_flag, is_last_display; + int index; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { + is_video_signal_type = mfc_core_get_video_signal_type(); + is_colour_description = mfc_core_get_colour_description(); + } + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { + is_content_light = mfc_core_get_sei_avail_content_light(); + is_display_colour = mfc_core_get_sei_avail_mastering_display(); + } + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->black_bar) && + (dec->detect_black_bar || + core->dev->debugfs.feature_option & MFC_OPTION_BLACK_BAR_ENABLE)) + __mfc_handle_black_bar_info(core, ctx); + else + dec->black_bar_updated = 0; + + if (dec->immediate_display == 1) { + dspl_y_addr = mfc_core_get_dec_y_addr(); + frame_type = mfc_core_get_dec_frame_type(); + idr_flag = mfc_core_get_dec_idr_flag(); + } else { + dspl_y_addr = mfc_core_get_disp_y_addr(); + frame_type = mfc_core_get_disp_frame_type(); + idr_flag = mfc_core_get_disp_idr_flag(); + } + + is_last_display = mfc_core_get_last_display(); + + /* If multi_view_enable(MV-HEVC), buffer must not be delete at the irq of main_view. + * Because, buffer will be reused for sub_view. + */ + if (!ctx->multi_view_enable || ctx->select_view_irq == MFC_VIEW_ID_SUB) { + dst_mb = mfc_find_del_buf(ctx, &ctx->dst_buf_queue, dspl_y_addr); + } else { + dst_mb = mfc_find_buf(ctx, &ctx->dst_buf_queue, dspl_y_addr); + mfc_ctx_debug(2, "not delete dst_mb to reuse for VIEW_1\n"); + } + + if (dst_mb) { + index = dst_mb->vb.vb2_buf.index; + /* Check if this is the buffer we're looking for */ + mfc_ctx_debug(2, "[BUFINFO][DPB] ctx[%d] get dst index: [%d][%d], addr[0]: 0x%08llx\n", + ctx->num, index, dst_mb->dpb_index, + dst_mb->addr[0][0]); + + if (dec->crc_enable && dec->crc && + (ctx->dev->debugfs.sfr_dump & MFC_DUMP_DEC_CRC)) { + if (dec->crc_idx < SZ_1K) { + dec->crc[dec->crc_idx++] = mfc_core_get_crc_luma(); + dec->crc[dec->crc_idx++] = mfc_core_get_crc_chroma(); + } else { + mfc_ctx_debug(2, "[CRC] couldn't store CRC dump (idx: %d)\n", + dec->crc_idx); + } + } + + dst_mb->vb.sequence = ctx->sequence; + dst_mb->vb.field = __mfc_handle_frame_field(core, ctx); + + /* Set flag bits in order to inform SEI information */ + if (ctx->select_view_irq == MFC_VIEW_ID_MAIN) { + mfc_clear_mb_flag(dst_mb); + + dst_mb->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME | + V4L2_BUF_FLAG_ERROR); + + switch (frame_type) { + case MFC_REG_DISPLAY_FRAME_I: + dst_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; + if (!(CODEC_HAS_IDR(ctx) && !idr_flag)) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_SYNC_FRAME); + mfc_ctx_debug(2, "[FRAME] syncframe IDR\n"); + } + break; + case MFC_REG_DISPLAY_FRAME_P: + dst_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; + break; + case MFC_REG_DISPLAY_FRAME_B: + dst_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; + break; + default: + break; + } + } + + if ((ctx->multi_view_enable || ctx->ready_to_be_multi_view_enable) && + mfc_core_get_mvc_right_view_id() == MFC_VIEW_ID_MAIN) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_RIGHT_IS_MAIN_VIEW); + mfc_ctx_debug(2, "[MV-HEVC] Right veiw is the main view.\n"); + } + + if (is_content_light) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_HDR_CONTENT_LIGHT); + mfc_ctx_debug(2, "[HDR] content light level parsed\n"); + } + + if (is_display_colour) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_HDR_DISPLAY_COLOUR); + mfc_ctx_debug(2, "[HDR] mastering display colour parsed\n"); + } + + if (is_video_signal_type) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_HDR_VIDEO_SIGNAL_TYPE); + mfc_ctx_debug(2, "[HDR] video signal type parsed\n"); + if (is_colour_description) { + mfc_set_mb_flag(dst_mb, + MFC_FLAG_HDR_MAXTIX_COEFF); + mfc_ctx_debug(2, "[HDR] matrix coefficients parsed\n"); + mfc_set_mb_flag(dst_mb, + MFC_FLAG_HDR_COLOUR_DESC); + mfc_ctx_debug(2, "[HDR] colour description parsed\n"); + } + } + + if (dec->black_bar_updated) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_BLACKBAR_DETECT); + mfc_ctx_debug(3, "[BLACKBAR] black bar detected\n"); + } + + if (ctx->update_framerate) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_FRAMERATE_CH); + ctx->update_framerate = false; + mfc_ctx_debug(2, "[QoS] framerate changed\n"); + } + + if (is_last_display) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_LAST_FRAME); + mfc_ctx_debug(2, "[FRAME] Last display frame\n"); + } + + if (ctx->dst_fmt->mem_planes == 1) { + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, + raw->total_plane_size); + mfc_ctx_debug(5, "single plane payload: %d\n", + raw->total_plane_size); + } else { + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) { + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, + i, + raw->plane_size[i]); + } + } + + if (mfc_get_warn(err)) { + mfc_ctx_info("Warning for displayed frame: %d\n", mfc_get_warn(err)); + dst_mb->vb.flags |= V4L2_BUF_FLAG_ERROR; + } + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + if (dec->immediate_display == 1) { + dst_frame_status = mfc_core_get_dec_status(); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, + dst_frame_status); + + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, ctx->stored_tag); + + dec->immediate_display = 0; + } + + mfc_rate_update_last_framerate(ctx, dst_mb->vb.vb2_buf.timestamp); + + mutex_lock(&dec->dpb_mutex); + + dec->dpb[dst_mb->dpb_index].queued = 0; + clear_bit(dst_mb->dpb_index, &dec->queued_dpb); + dec->display_index = dst_mb->dpb_index; + + mutex_unlock(&dec->dpb_mutex); + } else { + mfc_print_dpb_queue_with_lock(core->core_ctx[ctx->num], dec); + } + + /* + * When main-view of MV-HEVC, should return NULL. + * Because, if address of dst_mb returned by this function is not NULL, + * the address will be used by other functions. + * It could cause kernel panic. + */ + if (ctx->multi_view_enable && ctx->select_view_irq == MFC_VIEW_ID_MAIN) + dst_mb = NULL; + + return dst_mb; +} + +static void __mfc_handle_released_buf(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned long prev_flag, new_released_flag, released_flag = 0; + unsigned long flag; + unsigned int released_flag_sub, released_flag_main; + int i, main_i, sub_i; + + mutex_lock(&dec->dpb_mutex); + + prev_flag = dec->dynamic_used; + dec->dynamic_used = mfc_core_get_dec_used_flag(); + released_flag = prev_flag & (~dec->dynamic_used); + mfc_ctx_debug(2, "[DPB] Used flag: old = %#lx, new = %#lx, released = %#lx, queued = %#lx\n", + prev_flag, dec->dynamic_used, released_flag, dec->queued_dpb); + + /* In the case of multi_view_enable(MV-HEVC), both main_view and sub_view must be released + * together. This is because the driver assigns dpb_index with only the lower half bit + * and maps both main_view and sub_view together. + * + * 1) The driver splits the original released_flag into released_flag_sub, + * released_flag_main. + * 2) Using the 'and' operation, it calculates the bits that can be released together + * and creates new_released_flag with the result + * 3) If there are bits that can be released alone (either main or sub), + * it uses the 'xor' operation to set dynamic_used back to 1. + */ + if (ctx->multi_view_enable) { + released_flag_sub = released_flag >> (MFC_MAX_DPBS / 2); + released_flag_main = (unsigned int)released_flag; + released_flag_sub &= released_flag_main; + new_released_flag = ((unsigned long)released_flag_sub << + (MFC_MAX_DPBS / 2)) | released_flag_sub; + dec->dynamic_used |= (new_released_flag ^ released_flag); + released_flag = new_released_flag; + } + + flag = dec->dynamic_used | released_flag; + for (i = __ffs(flag); i < MFC_MAX_DPBS;) { + if (dec->dynamic_used & (1UL << i)) { + dec->dpb[i].ref = 1; + if (dec->dpb[i].mapcnt == 0) + mfc_ctx_err("[DPB] %d index is no dpb table\n", i); + } + if (released_flag & (1UL << i)) { + dec->dpb[i].ref = 0; + + if (ctx->multi_view_enable && i >= MFC_MAX_DPBS / 2) + main_i = i - MFC_MAX_DPBS / 2; + else + main_i = i; + + if (dec->dpb[main_i].queued && (dec->dpb[i].new_fd != -1)) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[i].fd[0]; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] Queued DPB[%d] released fd: %d\n", + i, dec->dpb[i].fd[0]); + dec->dpb[i].fd[0] = dec->dpb[i].new_fd; + dec->dpb[i].new_fd = -1; + mfc_ctx_debug(3, "[REFINFO] Queued DPB[%d] reuse fd: %d\n", + i, dec->dpb[i].fd[0]); + } else if (!dec->dpb[main_i].queued) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[i].fd[0]; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] Dqueued DPB[%d] released fd: %d\n", + i, dec->dpb[i].fd[0]); + + if (dec->dpb[i].new_fd != -1) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[i].new_fd; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] Dqueued DPB[%d] released fd: %d\n", + i, dec->dpb[i].new_fd); + dec->dpb[i].new_fd = -1; + } + + /* + * Except queued buffer, + * the released DPB is deleted from dpb_table + */ + dec->dpb_table_used &= ~(1UL << i); + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, i); + } else { + mfc_ctx_debug(3, "[REFINFO] Queued DPB[%d] reuse fd: %d\n", + i, dec->dpb[i].fd[0]); + } + } + flag &= ~(1UL << i); + if (flag == 0) + break; + i = __ffs(flag); + } + + /* The displayed and not referenced buffer must be freed from dpb_table */ + if (dec->display_index >= 0) { + i = dec->display_index; + + if (!ctx->multi_view_enable) { + if (!(dec->dynamic_used & (1UL << i)) && + dec->dpb[i].mapcnt && + !dec->dpb[i].queued) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[i].fd[0]; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] display DPB[%d] released fd: %d\n", + i, dec->dpb[i].fd[0]); + dec->dpb_table_used &= ~(1UL << i); + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, i); + } + } else { + /* display_index is dpb_index of main view (view0) */ + main_i = i; + sub_i = i + MFC_MAX_DPBS / 2; + + /* Both main_view and sub_view must always be released together. */ + if (!(dec->dynamic_used & (1UL << main_i)) && dec->dpb[main_i].mapcnt && + !dec->dpb[main_i].queued && !(dec->dynamic_used & (1UL << sub_i)) && + dec->dpb[sub_i].mapcnt && !dec->dpb[sub_i].queued) { + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[main_i].fd[0]; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] display DPB[%d] released fd: %d\n", + main_i, dec->dpb[main_i].fd[0]); + dec->dpb_table_used &= ~(1UL << main_i); + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, main_i); + + dec->ref_buf[dec->refcnt].fd[0] = dec->dpb[sub_i].fd[0]; + dec->refcnt++; + mfc_ctx_debug(3, "[REFINFO] display DPB[%d] released fd: %d\n", + sub_i, dec->dpb[sub_i].fd[0]); + dec->dpb_table_used &= ~(1UL << sub_i); + mfc_put_iovmm(ctx, dec->dpb, ctx->dst_fmt->mem_planes, sub_i); + } else if (dec->dpb[main_i].mapcnt) { + if (ctx->select_view_irq == MFC_VIEW_ID_MAIN) + dec->dynamic_used |= (1UL << main_i); + else + dec->dynamic_used |= (1UL << sub_i); + } + } + + dec->display_index = -1; + } + + mfc_print_dpb_table(ctx); + + mutex_unlock(&dec->dpb_mutex); +} + +static struct mfc_buf *__mfc_handle_frame_output(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int err) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned int frame_type; + + frame_type = mfc_core_get_disp_frame_type(); + + if (!ctx->multi_view_enable || ctx->select_view_irq == MFC_VIEW_ID_SUB) + ctx->sequence++; + + if (dec->immediate_display == 1) + frame_type = mfc_core_get_dec_frame_type(); + + mfc_ctx_debug(2, "[FRAME] frame type: %d\n", frame_type); + + /* If frame is same as previous then skip and do not dequeue */ + if (frame_type == MFC_REG_DISPLAY_FRAME_NOT_CODED) + return NULL; + + /* Dequeued display buffer for user */ + return __mfc_handle_frame_output_del(core, ctx, err); +} + +static void __mfc_handle_error_state(struct mfc_ctx *ctx, struct mfc_core_ctx *core_ctx) +{ + mfc_err("[MSR] It's Error state: cleanup queue\n"); + MFC_TRACE_CORE_CTX("*** ERROR state\n"); + + mfc_change_state(core_ctx, MFCINST_ERROR); + + /* Mark all dst buffers as having an error */ + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->err_buf_queue); + /* Mark all src buffers as having an error */ + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &core_ctx->src_buf_queue); +} + +void mfc_core_handle_error(struct mfc_core *core) +{ + struct mfc_dev *dev = core->dev; + struct mfc_core_ctx *core_ctx; + int i; + + mfc_core_err("[MSR] >>>>>>>> MFC CORE is Error state <<<<<<<<\n"); + mfc_core_change_state(core, MFCCORE_ERROR); + + mutex_lock(&dev->mfc_mutex); + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (!core->core_ctx[i]) + continue; + /* TODO: need to check two core mode */ + core_ctx = core->core_ctx[i]; + __mfc_handle_error_state(core_ctx->ctx, core_ctx); + } + mutex_unlock(&dev->mfc_mutex); +} + +/* Error handling for interrupt */ +static inline void __mfc_handle_error(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int error_code) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_buf *src_mb; + unsigned int err, warn; + + err = mfc_get_err(error_code); + warn = mfc_get_err(error_code); + + if ((err >= MFC_REG_ERR_FRAME_CONCEAL && err <= MFC_REG_ERR_WARNINGS_END) || + (warn >= MFC_REG_ERR_FRAME_CONCEAL && warn <= MFC_REG_ERR_WARNINGS_END)) + mfc_info("Interrupt Warn: display: %d, decoded: %d\n", warn, err); + else + mfc_err("Interrupt Error: display: %d, decoded: %d\n", warn, err); + + /* Error recovery is dependent on the state of context */ + switch (core_ctx->state) { + case MFCINST_RES_CHANGE_END: + case MFCINST_GOT_INST: + /* This error had to happen while parsing the header */ + src_mb = mfc_get_del_buf(ctx, &core_ctx->src_buf_queue, + MFC_BUF_NO_TOUCH_USED); + if (src_mb) { + unsigned char *stream_vir = NULL; + unsigned int strm_size = 0; + + stream_vir = src_mb->vir_addr[0]; + strm_size = src_mb->vb.vb2_buf.planes[0].bytesused; + if (strm_size > 640) + strm_size = 640; + + if (stream_vir && strm_size) + print_hex_dump(KERN_ERR, "No header: ", + DUMP_PREFIX_OFFSET, 32, 4, + stream_vir, strm_size, false); + + mfc_clear_mb_flag(src_mb); + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + break; + case MFCINST_INIT: + /* This error had to happen while acquireing instance */ + case MFCINST_RETURN_INST: + /* This error had to happen while releasing instance */ + case MFCINST_DPB_FLUSHING: + /* This error had to happen while flushing DPB */ + break; + case MFCINST_HEAD_PARSED: + /* This error had to happen while setting dst buffers */ + case MFCINST_RES_CHANGE_INIT: + case MFCINST_RES_CHANGE_FLUSH: + /* This error has to happen while resolution change */ + case MFCINST_ABORT_INST: + /* This error has to happen while buffer full handling */ + case MFCINST_FINISHING: + /* It is higly probable that an error occurred + * while decoding a frame + */ + __mfc_handle_error_state(ctx, core_ctx); + break; + default: + mfc_err("Encountered an error interrupt which had not been handled\n"); + mfc_err("core_ctx->state = %d, core_ctx->inst_no = %d\n", + core_ctx->state, core_ctx->inst_no); + break; + } + + mfc_wake_up_core(core, reason, error_code); +} + +static void __mfc_handle_frame_error(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec; + struct mfc_buf *src_mb = NULL; + unsigned int index; + enum vb2_buffer_state vb2_state; + + dec = ctx->dec_priv; + if (!dec) { + mfc_err("no mfc decoder to run\n"); + return; + } + + mfc_err("Interrupt Error: %d\n", err); + + if (mfc_get_err(err) == MFC_REG_ERR_MISSING_NON_BASE_VIEW_DETECTED) + mfc_err("[MV-HEVC] %s, Reuse current main-view, skipping previous one.\n", + "MFC_REG_ERR_MISSING_NON_BASE_VIEW_DETECTED"); + else + /* Get the source buffer */ + src_mb = mfc_get_del_buf(ctx, &core_ctx->src_buf_queue, + MFC_BUF_NO_TOUCH_USED); + + if (!src_mb) { + mfc_err("no src buffers\n"); + } else { + index = src_mb->vb.vb2_buf.index; + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_recover_buf_ctrls\n"); + + mfc_ctx_debug(2, "MFC needs next buffer\n"); + dec->consumed = 0; + mfc_clear_mb_flag(src_mb); + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + vb2_state = __mfc_get_buf_state(mfc_get_err(err)); + mfc_debug(2, "[STREAM] consumed only by error (state: %d)\n", vb2_state); + vb2_buffer_done(&src_mb->vb.vb2_buf, vb2_state); + } + + if (mfc_get_err(err) == MFC_REG_ERR_UNDEFINED_EXCEPTION) + mfc_core_handle_error(core); + + mfc_debug(2, "Assesing whether this context should be run again\n"); +} + +static void __mfc_handle_frame_input(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int err) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *src_mb; + unsigned int index; + int deleted = 0; + unsigned int consumed; + + if (mfc_get_err(err) == MFC_REG_ERR_NON_PAIRED_FIELD) { + /* + * For non-paired field, the same buffer need to be + * resubmitted and the consumed stream will be 0 + */ + mfc_debug(2, "Not paired field. Running again the same buffer\n"); + return; + } + + /* Get the source buffer */ + consumed = mfc_core_get_consumed_stream(); + src_mb = mfc_get_del_if_consumed(ctx, + &core_ctx->src_buf_queue, + consumed, + STUFF_BYTE, + err, + &deleted); + if (!src_mb) { + mfc_err("no src buffers\n"); + return; + } + + index = src_mb->vb.vb2_buf.index; + mfc_debug(2, "[BUFINFO] ctx[%d] get src index: %d(%d), addr: 0x%08llx\n", + ctx->num, index, src_mb->src_index, src_mb->addr[0][0]); + + if (!deleted) { + /* Run MFC again on the same buffer */ + mfc_debug(2, "[MULTIFRAME] Running again the same buffer\n"); + + dec->consumed += consumed; + dec->has_multiframe = 1; + + MFC_TRACE_CORE_CTX("** consumed:%d, remained:%d\n", + dec->consumed, mfc_dec_get_strm_size(ctx, src_mb)); + /* Do not move src buffer to done_list */ + return; + } + + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_recover_buf_ctrls\n"); + + mfc_clear_mb_flag(src_mb); + + if (mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY && + mfc_core_get_dec_y_addr() == 0) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM] decoding only but there is no address\n"); + } + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + dec->consumed = 0; + + if (ctx->multi_view_enable && ctx->select_view == 0) + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + + vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + mfc_debug(2, "[STREAM] src index: %d(%d), addr: 0x%08llx is buffer done\n", + index, src_mb->src_index, src_mb->addr[0][0]); +} + +/* Handle frame decoding interrupt */ +static void __mfc_handle_frame(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *subcore; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + unsigned int dst_frame_status, sei_avail_frame_pack; + unsigned int res_change, need_dpb_change, need_scratch_change; + struct mfc_buf *mfc_buf = NULL; + bool qos_update = false; + int index; + + dst_frame_status = mfc_core_get_disp_status(); + res_change = mfc_core_get_res_change(); + need_dpb_change = mfc_core_get_dpb_change(); + need_scratch_change = mfc_core_get_scratch_change(); + sei_avail_frame_pack = mfc_core_get_sei_avail_frame_pack(); + + if (dec->immediate_display == 1) + dst_frame_status = mfc_core_get_dec_status(); + + mfc_debug(2, "[FRAME] frame status: %d\n", dst_frame_status); + mfc_debug(2, "[FRAME] display status: %d, type: %d, yaddr: %#llx\n", + mfc_core_get_disp_status(), + mfc_core_get_disp_frame_type(), + mfc_core_get_disp_y_addr()); + mfc_debug(2, "[FRAME] decoded status: %d, type: %d, yaddr: %#llx\n", + mfc_core_get_dec_status(), + mfc_core_get_dec_frame_type(), + mfc_core_get_dec_y_addr()); + + mfc_debug(4, "[HDR] SEI available status: 0x%08x\n", + mfc_core_get_sei_avail()); + mfc_debug(4, "[HDR] SEI content light: 0x%08x\n", + mfc_core_get_sei_content_light()); + mfc_debug(4, "[HDR] SEI luminance: 0x%08x, 0x%08x white point: 0x%08x\n", + mfc_core_get_sei_mastering0(), + mfc_core_get_sei_mastering1(), + mfc_core_get_sei_mastering2()); + mfc_debug(4, "[HDR] SEI display primaries: 0x%08x, 0x%08x, 0x%08x\n", + mfc_core_get_sei_mastering3(), + mfc_core_get_sei_mastering4(), + mfc_core_get_sei_mastering5()); + + mfc_qos_get_disp_ratio(ctx, + mfc_core_get_decoded_frame_cnt(), + mfc_core_get_display_frame_cnt()); + qos_update = mfc_qos_mb_calculate(core, + core_ctx, mfc_core_get_processing_cycle(), + mfc_core_get_dec_frame_type()); + + if (core_ctx->state == MFCINST_RES_CHANGE_INIT) + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_FLUSH); + + if (res_change) { + mfc_info("[DRC] Resolution change set to %d\n", res_change); + mutex_lock(&ctx->drc_wait_mutex); + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_INIT); + if (!IS_SINGLE_MODE(ctx)) { + ctx->handle_drc_multi_mode = 1; + if (!ctx->wait_state) { + /* The core that detects DRC must be switched to single */ + ctx->op_core_type = (core->id == MFC_OP_CORE_FIXED_0) ? + MFC_OP_CORE_FIXED_0 : MFC_OP_CORE_FIXED_1; + ctx->wait_state = WAIT_G_FMT | WAIT_STOP; + mfc_debug(2, "[2CORE][DRC] MFC-%d op_core_type: %d\n", + core->id, ctx->op_core_type); + } + mfc_debug(2, "[2CORE][DRC] wait_state: %d\n", ctx->wait_state); + } else { + ctx->handle_drc_multi_mode = 0; + ctx->wait_state = WAIT_G_FMT | WAIT_STOP; + } + mfc_debug(2, "[DRC] Decoding waiting! : %d\n", ctx->wait_state); + mutex_unlock(&ctx->drc_wait_mutex); + mfc_buf = mfc_get_buf(ctx, &core_ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (mfc_buf) { + index = mfc_buf->vb.vb2_buf.index; + call_bop(ctx, core_restore_buf_ctrls, ctx, &ctx->src_ctrls[index]); + } + return; + } + + if (need_dpb_change || need_scratch_change) { + mfc_info("[DRC] Interframe resolution changed\n"); + mutex_lock(&ctx->drc_wait_mutex); + ctx->wait_state = WAIT_G_FMT | WAIT_STOP; + mfc_core_get_img_size(core, ctx, MFC_GET_RESOL_DPB_SIZE); + dec->inter_res_change = 1; + mutex_unlock(&ctx->drc_wait_mutex); + __mfc_handle_frame_all_extracted(core, ctx); + return; + } + + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &core_ctx->src_buf_queue, 0) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + mfc_err("Queue count is zero for src and dst\n"); + goto leave_handle_frame; + } + + if (IS_H264_DEC(ctx) && sei_avail_frame_pack && + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY) { + mfc_debug(2, "Frame packing SEI exists for a frame\n"); + mfc_debug(2, "Reallocate DPBs and issue init_buffer\n"); + mutex_lock(&ctx->drc_wait_mutex); + ctx->is_dpb_realloc = 1; + mfc_change_state(core_ctx, MFCINST_HEAD_PARSED); + ctx->capture_state = QUEUE_FREE; + ctx->wait_state = WAIT_STOP; + mutex_unlock(&ctx->drc_wait_mutex); + __mfc_handle_frame_all_extracted(core, ctx); + goto leave_handle_frame; + } + + /* All frames remaining in the buffer have been extracted */ + if (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_EMPTY) { + if (core_ctx->state == MFCINST_RES_CHANGE_FLUSH) { + mfc_debug(2, "[DRC] Last frame received after resolution change\n"); + __mfc_handle_frame_all_extracted(core, ctx); + + /* In the case of 2core DRC, state must be changed at subcore deinit. */ + if (ctx->handle_drc_multi_mode) + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_FLUSH_FINISHED); + else + mfc_change_state(core_ctx, MFCINST_RES_CHANGE_END); + + if (IS_MULTI_CORE_DEVICE(dev)) + mfc_rm_load_balancing(ctx, MFC_RM_LOAD_DELETE); + + mfc_rate_reset_ts_list(&ctx->src_ts); + mfc_rate_reset_last_framerate(ctx); + mfc_rate_reset_bufq_framerate(ctx); + mfc_rate_set_framerate(ctx, DEC_DEFAULT_FPS); + mfc_qos_on(core, ctx); + + goto leave_handle_frame; + } else { + mfc_buf = __mfc_handle_last_frame(core, ctx); + } + } + + /* Detection for QoS weight */ + if (!dec->num_of_tile_over_4 && + mfc_core_get_num_of_tile() >= 4) { + dec->num_of_tile_over_4 = 1; + qos_update = true; + } + + if (qos_update) { + mfc_qos_on(core, ctx); + if (IS_TWO_MODE1(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (subcore) { + subcore->core_ctx[ctx->num]->dynamic_weight_level = + core_ctx->dynamic_weight_level; + mfc_qos_on(subcore, ctx); + } + } + } + + /* copy decoded timestamp */ + if (mfc_dec_status_decoding(dst_frame_status)) + __mfc_handle_frame_copy_timestamp(core_ctx, mfc_core_get_dec_y_addr()); + + /* Mark source buffer as complete */ + if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) + __mfc_handle_frame_input(core, ctx, err); + + /* A frame has been decoded and is in the buffer */ + if (mfc_dec_status_display(dst_frame_status)) { + ctx->select_view_irq = mfc_core_get_mvc_view_id_disp_order() % MFC_NUM_MULTI_VIEW; + mfc_buf = __mfc_handle_frame_output(core, ctx, err); + } else { + ctx->select_view_irq = mfc_core_get_mvc_view_id_dec_order() % MFC_NUM_MULTI_VIEW; + } + + /* arrangement of assigned dpb table */ + __mfc_handle_released_buf(core, ctx); + + /* dequeue unused DPB */ + __mfc_handle_frame_unused_output(core, ctx); + + /* There is display buffer for user, update reference information */ + __mfc_handle_ref_info(ctx, mfc_buf, err); + + mfc_rate_update_bufq_framerate(ctx, MFC_TS_DST_DQ); + + if (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_EMPTY) { + mfc_handle_force_change_status(core->core_ctx[ctx->num]); + mfc_debug(2, "It can be continue decoding again\n"); + } + + /* The first frame is only for decoding, + * so the select_view should only be increased at display interrupt. + */ + if (ctx->multi_view_enable && mfc_core_get_dec_y_addr()) + ctx->select_view = (ctx->select_view + 1) % MFC_NUM_MULTI_VIEW; + +leave_handle_frame: + mfc_debug(2, "Assesing whether this context should be run again\n"); +} + +static inline void __mfc_handle_done_frame(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + __mfc_handle_frame(core, ctx, reason, err); +} + +/* Handle header decoder interrupt */ +static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *src_mb; + int i, is_interlace; + unsigned int strm_size, consumed; + + if (ctx->src_fmt->fourcc != V4L2_PIX_FMT_FIMV1) { + ctx->img_width = mfc_core_get_img_width(); + ctx->img_height = mfc_core_get_img_height(); + ctx->crop_width = ctx->img_width; + ctx->crop_height = ctx->img_height; + mfc_info("[STREAM] resolution w: %d, h: %d\n", ctx->img_width, ctx->img_height); + } + + ctx->dpb_count = mfc_core_get_dpb_count(); + mfc_ctx_debug(2, "dpb_count: %d\n", ctx->dpb_count); + + ctx->scratch_buf_size = mfc_core_get_scratch_size(); + + mfc_core_dec_get_crop_info(core, ctx); + dec->mv_count = mfc_core_get_mv_count(); + + if (ctx->img_width == 0 || ctx->img_height == 0) { + mfc_err("[STREAM] wrong resolution w: %d, h: %d\n", + ctx->img_width, ctx->img_height); + } else { + is_interlace = mfc_core_is_interlace_picture(); + dec->is_mbaff = mfc_core_is_mbaff_picture(); + if (is_interlace || dec->is_mbaff) + dec->is_interlaced = 1; + mfc_debug(2, "[INTERLACE] interlace: %d, mbaff: %d\n", + is_interlace, dec->is_mbaff); + } + + for (i = 0; i < ctx->dst_fmt->num_planes; i++) { + ctx->min_dpb_size[i] = mfc_core_get_min_dpb_size(i); + mfc_debug(2, "[FRAME] min_dpb_size[%d]: %d, min_dpb_size_2bits[%d]: %d\n", + i, ctx->min_dpb_size[i], i, ctx->min_dpb_size_2bits[i]); + } + + if (IS_MULTI_CORE_DEVICE(dev) && mfc_core_get_two_core_mode()) { + if (dev->debugfs.feature_option & MFC_OPTION_MULTI_CORE_DISABLE) { + mfc_info("[2CORE] op_mode: %d stream, but multi core disable\n", + mfc_core_get_two_core_mode()); + } else { + if (dev->num_inst > 1) + mfc_debug(2, "[2CORE] multi core bits: %#lx, num inst: %d\n", + dev->multi_core_inst_bits, dev->num_inst); + ctx->stream_op_mode = mfc_core_get_two_core_mode(); + mfc_info("[2CORE] This stream need to multi core stream_op_mode(%d)\n", + ctx->stream_op_mode); + } + } + + src_mb = mfc_get_buf + (ctx, &core_ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (src_mb) { + consumed = mfc_core_get_consumed_stream(); + strm_size = mfc_dec_get_strm_size(ctx, src_mb); + mfc_debug(2, "[STREAM] header size, %d, %#x, consumed, %d, %#x\n", + strm_size, strm_size, consumed, consumed); + if ((IS_H264_DEC(ctx)) && + (consumed > 0 && strm_size > consumed)) { + dec->consumed += consumed; + mfc_debug(2, "[STREAM] there is remained bytes(%d) after header parsing\n", + (strm_size - consumed)); + } else { + dec->consumed = 0; + } + } + + dec->frame_display_delay = mfc_core_get_display_delay(); + mfc_debug(2, "[FRAME] display delay for first frame %d\n", + dec->frame_display_delay); + + mfc_change_state(core_ctx, MFCINST_HEAD_PARSED); + + return 0; +} + +static inline void __mfc_handle_nal_abort(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + mfc_change_state(core_ctx, MFCINST_ABORT); +} + irqreturn_t mfc_core_top_half_irq(int irq, void *priv) { struct mfc_core *core = priv; struct mfc_core_ctx *core_ctx; + struct mfc_ctx *ctx; unsigned int err; unsigned int reason; @@ -48,12 +1285,21 @@ irqreturn_t mfc_core_top_half_irq(int irq, void *priv) return IRQ_WAKE_THREAD; } + ctx = core_ctx->ctx; reason = mfc_core_get_int_reason(); err = mfc_core_get_int_err(); core->last_int = reason; core->last_int_time = ktime_to_timespec64(ktime_get()); + if (reason == MFC_REG_R2H_CMD_SEQ_DONE_RET || + reason == MFC_REG_R2H_CMD_INIT_BUFFERS_RET || + reason == MFC_REG_R2H_CMD_FRAME_DONE_RET) { + ctx->frame_cnt++; + /* counting QoS table portion */ + mfc_qos_set_portion(core, ctx); + } + mfc_debug(2, "[c:%d] Int reason: %d (err: %d, warn: %d)\n", core->curr_core_ctx, reason, mfc_get_err(err), mfc_get_warn(err)); MFC_TRACE_CORE_CTX("<< INT(top): %d\n", reason); @@ -78,6 +1324,83 @@ static int __mfc_irq_dev(struct mfc_core *core, unsigned int reason, unsigned in return 1; } +static int __mfc_irq_ctx(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + if ((core->dev->debugfs.feature_option & MFC_OPTION_MSR_ENABLE) && + ctx->frame_cnt == 20) { + reason = 0; + mfc_debug(2, "[MSR] Forced entry into MSR mode, it will be recovery\n"); + core->dev->debugfs.feature_option &= ~MFC_OPTION_MSR_ENABLE; + } + + switch (reason) { + case MFC_REG_R2H_CMD_ERR_RET: + /* An error has occurred */ + if (core_ctx->state == MFCINST_RUNNING || core_ctx->state == MFCINST_ABORT) { + if (mfc_get_err(err) >= MFC_REG_ERR_FRAME_CONCEAL && + mfc_get_err(err) <= MFC_REG_ERR_WARNINGS_END) + __mfc_handle_frame(core, ctx, reason, err); + else + __mfc_handle_frame_error(core, ctx, reason, err); + } else { + __mfc_handle_error(core, ctx, reason, err); + } + break; + case MFC_REG_R2H_CMD_SLICE_DONE_RET: + case MFC_REG_R2H_CMD_FIELD_DONE_RET: + case MFC_REG_R2H_CMD_FRAME_DONE_RET: + case MFC_REG_R2H_CMD_COMPLETE_SEQ_RET: + __mfc_handle_done_frame(core, ctx, reason, err); + break; + case MFC_REG_R2H_CMD_SEQ_DONE_RET: + if (ctx->type == MFCINST_DECODER) + __mfc_handle_seq_dec(core, ctx); + break; + case MFC_REG_R2H_CMD_OPEN_INSTANCE_RET: + core_ctx->inst_no = mfc_core_get_inst_no(); + mfc_change_state(core_ctx, MFCINST_GOT_INST); + break; + case MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET: + mfc_change_state(core_ctx, MFCINST_FREE); + break; + case MFC_REG_R2H_CMD_NAL_ABORT_RET: + __mfc_handle_nal_abort(core, ctx, reason); + break; + case MFC_REG_R2H_CMD_DPB_FLUSH_RET: + ctx->select_view = MFC_VIEW_ID_MAIN; + mfc_change_state(core_ctx, MFCINST_ABORT); + break; + case MFC_REG_R2H_CMD_INIT_BUFFERS_RET: + if (err != 0) { + mfc_err("INIT_BUFFERS_RET error: %d\n", err); + break; + } + + if (IS_MULTI_MODE(ctx)) + mfc_change_state(core_ctx, MFCINST_BUF_INIT_BUT_MULTI_MODE_NOT_CHECKED_YET); + else + mfc_change_state(core_ctx, MFCINST_RUNNING); + + if (ctx->type == MFCINST_DECODER) { + if (ctx->is_dpb_realloc) + ctx->is_dpb_realloc = 0; + } + break; + case MFC_REG_R2H_CMD_MOVE_INSTANCE_RET: + break; + default: + mfc_err("Unknown int reason: %d(%#x)\n", reason, reason); + mfc_core_handle_error(core); + } + + return 1; +} + /* Interrupt processing */ irqreturn_t mfc_core_irq(int irq, void *priv) { @@ -116,7 +1439,35 @@ irqreturn_t mfc_core_irq(int irq, void *priv) ret = __mfc_irq_dev(core, reason, err); if (!ret) goto irq_end; - mfc_ctx_info("not implemented context irq ctx"); + + core_ctx = core->core_ctx[core->curr_core_ctx]; + if (!core_ctx) { + mfc_core_err("no mfc context to run\n"); + mfc_core_clear_int(); + mfc_core_pm_clock_off(core, 1); + goto irq_end; + } + ctx = core_ctx->ctx; + + ret = mfc_get_core_intlock(core_ctx); + if (ret) { + mfc_core_clear_int_only(); + goto irq_end; + } + + ret = __mfc_irq_ctx(core, ctx, reason, err); + if (!ret) + goto irq_end; + + /* clean-up interrupt */ + mfc_core_clear_int(); + + mfc_release_core_intlock(core_ctx); + + if (!(core_ctx->state == MFCINST_RES_CHANGE_INIT && IS_SINGLE_MODE(ctx))) + core->sched->dequeue_work(core, core_ctx); + + mfc_core_hwlock_handler_irq(core, ctx, reason, err); irq_end: mfc_core_debug_leave(); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h index 046b20e6d4c2..16902b1537c6 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h @@ -19,4 +19,7 @@ irqreturn_t mfc_core_top_half_irq(int irq, void *priv); irqreturn_t mfc_core_irq(int irq, void *priv); + +void mfc_core_handle_error(struct mfc_core *core); + #endif /* __MFC_CORE_ISR_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c index fd7ebe95e715..118108f910e2 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c @@ -17,8 +17,10 @@ #include "mfc_core_cmd.h" #include "mfc_core_hw_reg_api.h" +#include "base/mfc_queue.h" #include "base/mfc_utils.h" #include "base/mfc_mem.h" +#include "base/mfc_qos.h" void mfc_core_run_cache_flush(struct mfc_core *core, enum mfc_do_cache_flush do_cache_flush, @@ -263,3 +265,146 @@ int mfc_core_run_wakeup(struct mfc_core *core) return ret; } + +int mfc_core_run_dec_init(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *src_mb; + unsigned int strm_size; + + /* Initializing decoding - parsing header */ + + /* Get the next source buffer */ + src_mb = mfc_get_buf(ctx, &core_ctx->src_buf_queue, MFC_BUF_SET_USED); + if (!src_mb) { + mfc_err("no src buffers\n"); + return -EAGAIN; + } + + strm_size = mfc_dec_get_strm_size(ctx, src_mb); + mfc_debug(2, "Preparing to init decoding\n"); + mfc_debug(2, "[STREAM] Header size: %d, (offset: %u, consumed: %u)\n", + strm_size, + src_mb->vb.vb2_buf.planes[0].data_offset, + dec->consumed); + + mfc_core_set_dec_stream_buffer(core, ctx, src_mb, + mfc_dec_get_strm_offset(ctx, src_mb), strm_size); + + mfc_debug(2, "[BUFINFO] Header addr: 0x%08llx\n", src_mb->addr[0][0]); + mfc_clean_core_ctx_int_flags(core->core_ctx[ctx->num]); + mfc_core_cmd_dec_seq_header(core, ctx); + + return 0; +} + +static int __mfc_check_last_frame(struct mfc_core_ctx *core_ctx, + struct mfc_buf *mfc_buf) +{ + if (mfc_check_mb_flag(mfc_buf, MFC_FLAG_LAST_FRAME)) { + mfc_debug(2, "Setting core_ctx->state to FINISHING\n"); + mfc_change_state(core_ctx, MFCINST_FINISHING); + return 1; + } + + return 0; +} + +int mfc_core_run_dec_frame(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_buf *src_mb, *dst_mb; + int last_frame = 0; + unsigned int index, src_index; + int ret; + + /* Get the next source buffer */ + if (IS_TWO_MODE2(ctx)) { + src_mb = mfc_get_buf_no_used(ctx, &core_ctx->src_buf_queue, + MFC_BUF_SET_USED); + if (!src_mb) { + mfc_debug(2, "no src buffers\n"); + return -EAGAIN; + } + } else { + src_mb = mfc_get_buf(ctx, &core_ctx->src_buf_queue, + MFC_BUF_SET_USED); + if (!src_mb) { + mfc_debug(2, "no src buffers\n"); + return -EAGAIN; + } + } + + /* Try to use the non-referenced DPB on dst-queue */ + if (dec->is_dynamic_dpb) { + dst_mb = mfc_search_for_dpb(core_ctx); + if (!dst_mb) { + src_mb->used = MFC_BUF_RESET_USED; + mfc_debug(2, "[DPB] couldn't find dst buffers\n"); + return -EAGAIN; + } + } + + index = src_mb->vb.vb2_buf.index; + src_index = src_mb->src_index; + + if (mfc_check_mb_flag(src_mb, MFC_FLAG_EMPTY_DATA)) + src_mb->vb.vb2_buf.planes[0].bytesused = 0; + + mfc_core_set_dec_stream_buffer(core, ctx, src_mb, + mfc_dec_get_strm_offset(ctx, src_mb), + mfc_dec_get_strm_size(ctx, src_mb)); + + if (call_bop(ctx, core_set_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_set_buf_ctrls\n"); + mfc_core_update_tag(core, ctx, ctx->stored_tag); + + if (dec->is_dynamic_dpb) + mfc_core_set_dynamic_dpb(core, ctx, dst_mb); + + mfc_clean_core_ctx_int_flags(core_ctx); + + last_frame = __mfc_check_last_frame(core_ctx, src_mb); + ret = mfc_core_cmd_dec_one_frame(core, ctx, last_frame, src_index); + + return ret; +} + +int mfc_core_run_dec_last_frames(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *dst_mb; + unsigned int src_index; + + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + mfc_debug(2, "no dst buffer\n"); + return -EAGAIN; + } + + /* Try to use the non-referenced DPB on dst-queue */ + if (dec->is_dynamic_dpb) { + dst_mb = mfc_search_for_dpb(core_ctx); + if (!dst_mb) { + mfc_debug(2, "[DPB] couldn't find dst buffers\n"); + return -EAGAIN; + } + } + + /* Get the next source buffer */ + mfc_get_buf(ctx, &core_ctx->src_buf_queue, MFC_BUF_SET_USED); + + /* Frames are being decoded */ + mfc_core_set_dec_stream_buffer(core, ctx, 0, 0, 0); + src_index = ctx->curr_src_index + 1; + + if (dec->is_dynamic_dpb) + mfc_core_set_dynamic_dpb(core, ctx, dst_mb); + + mfc_clean_core_ctx_int_flags(core_ctx); + mfc_core_cmd_dec_one_frame(core, ctx, 1, src_index); + + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h index 3d243dc18e15..6b9c9ef91e47 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h @@ -23,4 +23,8 @@ void mfc_core_run_deinit_hw(struct mfc_core *core); int mfc_core_run_sleep(struct mfc_core *core); int mfc_core_run_wakeup(struct mfc_core *core); + +int mfc_core_run_dec_init(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_run_dec_frame(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_run_dec_last_frames(struct mfc_core *core, struct mfc_ctx *ctx); #endif /* __MFC_CORE_RUN_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c index 0a805464fbc9..a7db47e58589 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c @@ -332,6 +332,7 @@ static int __mfc_rm_move_core_running(struct mfc_ctx *ctx, int to_core_num, int from_core->core_ctx[core_ctx->num] = 0; mfc_core_pm_clock_off(to_core, 0); + mfc_core_move_hwlock_ctx(to_core, from_core, core_ctx); mfc_core_release_hwlock_dev(subcore); mfc_core_release_hwlock_dev(maincore); -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035633epcas5p3d859613b1d1d3319ded26da626c959bc@epcas5p3.samsung.com>]
* [PATCH 17/29] media: mfc: Add VB2 decoder support [not found] ` <CGME20250930035633epcas5p3d859613b1d1d3319ded26da626c959bc@epcas5p3.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Implement VB2 queue operations for decoding (setup, buffer handling, streaming control, multi‑view and DMA direction support). - Added header exposing decoder VB2 operations to other MFC components. This introduces a full VB2 backend for video decoding, aligning the driver with standard V4L2 buffer management. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../platform/samsung/exynos-mfc/mfc_dec_vb2.c | 393 ++++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_dec_vb2.h | 19 + 3 files changed, 413 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index 19e38c886255..9127f2dc4df6 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_VIDEO_EXYNOS_MFC) := exynos_mfc.o ccflags-y += -I$(srctree)/$(src) #Dev interface layer -exynos_mfc-y += mfc.o +exynos_mfc-y += mfc.o mfc_dec_vb2.o #Dev control layer exynos_mfc-y += mfc_rm.o mfc_ctx_ctrl.o mfc_debugfs.o #Core interface layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c new file mode 100644 index 000000000000..3097a6c0bf14 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_dec_vb2.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_dec_vb2.h" + +#include "mfc_rm.h" + +#include "base/mfc_queue.h" +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" + +static int mfc_dec_queue_setup(struct vb2_queue *vq, + unsigned int *buf_count, unsigned int *plane_count, + unsigned int psize[], struct device *alloc_devs[]) +{ + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_raw_info *raw; + int i, offset; + + mfc_ctx_debug_enter(); + + raw = &ctx->raw_buf; + + /* + * During queue_setup, + * context information is need to for only main core + */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + /* Video output for decoding (source) + * this can be set after getting an instance + */ + if (core_ctx->state == MFCINST_GOT_INST && + vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_debug(4, "dec src\n"); + /* A single plane is required for input */ + *plane_count = 1; + if (*buf_count < 1) + *buf_count = 1; + if (*buf_count > MFC_MAX_BUFFERS) + *buf_count = MFC_MAX_BUFFERS; + + /* need to use minimum size to prevent qbuf fail */ + psize[0] = 1; + alloc_devs[0] = dev->device; + /* Video capture for decoding (destination) + * this can be set after the header was parsed + */ + } else if (core_ctx->state >= MFCINST_HEAD_PARSED && + vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_debug(4, "dec dst\n"); + /* Output plane count is different by the pixel format */ + *plane_count = ctx->num_fd_frame; + /* Setup buffer count */ + if (*buf_count < ctx->dpb_count) + *buf_count = ctx->dpb_count; + if (*buf_count > MFC_MAX_BUFFERS) + *buf_count = MFC_MAX_BUFFERS; + + if (ctx->dst_fmt->mem_planes == 1) { + psize[0] = raw->total_plane_size; + alloc_devs[0] = dev->device; + } else { + for (i = 0; i < ctx->dst_fmt->num_planes; i++) { + psize[i] = ctx->min_dpb_size[i]; + alloc_devs[i] = dev->device; + } + } + if (ctx->multi_view_enable) { + offset = ctx->view_buf_info[MFC_MV_BUF_IDX_VIEW1].offset; + if (ctx->dst_fmt->mem_planes == 1) { + psize[offset] = raw->total_plane_size; + alloc_devs[offset] = dev->device; + } else { + for (i = 0; i < ctx->dst_fmt->num_planes; i++) { + psize[offset + i] = ctx->min_dpb_size[i]; + alloc_devs[offset + i] = dev->device; + } + } + } + + /* Decoder DPB should be read for reference */ + vq->dma_dir = DMA_BIDIRECTIONAL; + } else { + mfc_err("State seems invalid. State = %d, vq->type = %d\n", + core_ctx->state, vq->type); + return -EINVAL; + } + + mfc_debug(2, "buf_count: %d, plane_count: %d, type: %#x\n", + *buf_count, *plane_count, vq->type); + for (i = 0; i < *plane_count; i++) + mfc_debug(2, "plane[%d] size: %d\n", i, psize[i]); + + mfc_ctx_debug_leave(); + + return 0; +} + +static void mfc_dec_unlock(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mutex_unlock(&dev->mfc_mutex); +} + +static void mfc_dec_lock(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mutex_lock(&dev->mfc_mutex); +} + +static int mfc_dec_buf_init(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + int ret; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + ret = mfc_check_vb_with_fmt(ctx->dst_fmt, vb); + if (ret < 0) + return ret; + mfc_calc_base_addr(ctx, vb, ctx->dst_fmt); + + buf->paddr = mfc_mem_get_paddr_vb(vb); + mfc_ctx_debug(2, "[DPB] vb index [%d] vb paddr %#llx daddr %#llx\n", + vb->index, buf->paddr, buf->addr[0][0]); + + if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_DST, + vb->index) < 0) + mfc_ctx_err("failed in init_buf_ctrls\n"); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + ret = mfc_check_vb_with_fmt(ctx->src_fmt, vb); + if (ret < 0) + return ret; + + buf->addr[0][0] = mfc_mem_get_daddr_vb(vb, 0); + + if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, + vb->index) < 0) + mfc_ctx_err("failed in init_buf_ctrls\n"); + } else { + mfc_ctx_err("unknown queue type\n"); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_dec_buf_prepare(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + struct mfc_raw_info *raw; + unsigned int index = vb->index; + size_t buf_size; + int i; + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + raw = &ctx->raw_buf; + /* check the size per plane */ + if (ctx->dst_fmt->mem_planes == 1) { + buf_size = vb2_plane_size(vb, 0); + mfc_ctx_debug(2, "[FRAME] single plane vb size: %lu, calc size: %d\n", + buf_size, raw->total_plane_size); + if (buf_size < raw->total_plane_size) { + mfc_ctx_err("[FRAME] single plane size(%lu) is smaller than (%d)\n", + buf_size, raw->total_plane_size); + return -EINVAL; + } + } else { + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) { + buf_size = vb2_plane_size(vb, i); + mfc_ctx_debug(2, "[FRAME] plane[%d] vb size: %lu, calc size: %d\n", + i, buf_size, raw->plane_size[i]); + if (buf_size < raw->plane_size[i]) { + mfc_ctx_err("[FRAME] plane[%d] size(%lu) is smaller than (%d)\n", + i, buf_size, raw->plane_size[i]); + return -EINVAL; + } + } + } + /* Copy dst buffer flag to buf_ctrl */ + buf->flag = call_cop(ctx, get_buf_ctrl_val, ctx, + &ctx->dst_ctrls[index], + V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG); + + mfc_mem_buf_prepare(vb, 0); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + buf_size = vb2_plane_size(vb, 0); + buf->sg_size = mfc_mem_get_sg_length(ctx->dev, vb2_dma_sg_plane_desc(vb, 0)); + vb->planes[0].bytesused = buf->vb.planes[0].bytesused; + vb->planes[0].data_offset = buf->vb.planes[0].data_offset; + mfc_ctx_debug(2, "[STREAM] vb size, %ld, %s, %ld, sg_size, %zu, %s, %u, %s, %u\n", + buf_size, + "dbuf size", vb->planes[0].dbuf->size, + buf->sg_size, + "bytesused", vb->planes[0].bytesused, + "data_offset", vb->planes[0].data_offset); + + call_cop(ctx, to_buf_ctrls, ctx, &ctx->src_ctrls[index]); + + /* Copy src buffer flag to buf_ctrl */ + buf->flag = call_cop(ctx, get_buf_ctrl_val, ctx, + &ctx->src_ctrls[index], + V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG); + + mfc_mem_buf_prepare(vb, 1); + } + + return 0; +} + +static void mfc_dec_buf_finish(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + unsigned int index = vb->index; + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + /* Copy to dst buffer flag */ + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, buf->flag); + mfc_ctx_debug(4, "[FLAG] dst update buf[%d] flag = %#x\n", + index, buf->flag); + + call_cop(ctx, to_ctx_ctrls, ctx, &ctx->dst_ctrls[index]); + + mfc_mem_buf_finish(vb, 0); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + /* Copy to src buffer flag */ + call_cop(ctx, update_buf_val, ctx, &ctx->src_ctrls[index], + V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, buf->flag); + mfc_ctx_debug(4, "[FLAG] src update buf[%d] flag = %#x\n", + index, buf->flag); + + call_cop(ctx, to_ctx_ctrls, ctx, &ctx->src_ctrls[index]); + } +} + +static void mfc_dec_buf_cleanup(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + unsigned int index = vb->index; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + if (call_cop(ctx, cleanup_buf_ctrls, ctx, + MFC_CTRL_TYPE_DST, index) < 0) + mfc_ctx_err("failed in cleanup_buf_ctrls\n"); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + if (call_cop(ctx, cleanup_buf_ctrls, ctx, + MFC_CTRL_TYPE_SRC, index) < 0) + mfc_ctx_err("failed in cleanup_buf_ctrls\n"); + } else { + mfc_ctx_err("unknown queue type\n"); + } + + mfc_ctx_debug_leave(); +} + +static int mfc_dec_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mfc_rm_update_real_time(ctx); + + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + + return 0; +} + +static void mfc_dec_stop_streaming(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mfc_ctx_info("dec stop_streaming is called, type : %d\n", q->type); + MFC_TRACE_CTX("** DEC streamoff(type:%d)\n", q->type); + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + mfc_rm_request_work(ctx->dev, MFC_WORK_BUTLER, ctx); + + mfc_rm_instance_dec_stop(dev, ctx, q->type); +} + +static void mfc_dec_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + int i; + unsigned char *stream_vir = NULL; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mutex_lock(&ctx->op_mode_mutex); + buf->src_index = ctx->serial_src_index++; + mfc_ctx_debug(2, "[BUFINFO] ctx[%d] add src index: %d(%d), addr: 0x%08llx\n", + ctx->num, vb->index, buf->src_index, + buf->addr[0][0]); + mutex_unlock(&ctx->op_mode_mutex); + + if (vb->memory == V4L2_MEMORY_DMABUF && + mfc_rm_query_state(ctx, SMALLER, MFCINST_HEAD_PARSED)) + stream_vir = vb2_plane_vaddr(vb, 0); + + buf->vir_addr[0] = stream_vir; + + mfc_add_tail_buf(ctx, &ctx->src_buf_ready_queue, buf); + + if (dev->debugfs.debug_ts == 1) + mfc_ctx_info("[TS] framerate: %ld, timestamp: %lld\n", + ctx->framerate, buf->vb.vb2_buf.timestamp); + + MFC_TRACE_CTX("Q src[%d](%d) fd: %d, %#llx\n", + vb->index, buf->src_index, vb->planes[0].m.fd, buf->addr[0][0]); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + for (i = 0; i < ctx->num_fd_frame; i++) { + // ToDo: if multi_view, vir_addr array_size could be over 3 + buf->vir_addr[i] = vb2_plane_vaddr(vb, i); + mfc_ctx_debug(2, "[BUFINFO] ctx[%d] add dst index: %d, addr[0][%d]: 0x%08llx\n", + ctx->num, vb->index, i, buf->addr[0][i]); + if (ctx->multi_view_enable) { + mfc_ctx_debug(2, "[BUFINFO-VIEW1] ctx[%d] add dst index: %d, addr[2][%d]: 0x%08llx\n", + ctx->num, vb->index, i, buf->addr[2][i]); + } + } + mfc_store_dpb(ctx, vb); + + if ((vb->memory == V4L2_MEMORY_USERPTR || vb->memory == V4L2_MEMORY_DMABUF) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, + &ctx->dst_buf_queue, dec->total_dpb_count)) + ctx->capture_state = QUEUE_BUFS_MMAPED; + + MFC_TRACE_CTX("Q dst[%d][%d] fd: %d, %#llx / used %#lx\n", + vb->index, buf->dpb_index, vb->planes[0].m.fd, + buf->addr[0][0], dec->dynamic_used); + } else { + mfc_ctx_err("Unsupported buffer type (%d)\n", vq->type); + } + + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + + mfc_ctx_debug_leave(); +} + +static const struct vb2_ops mfc_dec_qops = { + .queue_setup = mfc_dec_queue_setup, + .wait_prepare = mfc_dec_unlock, + .wait_finish = mfc_dec_lock, + .buf_init = mfc_dec_buf_init, + .buf_prepare = mfc_dec_buf_prepare, + .buf_finish = mfc_dec_buf_finish, + .buf_cleanup = mfc_dec_buf_cleanup, + .start_streaming = mfc_dec_start_streaming, + .stop_streaming = mfc_dec_stop_streaming, + .buf_queue = mfc_dec_buf_queue, +}; + +const struct vb2_ops *mfc_get_dec_vb2_ops(void) +{ + return &mfc_dec_qops; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h new file mode 100644 index 000000000000..3d0cb7b14ce5 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_dec_vb2.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_DEC_VB2_H +#define __MFC_DEC_VB2_H __FILE__ + +#include "base/mfc_common.h" + +const struct vb2_ops *mfc_get_dec_vb2_ops(void); + +#endif /* __MFC_DEC_VB2_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035637epcas5p4d52ed2f59e17862cd7d7a650fa01bf44@epcas5p4.samsung.com>]
* [PATCH 18/29] media: mfc: Add V4L2 decoder driver [not found] ` <CGME20250930035637epcas5p4d52ed2f59e17862cd7d7a650fa01bf44@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Add a V4L2‑based decoder for Exynos MFC. - Implement full decoder V4L2 ioctl, control, buffer, and stream handling. - Provide ioctl getter and default format helper. Move the decoder to the standard V4L2 framework, to enable proper media‑device registration and user‑space interaction. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../samsung/exynos-mfc/mfc_dec_v4l2.c | 1741 +++++++++++++++++ .../samsung/exynos-mfc/mfc_dec_v4l2.h | 22 + 3 files changed, 1764 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index 9127f2dc4df6..b6b312ae7f22 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_VIDEO_EXYNOS_MFC) := exynos_mfc.o ccflags-y += -I$(srctree)/$(src) #Dev interface layer -exynos_mfc-y += mfc.o mfc_dec_vb2.o +exynos_mfc-y += mfc.o mfc_dec_v4l2.o mfc_dec_vb2.o #Dev control layer exynos_mfc-y += mfc_rm.o mfc_ctx_ctrl.o mfc_debugfs.o #Core interface layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c new file mode 100644 index 000000000000..dd59dc352e34 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c @@ -0,0 +1,1741 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * mfc_dec_v4l2.c + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/vmalloc.h> +#include <kunit/visibility.h> + +#include "mfc_dec_v4l2.h" +#include "mfc_dec_vb2.h" +#include "mfc_rm.h" + +#include "mfc_core_hwlock.h" + +#include "base/mfc_format.h" +#include "base/mfc_queue.h" +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" + +#define MAX_FRAME_SIZE (2 * SZ_1K * SZ_1K) +static struct v4l2_queryctrl dec_controls[] = { + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H.264 Display Delay", + .minimum = -1, + .maximum = 32, + .step = 1, + .default_value = -1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mpeg4 Loop Filter Enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Slice Interface Enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Packed PB Enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame Tag", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "CRC enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "CRC data", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "CRC data", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Display status", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame type", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Frame pack sei parse flag", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_I_FRAME_DECODING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "I frame decoding mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frames per second in 1000x scale", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 60000, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODER_IMMEDIATE_DISPLAY, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Immediate Display Enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODER_DECODING_TIMESTAMP_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Decoding Timestamp Mode Enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODER_WAIT_DECODING_START, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Wait until buffer setting done", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_GET_VERSION_INFO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Get MFC version information", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_SET_DUAL_DPB_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Set Dual DPB mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_QOS_RATIO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "QoS ratio value", + .minimum = 20, + .maximum = INT_MAX, + .step = 1, + .default_value = 100, + }, + { + .id = V4L2_CID_MPEG_MFC_SET_DYNAMIC_DPB_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Set dynamic DPB", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_SET_USER_SHARED_HANDLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Set dynamic DPB", + .minimum = 0, + .maximum = U16_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_GET_EXT_INFO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Get extra information", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_SET_BUF_PROCESS_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Set buffer process type", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_GET_10BIT_INFO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "10 bit contents information", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_BLACK_BAR_DETECT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Set black bar detection option", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_HDR_USER_SHARED_HANDLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Dynamic HDR10+ SEI metadata", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_AV1_FILM_GRAIN_USER_SHARED_HANDLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "AV1 Film Grain SEI metadata", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_AV1_FILM_GRAIN_PRESENT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "AV1 Film Grain presented", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DECODING_ORDER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "decoding order enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_UNCOMP_FMT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Uncompressed format", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_GET_DISPLAY_DELAY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "display delay for first frame", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_POC, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame POC", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Buffer flag", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Buffer flag", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SKIP_LAZY_UNMAP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "skip lazy unmap", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_PRIORITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "priority", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_HEIF_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "heif mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_MULTI_VIEW_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Multi-View Enable", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, +}; + +#define DEC_NUM_CTRLS ARRAY_SIZE(dec_controls) +/* Find selected format description */ +VISIBLE_IF_KUNIT struct mfc_fmt *__mfc_dec_find_format(struct mfc_ctx *ctx, + unsigned int pixelformat) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_fmt *fmt = NULL; + unsigned long i; + + for (i = 0; i < MFC_NUM_FORMATS; i++) { + if ((mfc_formats[i].type & MFC_FMT_STREAM) && + !(mfc_formats[i].type & MFC_FMT_DEC)) { + continue; + } + if (mfc_formats[i].fourcc == pixelformat) { + fmt = (struct mfc_fmt *)&mfc_formats[i]; + break; + } + } + + if (fmt && !dev->pdata->support_10bit && (fmt->type & MFC_FMT_10BIT)) { + mfc_ctx_err("[FRAME] 10bit is not supported\n"); + fmt = NULL; + } + if (fmt && !dev->pdata->support_422 && (fmt->type & MFC_FMT_422)) { + mfc_ctx_err("[FRAME] 422 is not supported\n"); + fmt = NULL; + } + if (fmt && (fmt->type & MFC_FMT_RGB)) { + mfc_ctx_err("[FRAME] RGB is not supported by decoder\n"); + fmt = NULL; + } + if (fmt && (fmt->type & MFC_FMT_STREAM) && + dev->pdata->mfc_resource[fmt->codec_mode].op_core_type == MFC_OP_CORE_NOT_FIXED) { + mfc_ctx_err("[STREAM] %s is not supported\n", fmt->name); + fmt = NULL; + } + + return fmt; +} +EXPORT_SYMBOL_IF_KUNIT(__mfc_dec_find_format); + +static struct v4l2_queryctrl *__mfc_dec_get_ctrl(int id) +{ + unsigned long i; + + for (i = 0; i < DEC_NUM_CTRLS; ++i) + if (id == dec_controls[i].id) + return &dec_controls[i]; + + return NULL; +} + +/* Check whether a ctrl value if correct */ +static int __mfc_dec_check_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + struct v4l2_queryctrl *c; + + c = __mfc_dec_get_ctrl(ctrl->id); + if (!c) { + mfc_ctx_err("[CTRLS] not supported control id (%#x)\n", ctrl->id); + return -EINVAL; + } + + if (ctrl->value < c->minimum || ctrl->value > c->maximum || + (c->step != 0 && ctrl->value % c->step != 0)) { + mfc_ctx_err("[CTRLS][%s] id: %#x, invalid value (%d)\n", + c->name, ctrl->id, ctrl->value); + return -ERANGE; + } + + mfc_ctx_debug(5, "[CTRLS][%s] id: %#x, value: %d (%#x)\n", + c->name, ctrl->id, ctrl->value, ctrl->value); + + return 0; +} + +/* Query capabilities of the device */ +static int mfc_dec_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, "MFC", sizeof(cap->driver)); + strscpy(cap->card, "decoder", sizeof(cap->card)); + + return 0; +} + +static int __mfc_dec_enum_fmt(struct mfc_dev *dev, struct v4l2_fmtdesc *f, + unsigned int type) +{ + struct mfc_fmt *fmt; + unsigned long i, j = 0; + + for (i = 0; i < MFC_NUM_FORMATS; ++i) { + if (!(mfc_formats[i].type & type)) + continue; + if (!dev->pdata->support_10bit && (mfc_formats[i].type & MFC_FMT_10BIT)) + continue; + if (!dev->pdata->support_422 && (mfc_formats[i].type & MFC_FMT_422)) + continue; + + if (j == f->index) { + fmt = &mfc_formats[i]; + strscpy(f->description, fmt->name, + sizeof(f->description)); + f->pixelformat = fmt->fourcc; + + return 0; + } + + ++j; + } + + return -EINVAL; +} + +static int mfc_dec_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, + struct v4l2_fmtdesc *f) +{ + struct mfc_dev *dev = video_drvdata(file); + + return __mfc_dec_enum_fmt(dev, f, MFC_FMT_FRAME); +} + +static int mfc_dec_enum_fmt_vid_out_mplane(struct file *file, void *prov, + struct v4l2_fmtdesc *f) +{ + struct mfc_dev *dev = video_drvdata(file); + + return __mfc_dec_enum_fmt(dev, f, MFC_FMT_STREAM); +} + +static void __mfc_dec_change_format_8bit(struct mfc_ctx *ctx) +{ + u32 org_fmt = ctx->dst_fmt->fourcc; + + switch (org_fmt) { + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + /* It is right format */ + break; + case V4L2_PIX_FMT_NV61M: + /* change to CrCb order format */ + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV21M); + break; + default: + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M); + break; + } +} + +static void __mfc_dec_change_format_8bit_422(struct mfc_ctx *ctx) +{ + u32 org_fmt = ctx->dst_fmt->fourcc; + + switch (org_fmt) { + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + /* It is right format */ + break; + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_YVU420M: + /* change to CrCb order format */ + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV61M); + break; + default: + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M); + break; + } +} + +static void __mfc_dec_change_format(struct mfc_ctx *ctx) +{ + u32 org_fmt = ctx->dst_fmt->fourcc; + + if (ctx->is_422) + __mfc_dec_change_format_8bit_422(ctx); + else + __mfc_dec_change_format_8bit(ctx); + + ctx->raw_buf.num_planes = ctx->dst_fmt->num_planes; + if (org_fmt != ctx->dst_fmt->fourcc) + mfc_ctx_info("[FRAME] format is changed to %s\n", ctx->dst_fmt->name); +} + +static void __mfc_dec_set_num_fd_frame(struct mfc_ctx *ctx, + struct v4l2_pix_format_mplane *pix_fmt_mp) +{ + int calc_num_planes; + int num_fd_depth_map = 0; + int num_view = 1; + int num_fd_sub_view_meta = 0; + + if (ctx->multi_view_enable) { + pix_fmt_mp->flags |= MFC_FMT_FLAG_MULTI_VIEW; + num_view = MFC_NUM_MULTI_VIEW; + num_fd_sub_view_meta = MFC_NUM_FD_SUB_VIEW_META; + + // ToDo: Depth is not supported yet. + pix_fmt_mp->flags &= ~MFC_FMT_FLAG_DEPTH_MAP; + num_fd_depth_map = 0; + + calc_num_planes = + (ctx->dst_fmt->mem_planes + num_fd_depth_map) * num_view + + num_fd_sub_view_meta; + } else { + pix_fmt_mp->flags &= ~MFC_FMT_FLAG_MULTI_VIEW; + calc_num_planes = ctx->dst_fmt->mem_planes; + } + + mfc_set_view_buf_info(ctx, ctx->dst_fmt->mem_planes, + num_fd_depth_map, num_fd_sub_view_meta); + + ctx->num_fd_frame = calc_num_planes; + pix_fmt_mp->num_planes = calc_num_planes; +} + +static void __mfc_dec_update_pix_format(struct mfc_ctx *ctx, struct v4l2_format *f) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_raw_info *raw; + int i; + + raw = &ctx->raw_buf; + + pix_fmt_mp->width = ctx->img_width; + pix_fmt_mp->height = ctx->img_height; + __mfc_dec_set_num_fd_frame(ctx, pix_fmt_mp); + + if (dec->is_interlaced) + pix_fmt_mp->field = V4L2_FIELD_INTERLACED; + else + pix_fmt_mp->field = V4L2_FIELD_NONE; + + /* Set pixelformat to the format in which MFC outputs the decoded frame */ + pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc; + for (i = 0; i < ctx->dst_fmt->mem_planes; i++) { + pix_fmt_mp->plane_fmt[i].bytesperline = raw->stride[i]; + if (ctx->dst_fmt->mem_planes == 1) + pix_fmt_mp->plane_fmt[i].sizeimage = raw->total_plane_size; + else + pix_fmt_mp->plane_fmt[i].sizeimage = raw->plane_size[i]; + } +} + +/* Get format */ +static int mfc_dec_g_fmt_vid_cap_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_dec *dec = ctx->dec_priv; + int ret; + + mfc_ctx_debug_enter(); + + /* During g_fmt, context information is need to for only main core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + mfc_debug(2, "dec dst g_fmt, state: %d wait_state: %d\n", + core_ctx->state, ctx->wait_state); + MFC_TRACE_CTX("** DEC g_fmt(state:%d wait_state:%d)\n", + core_ctx->state, ctx->wait_state); + + mutex_lock(&ctx->drc_wait_mutex); + if (dec->disp_drc.disp_res_change) { + __mfc_dec_update_pix_format(ctx, f); + mutex_unlock(&ctx->drc_wait_mutex); + return 0; + } + mutex_unlock(&ctx->drc_wait_mutex); + + if (core_ctx->state == MFCINST_GOT_INST || + core_ctx->state == MFCINST_RES_CHANGE_INIT || + core_ctx->state == MFCINST_RES_CHANGE_FLUSH || + core_ctx->state == MFCINST_RES_CHANGE_FLUSH_FINISHED || + core_ctx->state == MFCINST_RES_CHANGE_END) { + /* If there is no source buffer to parsing, we can't SEQ_START */ + mutex_lock(&ctx->drc_wait_mutex); + if (((ctx->wait_state & WAIT_G_FMT) != 0) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, + &ctx->src_buf_ready_queue, 0) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, + &core_ctx->src_buf_queue, 0)) { + mfc_err("There is no source buffer to parsing, keep previous resolution\n"); + mutex_unlock(&ctx->drc_wait_mutex); + return -EAGAIN; + } + mutex_unlock(&ctx->drc_wait_mutex); + + /* + * If the MFC is parsing the header, + * so wait until it is finished. + */ + ret = mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_SEQ_DONE_RET); + if (ret) { + if (core_ctx->int_err == MFC_REG_ERR_UNSUPPORTED_FEATURE) { + mfc_err("header parsing failed by unsupported feature\n"); + return -EINVAL; + } + mfc_err("header parsing failed\n"); + return -EAGAIN; + } + } + + if (core_ctx->state >= MFCINST_HEAD_PARSED && + core_ctx->state < MFCINST_ABORT) { + if (mfc_check_resolution(ctx)) { + mfc_ctx_err("Unsupported product resolution\n"); + return -EAGAIN; + } + + /* This is run on CAPTURE (decode output) */ + if (ctx->stream_op_mode == MFC_OP_TWO_MODE1 || + ctx->stream_op_mode == MFC_OP_TWO_MODE2) { + mfc_info("[2CORE] start the sub core\n"); + if (mfc_rm_instance_setup(dev, ctx)) { + mfc_err("[2CORE] failed to setup sub core\n"); + return -EAGAIN; + } + } + + /* + * The format should be changed according to various conditions. + * 1. bit depth (8bit or 10bit) + * 2. chroma order (CbCr or CrCb) + * 3. component in memory (multi or single) + */ + + __mfc_dec_change_format(ctx); + + /* Width and height are set to the dimensions + * of the movie, the buffer is bigger and + * further processing stages should crop to this + * rectangle. + */ + mfc_dec_calc_dpb_size(ctx, &ctx->raw_buf, ctx->dst_fmt); + + if (IS_LOW_MEM) { + unsigned int dpb_size; + /* + * If total memory requirement is too big for this device, + * then it returns error. + * DPB size : Total plane size * the number of DPBs + * 5: the number of extra DPBs + * 3: the number of DPBs for Android framework + * 600MB: being used to return an error, + * when 8K resolution video clip is being tried to be decoded + */ + dpb_size = (ctx->raw_buf.total_plane_size * + (ctx->dpb_count + MFC_EXTRA_DPB + 3)); + if (dpb_size > SZ_6M) { + mfc_info("required memory size is too big (%dx%d, dpb: %d)\n", + ctx->img_width, ctx->img_height, ctx->dpb_count); + return -EINVAL; + } + } + + __mfc_dec_update_pix_format(ctx, f); + } + + mutex_lock(&ctx->drc_wait_mutex); + if ((ctx->wait_state & WAIT_G_FMT) != 0) { + ctx->wait_state &= ~(WAIT_G_FMT); + mfc_debug(2, "clear WAIT_G_FMT %d\n", ctx->wait_state); + MFC_TRACE_CTX("** DEC clear WAIT_G_FMT(wait_state %d)\n", ctx->wait_state); + } + mutex_unlock(&ctx->drc_wait_mutex); + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_dec_g_fmt_vid_out_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + + mfc_ctx_debug_enter(); + + mfc_ctx_debug(4, "dec src g_fmt\n"); + + /* This is run on OUTPUT + * The buffer contains compressed image + * so width and height have no meaning + */ + pix_fmt_mp->width = 0; + pix_fmt_mp->height = 0; + pix_fmt_mp->field = V4L2_FIELD_NONE; + pix_fmt_mp->plane_fmt[0].bytesperline = dec->src_buf_size; + pix_fmt_mp->plane_fmt[0].sizeimage = dec->src_buf_size; + pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc; + pix_fmt_mp->num_planes = ctx->src_fmt->mem_planes; + + mfc_ctx_debug_leave(); + + return 0; +} + +/* Try format */ +static int mfc_dec_try_fmt(struct file *file, void *priv, struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_fmt *fmt; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + + fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for %s\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "source" : "destination"); + return -EINVAL; + } + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && + fmt->codec_mode == MFC_FORMATS_NO_CODEC) { + mfc_ctx_err("MFC_FORMATS_NO_CODEC is invalid to src(fmt is %s)\n", + fmt->name); + return -EINVAL; + } + + /* For resource reservation */ + ctx->img_width = pix_fmt_mp->width; + ctx->img_height = pix_fmt_mp->height; + + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + ctx->src_fmt = fmt; + ctx->codec_mode = ctx->src_fmt->codec_mode; + ctx->op_core_type = ctx->dev->pdata->mfc_resource[ctx->codec_mode].op_core_type; + } + + mfc_ctx_debug(2, "[%s] resolution %dx%d, %s : %s\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "STREAM" : "FRAME", + ctx->img_width, ctx->img_height, + V4L2_TYPE_IS_OUTPUT(f->type) ? "codectype" : "pixelformat", fmt->name); + + return 0; +} + +/* Set format */ +static int mfc_dec_s_fmt_vid_cap_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_fmt *fmt = NULL; + + mfc_ctx_debug_enter(); + + if (ctx->vq_dst.streaming) { + mfc_ctx_err("queue busy\n"); + return -EBUSY; + } + + fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for destination\n"); + return -EINVAL; + } + ctx->dst_fmt = fmt; + + if ((!ctx->img_width && !ctx->img_height) && + pix_fmt_mp->width > 0 && pix_fmt_mp->height > 0) { + ctx->img_width = pix_fmt_mp->width; + ctx->img_height = pix_fmt_mp->height; + } + + ctx->raw_buf.num_planes = ctx->dst_fmt->num_planes; + mfc_ctx_info("[FRAME] dec dst pixelformat : %s (%d x %d)\n", + ctx->dst_fmt->name, ctx->img_width, ctx->img_height); + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_dec_s_fmt_vid_out_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_fmt *fmt = NULL; + int ret = 0; + + mfc_ctx_debug_enter(); + + if (ctx->vq_src.streaming) { + mfc_ctx_err("queue busy\n"); + return -EBUSY; + } + + fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for source\n"); + return -EINVAL; + } + ctx->src_fmt = fmt; + + ctx->codec_mode = ctx->src_fmt->codec_mode; + mfc_ctx_info("[STREAM] codectype: %s(%d)\n", + ctx->src_fmt->name, ctx->codec_mode); + + ctx->pix_format = pix_fmt_mp->pixelformat; + if (pix_fmt_mp->width > 0 && pix_fmt_mp->height > 0) { + ctx->img_height = pix_fmt_mp->height; + ctx->img_width = pix_fmt_mp->width; + } + + /* As this buffer will contain compressed data, the size is set + * to the maximum size. + */ + if (pix_fmt_mp->plane_fmt[0].sizeimage) + dec->src_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage; + else + dec->src_buf_size = MAX_FRAME_SIZE; + mfc_ctx_debug(2, "[STREAM] sizeimage: %d\n", pix_fmt_mp->plane_fmt[0].sizeimage); + pix_fmt_mp->plane_fmt[0].bytesperline = 0; + + ret = mfc_rm_instance_open(dev, ctx); + if (ret) + mfc_ctx_err("Failed to instance open\n"); + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Request buffers */ +static int mfc_dec_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *reqbufs) +{ + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int i, ret = 0; + + mfc_ctx_debug_enter(); + + if (reqbufs->memory == V4L2_MEMORY_MMAP) { + mfc_ctx_err("Not supported memory type (%d)\n", reqbufs->memory); + return -EINVAL; + } + + if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "dec src reqbuf(%d)\n", reqbufs->count); + /* Can only request buffers after + * an instance has been opened. + */ + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_GOT_INST)) { + if (reqbufs->count == 0) { + ret = vb2_reqbufs(&ctx->vq_src, reqbufs); + ctx->output_state = QUEUE_FREE; + return ret; + } + + /* Decoding */ + if (ctx->output_state != QUEUE_FREE) { + mfc_ctx_err("Bufs have already been requested\n"); + return -EINVAL; + } + + ret = vb2_reqbufs(&ctx->vq_src, reqbufs); + if (ret) { + mfc_ctx_err("vb2_reqbufs on src failed\n"); + return ret; + } + + ctx->output_state = QUEUE_BUFS_REQUESTED; + } + } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "dec dst reqbuf(%d)\n", reqbufs->count); + if (reqbufs->count == 0) { + ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); + + if (!dec->inter_res_change) { + for (i = 0; i < MFC_CORE_TYPE_NUM; i++) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + break; + core = dev->core[ctx->op_core_num[i]]; + + core_ctx = core->core_ctx[ctx->num]; + mfc_release_codec_buffers(core_ctx); + } + } + ctx->capture_state = QUEUE_FREE; + return ret; + } + + if (ctx->capture_state != QUEUE_FREE) { + mfc_ctx_err("Bufs have already been requested\n"); + return -EINVAL; + } + + ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); + if (ret) { + mfc_ctx_err("vb2_reqbufs on capture failed\n"); + return ret; + } + + if (reqbufs->count < ctx->dpb_count) { + mfc_ctx_err("Not enough buffers allocated\n"); + reqbufs->count = 0; + vb2_reqbufs(&ctx->vq_dst, reqbufs); + return -ENOMEM; + } + + dec->total_dpb_count = reqbufs->count; + + if (!dec->inter_res_change) { + for (i = 0; i < MFC_CORE_TYPE_NUM; i++) { + if (ctx->op_core_num[i] == MFC_CORE_INVALID) + break; + + core = dev->core[ctx->op_core_num[i]]; + core_ctx = core->core_ctx[ctx->num]; + ret = mfc_alloc_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to allocate decoding buffers\n"); + reqbufs->count = 0; + vb2_reqbufs(&ctx->vq_dst, reqbufs); + return -ENOMEM; + } + } + } + + ctx->capture_state = QUEUE_BUFS_REQUESTED; + + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + } + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Query buffer */ +static int mfc_dec_querybuf(struct file *file, void *priv, + struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret; + + mfc_ctx_debug_enter(); + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "dec dst querybuf\n"); + ret = vb2_querybuf(&ctx->vq_dst, buf); + if (ret != 0) { + mfc_ctx_err("dec dst: error in vb2_querybuf()\n"); + return ret; + } + } else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "dec src querybuf\n"); + ret = vb2_querybuf(&ctx->vq_src, buf); + if (ret != 0) { + mfc_ctx_err("dec src: error in vb2_querybuf()\n"); + return ret; + } + } else { + mfc_ctx_err("invalid buf type (%d)\n", buf->type); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Queue a buffer */ +static int mfc_dec_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + int ret = -EINVAL; + + mfc_ctx_debug_enter(); + + if (mfc_rm_query_state(ctx, EQUAL_OR, MFCINST_ERROR)) { + mfc_ctx_err("Call on QBUF after unrecoverable error\n"); + return -EIO; + } + + if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) { + mfc_ctx_err("Invalid V4L2 Buffer for driver: type(%d)\n", buf->type); + return -EINVAL; + } + + if (!buf->length) { + mfc_ctx_err("multiplanar but length is zero\n"); + return -EIO; + } + + if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "dec src buf[%d] Q\n", buf->index); + if (buf->m.planes[0].bytesused > buf->m.planes[0].length) { + mfc_ctx_err("data size (%d) %s(%d)\n", + buf->m.planes[0].bytesused, + "must be less than buffer size", + buf->m.planes[0].length); + return -EIO; + } + + mfc_idle_update_queued(dev, ctx); + mfc_rate_update_bitrate(ctx, buf->m.planes[0].bytesused); + mfc_rate_update_bufq_framerate(ctx, MFC_TS_SRC_Q); + mfc_rate_update_framerate(ctx); + mfc_rm_qos_control(ctx, MFC_QOS_TRIGGER); + + if (!buf->m.planes[0].bytesused) { + buf->m.planes[0].bytesused = buf->m.planes[0].length; + mfc_ctx_debug(2, "Src size zero, changed to buf size %d\n", + buf->m.planes[0].bytesused); + } else { + mfc_ctx_debug(2, "Src size, %d, buf length, %d\n", + buf->m.planes[0].bytesused, + buf->m.planes[0].length); + } + + ret = vb2_qbuf(&ctx->vq_src, NULL, buf); + } else { + mfc_ctx_debug(4, "dec dst buf[%d] Q\n", buf->index); + mfc_idle_update_queued(dev, ctx); + mfc_rate_update_bufq_framerate(ctx, MFC_TS_DST_Q); + mfc_rate_update_framerate(ctx); + mfc_rm_qos_control(ctx, MFC_QOS_TRIGGER); + ret = vb2_qbuf(&ctx->vq_dst, NULL, buf); + } + + mfc_ctx_debug_leave(); + return ret; +} + +/* Dequeue a buffer */ +static int mfc_dec_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; + struct dec_dpb_ref_info *dst_buf, *src_buf; + int ret; + int ncount = 0; + + mfc_ctx_debug_enter(); + + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_ERROR)) { + mfc_ctx_err("Call on DQBUF after unrecoverable error\n"); + return -EIO; + } + + if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) { + mfc_ctx_err("Invalid V4L2 Buffer for driver: type(%d)\n", buf->type); + return -EINVAL; + } + + if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK); + mfc_ctx_debug(4, "dec src buf[%d] DQ\n", buf->index); + } else { + ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK); + mfc_ctx_debug(4, "dec dst buf[%d] DQ\n", buf->index); + + if (buf->index >= MFC_MAX_BUFFERS) { + mfc_ctx_err("buffer index[%d] range over\n", buf->index); + return -EINVAL; + } + + /* Memcpy from dec->ref_info to shared memory */ + if (dec->ref_info) { + src_buf = &dec->ref_info[buf->index]; + for (ncount = 0; ncount < MFC_MAX_BUFFERS; ncount++) { + if (src_buf->dpb[ncount].fd[0] == MFC_INFO_INIT_FD) + break; + mfc_ctx_debug(2, "[REFINFO] DQ index[%d] Released FD = %d\n", + buf->index, src_buf->dpb[ncount].fd[0]); + } + + if (dec->sh_handle_dpb.vaddr) { + dst_buf = (struct dec_dpb_ref_info *) + dec->sh_handle_dpb.vaddr + buf->index; + memcpy(dst_buf, src_buf, sizeof(struct dec_dpb_ref_info)); + dst_buf->index = buf->index; + } + } + } + mfc_ctx_debug_leave(); + return ret; +} + +/* Stream on */ +static int mfc_dec_streamon(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret = -EINVAL; + + mfc_ctx_debug_enter(); + + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "dec src streamon\n"); + ret = vb2_streamon(&ctx->vq_src, type); + } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "dec dst streamon\n"); + ret = vb2_streamon(&ctx->vq_dst, type); + if (!ret) + mfc_rm_qos_control(ctx, MFC_QOS_ON); + } else { + mfc_ctx_err("unknown v4l2 buffer type\n"); + } + + mfc_ctx_debug(2, "src: %d, dst: %d, dpb_count = %d\n", + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + ctx->dpb_count); + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Stream off, which equals to a pause */ +static int mfc_dec_streamoff(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret = -EINVAL; + + mfc_ctx_debug_enter(); + + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "dec src streamoff\n"); + ret = vb2_streamoff(&ctx->vq_src, type); + } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "dec dst streamoff\n"); + mfc_rate_reset_bufq_framerate(ctx); + ret = vb2_streamoff(&ctx->vq_dst, type); + if (!ret) + mfc_rm_qos_control(ctx, MFC_QOS_OFF); + } else { + mfc_ctx_err("unknown v4l2 buffer type\n"); + } + + mfc_ctx_debug_leave(); + + return ret; +} + +static int __mfc_dec_ext_info(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + int val = 0; + + val |= DEC_SET_DYNAMIC_DPB; + val |= DEC_SET_C2_INTERFACE; + val |= DEC_SET_BUF_FLAG_CTRL; + val |= DEC_SET_FRAME_ERR_TYPE; + val |= DEC_SET_OPERATING_FPS; + val |= DEC_SET_PRIORITY; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->skype)) + val |= DEC_SET_SKYPE_FLAG; + + mfc_ctx_debug(5, "[CTRLS] ext info val: %#x\n", val); + + return val; +} + +/* Get ctrl */ +static int __mfc_dec_get_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_ctx_ctrl *ctx_ctrl; + int found = 0; + + switch (ctrl->id) { + case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER: + ctrl->value = dec->loop_filter_mpeg4; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY: + ctrl->value = dec->display_delay; + break; + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: + /* These context information is need to for only main core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (core_ctx->state >= MFCINST_HEAD_PARSED && + core_ctx->state < MFCINST_ABORT) { + ctrl->value = ctx->dpb_count; + break; + } else if (core_ctx->state != MFCINST_INIT) { + mfc_err("Decoding not initialised\n"); + return -EINVAL; + } + + /* Should wait for the header to be parsed */ + if (mfc_wait_for_done_core_ctx(core_ctx, + MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + core->sched->yield_work(core, core_ctx); + return -EIO; + } + + if (core_ctx->state >= MFCINST_HEAD_PARSED && + core_ctx->state < MFCINST_ABORT) { + ctrl->value = ctx->dpb_count; + } else { + mfc_err("Decoding not initialised\n"); + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE: + ctrl->value = dec->slice_enable; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB: + /* Not used */ + break; + case V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE: + ctrl->value = dec->crc_enable; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_CHECK_STATE: + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + if (ctx->is_dpb_realloc && + mfc_rm_query_state(ctx, EQUAL, MFCINST_HEAD_PARSED)) + ctrl->value = MFCSTATE_DEC_S3D_REALLOC; + else if (core_ctx->state == MFCINST_RES_CHANGE_FLUSH || + core_ctx->state == MFCINST_RES_CHANGE_END || + core_ctx->state == MFCINST_HEAD_PARSED || + dec->inter_res_change) + ctrl->value = MFCSTATE_DEC_RES_DETECT; + else if (mfc_rm_query_state(ctx, EQUAL, MFCINST_FINISHING)) + ctrl->value = MFCSTATE_DEC_TERMINATING; + else + ctrl->value = MFCSTATE_PROCESSING; + break; + case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING: + ctrl->value = dec->sei_parse; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_I_FRAME_DECODING: + ctrl->value = dec->idr_decoding; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE: + ctrl->value = mfc_rate_get_framerate(ctx); + break; + case V4L2_CID_MPEG_MFC_GET_VERSION_INFO: + ctrl->value = dev->pdata->ip_ver; + break; + case V4L2_CID_MPEG_VIDEO_QOS_RATIO: + ctrl->value = ctx->qos_ratio; + break; + case V4L2_CID_MPEG_MFC_SET_DYNAMIC_DPB_MODE: + ctrl->value = dec->is_dynamic_dpb; + break; + case V4L2_CID_MPEG_MFC_GET_EXT_INFO: + ctrl->value = __mfc_dec_ext_info(ctx); + break; + case V4L2_CID_MPEG_MFC_GET_DRIVER_INFO: + ctrl->value = MFC_DRIVER_INFO; + break; + case V4L2_CID_MPEG_VIDEO_UNCOMP_FMT: + if (dec->uncomp_fmt) + ctrl->value = dec->uncomp_fmt->fourcc; + else + ctrl->value = 0; + break; + case V4L2_CID_MPEG_VIDEO_GET_DISPLAY_DELAY: + /* These context information is need to for only main core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + if (core_ctx->state >= MFCINST_HEAD_PARSED) { + ctrl->value = dec->frame_display_delay; + } else { + mfc_err("display delay information not parsed yet\n"); + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_PRIORITY: + ctrl->value = ctx->prio; + mfc_ctx_debug(2, "[PRIO] user get priority: %d (%d)\n", + ctrl->value, ctx->user_prio); + break; + case V4L2_CID_MPEG_MFC_MULTI_VIEW_ENABLE: + ctrl->value = (ctx->multi_view_enable || ctx->ready_to_be_multi_view_enable); + break; + default: + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_GET)) + continue; + + if (ctx_ctrl->id == ctrl->id) { + if (ctx_ctrl->get.has_new) { + ctx_ctrl->get.has_new = 0; + ctrl->value = ctx_ctrl->get.val; + } else { + mfc_ctx_debug(5, "[CTRLS] %s: 0x%08x\n", + "Control value is not up to date", + ctrl->id); + return -EINVAL; + } + + found = 1; + break; + } + } + + if (!found) { + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + return -EINVAL; + } + break; + } + + mfc_ctx_debug(5, "[CTRLS] get id: %#x, value: %d\n", ctrl->id, ctrl->value); + + return 0; +} + +/* Set a ctrl */ +static int mfc_dec_s_ctrl(struct file *file, void *priv, + struct v4l2_control *ctrl) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_ctx_ctrl *ctx_ctrl; + int ret = 0; + int found = 0; + + mfc_ctx_debug_enter(); + + ret = __mfc_dec_check_ctrl_val(ctx, ctrl); + if (ret) + return ret; + + switch (ctrl->id) { + case V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER: + dec->loop_filter_mpeg4 = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY: + dec->display_delay = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE: + dec->slice_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_PACKED_PB: + /* Not used */ + break; + case V4L2_CID_MPEG_MFC51_VIDEO_CRC_ENABLE: + dec->crc_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING: + dec->sei_parse = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_I_FRAME_DECODING: + dec->idr_decoding = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DECODER_IMMEDIATE_DISPLAY: + dec->immediate_display = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DECODER_DECODING_TIMESTAMP_MODE: + dec->is_dts_mode = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DECODER_WAIT_DECODING_START: + mutex_lock(&ctx->drc_wait_mutex); + ctx->wait_state = ctrl->value; + mutex_unlock(&ctx->drc_wait_mutex); + break; + case V4L2_CID_MPEG_MFC_SET_DUAL_DPB_MODE: + mfc_ctx_err("[DPB] not supported CID: 0x%x\n", ctrl->id); + break; + case V4L2_CID_MPEG_VIDEO_QOS_RATIO: + ctx->qos_ratio = ctrl->value; + mfc_ctx_info("[QoS] set %d qos_ratio\n", ctrl->value); + break; + case V4L2_CID_MPEG_MFC_SET_DYNAMIC_DPB_MODE: + /* is_dynamic_dpb is controlled by driver */ + if (dec->is_dynamic_dpb == 0) + mfc_ctx_debug(2, "[PLUGIN] is_dynamic_dpb is disabled by driver\n"); + if (!ctrl->value) + mfc_ctx_err("[DPB] user has to enable is_dynamic_dpb by default\n"); + break; + case V4L2_CID_MPEG_MFC_SET_USER_SHARED_HANDLE: + if (dec->sh_handle_dpb.fd == -1) { + dec->sh_handle_dpb.fd = ctrl->value; + if (mfc_mem_get_user_shared_handle(ctx, &dec->sh_handle_dpb, "DPB")) + return -EINVAL; + } + break; + case V4L2_CID_MPEG_MFC_SET_BUF_PROCESS_TYPE: + ctx->buf_process_type = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_BLACK_BAR_DETECT: + dec->detect_black_bar = ctrl->value; + if (IS_BLACKBAR_OFF(ctx)) { + mfc_ctx_info("[BLACKBAR] black bar detection doesn't work\n"); + dec->detect_black_bar = 0; + } + break; + case V4L2_CID_MPEG_VIDEO_DECODING_ORDER: + dec->decoding_order = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SKIP_LAZY_UNMAP: + ctx->skip_lazy_unmap = ctrl->value; + mfc_ctx_debug(2, "[LAZY_UNMAP] lazy unmap %s\n", + ctx->skip_lazy_unmap ? "disable" : "enable"); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE: + mfc_ctx_debug(2, "[QoS] user set the operating frame rate: %d\n", ctrl->value); + ctx->operating_framerate = ctrl->value; + mfc_rm_update_real_time(ctx); + break; + case V4L2_CID_MPEG_VIDEO_PRIORITY: + mfc_ctx_debug(2, "[PRIO] user set priority: %d\n", ctrl->value); + ctx->user_prio = ctrl->value; + mfc_rm_update_real_time(ctx); + break; + case V4L2_CID_MPEG_MFC_HEIF_MODE: + mfc_ctx_debug(2, "[HEIF] heif mode: %d\n", ctrl->value); + ctx->is_heif_mode = ctrl->value; + break; + default: + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_SET)) + continue; + + if (ctx_ctrl->id == ctrl->id) { + ctx_ctrl->set.has_new = 1; + ctx_ctrl->set.val = ctrl->value; + + found = 1; + break; + } + } + + if (!found) { + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + return -EINVAL; + } + break; + } + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_dec_s_ext_ctrls(struct file *file, void *priv, + struct v4l2_ext_controls *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_ext_control *ext_ctrl; + struct v4l2_control ctrl; + int i; + int ret = 0; + + if (f->which != V4L2_CTRL_CLASS_CODEC && f->which != V4L2_CTRL_CLASS_USER) + return -EINVAL; + + for (i = 0; i < f->count; i++) { + ext_ctrl = (f->controls + i); + + ctrl.id = ext_ctrl->id; + ctrl.value = ext_ctrl->value; + + ret = mfc_dec_s_ctrl(file, priv, &ctrl); + if (ret != 0) { + f->error_idx = i; + break; + } + mfc_ctx_debug(5, "[CTRLS] set id: %#x, value: %d\n", ctrl.id, ctrl.value); + } + + return 0; +} + +static void __mfc_dec_update_disp_res(struct mfc_ctx *ctx, struct v4l2_selection *s) +{ + struct mfc_dec *dec = ctx->dec_priv; + + s->r.left = 0; + s->r.top = 0; + s->r.width = dec->disp_drc.width[dec->disp_drc.pop_idx]; + s->r.height = dec->disp_drc.height[dec->disp_drc.pop_idx]; + mfc_ctx_debug(2, "[FRAME] Composing info: w=%d h=%d\n", s->r.width, s->r.height); + + dec->disp_drc.disp_res_change--; + mfc_ctx_debug(3, "[DRC] disp_res_change[%d] count %d\n", + dec->disp_drc.pop_idx, dec->disp_drc.disp_res_change); + dec->disp_drc.pop_idx = (dec->disp_drc.pop_idx + 1) % MFC_MAX_DRC_FRAME; + + if (!dec->disp_drc.disp_res_change) { + dec->disp_drc.push_idx = 0; + dec->disp_drc.pop_idx = 0; + } + + /* + * Do not clear WAIT_G_FMT except RUNNING state + * because the resolution change (DRC) case uses WAIT_G_FMT + */ + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_RUNNING) && + (ctx->wait_state & WAIT_G_FMT) != 0) { + ctx->wait_state &= ~(WAIT_G_FMT); + mfc_ctx_debug(2, "clear WAIT_G_FMT %d\n", ctx->wait_state); + MFC_TRACE_CTX("** DEC clear WAIT_G_FMT(wait_state %d)\n", ctx->wait_state); + } +} + +/* Get cropping information */ +static int mfc_dec_g_selection(struct file *file, void *priv, + struct v4l2_selection *s) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_dec *dec = ctx->dec_priv; + + mfc_ctx_debug_enter(); + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + mutex_lock(&ctx->drc_wait_mutex); + if (dec->disp_drc.disp_res_change) { + __mfc_dec_update_disp_res(ctx, s); + mutex_unlock(&ctx->drc_wait_mutex); + return 0; + } + mutex_unlock(&ctx->drc_wait_mutex); + + if (!NEED_TO_GET_CROP(core_ctx)) { + mfc_err("ready to get compose failed\n"); + return -EINVAL; + } + + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_RUNNING) && + dec->detect_black_bar && dec->black_bar_updated) { + s->r.left = dec->black_bar.left; + s->r.top = dec->black_bar.top; + s->r.width = dec->black_bar.width; + s->r.height = dec->black_bar.height; + mfc_debug(2, "[FRAME][BLACKBAR] Cropping info: l=%d t=%d w=%d h=%d\n", + dec->black_bar.left, + dec->black_bar.top, + dec->black_bar.width, + dec->black_bar.height); + } else { + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264 || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_HEVC) { + s->r.left = dec->cr_left; + s->r.top = dec->cr_top; + s->r.width = ctx->img_width - dec->cr_left - dec->cr_right; + s->r.height = ctx->img_height - dec->cr_top - dec->cr_bot; + mfc_debug(2, "[FRAME] %s: l=%d t=%d w=%d h=%d (r=%d b=%d fw=%d fh=%d)\n", + "Composing info", s->r.left, s->r.top, s->r.width, s->r.height, + dec->cr_right, dec->cr_bot, ctx->img_width, ctx->img_height); + } else { + s->r.left = 0; + s->r.top = 0; + s->r.width = ctx->img_width; + s->r.height = ctx->img_height; + mfc_debug(2, "[FRAME] Composing info: w=%d h=%d fw=%d fh=%d\n", + s->r.width, s->r.height, + ctx->img_width, ctx->img_height); + } + } + + mfc_ctx_debug_leave(); + return 0; +} + +static int mfc_dec_g_ext_ctrls(struct file *file, void *priv, + struct v4l2_ext_controls *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_ext_control *ext_ctrl; + struct v4l2_control ctrl; + int i; + int ret = 0; + + if (f->which != V4L2_CTRL_CLASS_CODEC && f->which != V4L2_CTRL_CLASS_USER) + return -EINVAL; + + for (i = 0; i < f->count; i++) { + ext_ctrl = (f->controls + i); + + ctrl.id = ext_ctrl->id; + + ret = __mfc_dec_get_ctrl_val(ctx, &ctrl); + if (ret == 0) { + ext_ctrl->value = ctrl.value; + } else { + f->error_idx = i; + break; + } + + mfc_ctx_debug(5, "[CTRLS][%d] id: %#x, value: %d\n", + i, ext_ctrl->id, ext_ctrl->value); + } + + return ret; +} + +/* Initialize for default format */ +void mfc_dec_set_default_format(struct mfc_ctx *ctx) +{ + struct mfc_fmt *fmt = NULL; + + /* Set default format for source */ + fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_H264); + if (!fmt) { + /* NEVER come here */ + mfc_ctx_err("Wrong memory access. Set fmt by mfc_formats[0]\n"); + fmt = &mfc_formats[0]; + } + ctx->src_fmt = fmt; + + /* Set default format for destination */ + fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M); + if (!fmt) { + /* NEVER come here */ + mfc_ctx_err("Wrong memory access. Set fmt by mfc_formats[0]\n"); + fmt = &mfc_formats[0]; + } + ctx->dst_fmt = fmt; +} + +/* v4l2_ioctl_ops */ +static const struct v4l2_ioctl_ops mfc_dec_ioctl_ops = { + .vidioc_querycap = mfc_dec_querycap, + .vidioc_enum_fmt_vid_cap = mfc_dec_enum_fmt_vid_cap_mplane, + .vidioc_enum_fmt_vid_out = mfc_dec_enum_fmt_vid_out_mplane, + .vidioc_g_fmt_vid_cap_mplane = mfc_dec_g_fmt_vid_cap_mplane, + .vidioc_g_fmt_vid_out_mplane = mfc_dec_g_fmt_vid_out_mplane, + .vidioc_try_fmt_vid_cap_mplane = mfc_dec_try_fmt, + .vidioc_try_fmt_vid_out_mplane = mfc_dec_try_fmt, + .vidioc_s_fmt_vid_cap_mplane = mfc_dec_s_fmt_vid_cap_mplane, + .vidioc_s_fmt_vid_out_mplane = mfc_dec_s_fmt_vid_out_mplane, + .vidioc_reqbufs = mfc_dec_reqbufs, + .vidioc_querybuf = mfc_dec_querybuf, + .vidioc_qbuf = mfc_dec_qbuf, + .vidioc_dqbuf = mfc_dec_dqbuf, + .vidioc_streamon = mfc_dec_streamon, + .vidioc_streamoff = mfc_dec_streamoff, + .vidioc_s_ext_ctrls = mfc_dec_s_ext_ctrls, + .vidioc_g_selection = mfc_dec_g_selection, + .vidioc_g_ext_ctrls = mfc_dec_g_ext_ctrls, +}; + +const struct v4l2_ioctl_ops *mfc_get_dec_v4l2_ioctl_ops(void) +{ + return &mfc_dec_ioctl_ops; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h new file mode 100644 index 000000000000..04652a71cd23 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * mfc_dec_v4l2.h + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __MFC_DEC_V4L2_H +#define __MFC_DEC_V4L2_H __FILE__ + +#include "base/mfc_common.h" + +const struct v4l2_ioctl_ops *mfc_get_dec_v4l2_ioctl_ops(void); +void mfc_dec_set_default_format(struct mfc_ctx *ctx); + +#endif /* __MFC_DEC_V4L2_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035641epcas5p4a5011f149b293c1b5aee60df0447666c@epcas5p4.samsung.com>]
* [PATCH 19/29] media: mfc: Add QoS, Butler workqueue, and priority‑based scheduling [not found] ` <CGME20250930035641epcas5p4a5011f149b293c1b5aee60df0447666c@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Integrate QoS handling (core, ops, PM). - Add Butler workqueue for core tasks (allocation, init, cleanup). - Implement async QoS control workqueue using atomic counters and proper sync. - Update probe to initialize workqueues, QoS structures, and improve logging. - Modify PM to trigger QoS updates on clock changes and issue idle‑clock QoS when bus devfreq is active. - Refactor scheduler for priority‑aware work handling via bit‑mask tracking. - Extend ops table with extra instance and buffer management. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/mfc_core.c | 145 +++++++ .../samsung/exynos-mfc/mfc_core_ops.c | 370 ++++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_core_pm.c | 25 ++ .../samsung/exynos-mfc/mfc_core_sched_prio.c | 331 ++++++++++++++++ .../samsung/exynos-mfc/mfc_dec_v4l2.c | 12 +- .../samsung/exynos-mfc/mfc_dec_v4l2.h | 12 +- 6 files changed, 881 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c index 4f5cf459c36f..af6fd088fad3 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c @@ -28,6 +28,7 @@ #include "mfc_core_ops.h" #include "mfc_core_isr.h" +#include "mfc_dec_v4l2.h" #include "mfc_debugfs.h" #include "mfc_core_hwlock.h" @@ -37,7 +38,9 @@ #include "mfc_core_hw_reg_api.h" +#include "base/mfc_qos.h" #include "base/mfc_sched.h" +#include "base/mfc_queue.h" #include "base/mfc_buf.h" #include "base/mfc_mem.h" @@ -45,6 +48,45 @@ struct _mfc_trace_logging g_mfc_core_trace_logging[MFC_TRACE_LOG_COUNT_MAX]; +static void mfc_core_butler_worker(struct work_struct *work) +{ + struct mfc_core *core; + + core = container_of(work, struct mfc_core, butler_work); + + mfc_core_try_run(core); +} + +static int __mfc_core_parse_mfc_qos_platdata(struct device_node *np, + char *node_name, + struct mfc_qos *qosdata, + struct mfc_core *core) +{ + struct device_node *np_qos; + + np_qos = of_find_node_by_name(NULL, node_name); + if (!np_qos) { + dev_err(core->device, + "%s: could not find mfc_qos_platdata node\n", + node_name); + return -EINVAL; + } + + of_property_read_u32(np_qos, "thrd_mb", &qosdata->threshold_mb); + of_property_read_u32(np_qos, "freq_mfc", &qosdata->freq_mfc); + of_property_read_u32(np_qos, "freq_int", &qosdata->freq_int); + of_property_read_u32(np_qos, "freq_mif", &qosdata->freq_mif); + of_property_read_u32(np_qos, "mo_value", &qosdata->mo_value); + of_property_read_u32(np_qos, "time_fw", &qosdata->time_fw); + + of_property_read_string(np_qos, "bts_scen", &qosdata->name); + if (!qosdata->name) { + mfc_pr_err("[QoS] bts_scen is missing in '%s' node", node_name); + return -EINVAL; + } + return 0; +} + #if (IS_ENABLED(CONFIG_SAMSUNG_IOMMU)) static int mfc_core_sysmmu_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, @@ -140,6 +182,9 @@ static int mfc_core_sysmmu_fault_handler(struct iommu_domain *domain, static int __mfc_core_parse_dt(struct device_node *np, struct mfc_core *core) { struct mfc_core_platdata *pdata = core->core_pdata; + struct device_node *np_qos; + char node_name[50]; + int i; if (!np) { mfc_pr_err("there is no device node\n"); @@ -164,6 +209,61 @@ static int __mfc_core_parse_dt(struct device_node *np, struct mfc_core *core) of_property_read_u32(np, "masterid_mask", &pdata->masterid_mask); of_property_read_u32(np, "tsmux_masterid", &pdata->tsmux_masterid); + /* QoS */ + of_property_read_u32(np, "num_default_qos_steps", + &pdata->num_default_qos_steps); + of_property_read_u32(np, "max_mb", &pdata->max_mb); + of_property_read_u32(np, "max_hw_mb", &pdata->max_hw_mb); + of_property_read_u32(np, "mfc_freq_control", &pdata->mfc_freq_control); + of_property_read_u32(np, "mo_control", &pdata->mo_control); + of_property_read_u32(np, "bw_control", &pdata->bw_control); + of_property_read_u32(np, "pm_qos_id", &pdata->pm_qos_id); + + pdata->default_qos_table = devm_kzalloc(core->device, + sizeof(struct mfc_qos) * + pdata->num_default_qos_steps, + GFP_KERNEL); + for (i = 0; i < pdata->num_default_qos_steps; i++) { + snprintf(node_name, sizeof(node_name), "mfc_d_qos_variant_%d", + i); + __mfc_core_parse_mfc_qos_platdata(np, node_name, + &pdata->default_qos_table[i], + core); + } + + /* performance boost mode */ + pdata->qos_boost_table = devm_kzalloc(core->device, + sizeof(struct mfc_qos_boost), + GFP_KERNEL); + np_qos = of_find_node_by_name(np, "mfc_perf_boost_table"); + if (!np_qos) { + dev_err(core->device, + "[QoS][BOOST] could not find mfc_perf_boost_table node\n"); + return -EINVAL; + } + of_property_read_u32(np_qos, "num_cluster", + &pdata->qos_boost_table->num_cluster); + of_property_read_u32_array(np_qos, "num_cpu", + &pdata->qos_boost_table->num_cpu[0], + pdata->qos_boost_table->num_cluster); + of_property_read_u32(np_qos, "freq_mfc", + &pdata->qos_boost_table->freq_mfc); + of_property_read_u32(np_qos, "freq_int", + &pdata->qos_boost_table->freq_int); + of_property_read_u32(np_qos, "freq_mif", + &pdata->qos_boost_table->freq_mif); + of_property_read_u32_array(np_qos, "freq_cluster", + &pdata->qos_boost_table->freq_cluster[0], + pdata->qos_boost_table->num_cluster); + + of_property_read_string(np_qos, "bts_scen", + &pdata->qos_boost_table->name); + if (!pdata->qos_boost_table->name) { + mfc_pr_err + ("[QoS][BOOST] bts_scen is missing in qos_boost node"); + return -EINVAL; + } + return 0; } @@ -274,6 +374,7 @@ static int mfc_core_probe(struct platform_device *pdev) struct mfc_core *core; struct mfc_dev *dev; int ret = -ENOENT; + int i; dev_info(&pdev->dev, "%s is called\n", __func__); @@ -325,6 +426,44 @@ static int mfc_core_probe(struct platform_device *pdev) spin_lock_init(&core->batch_lock); + /* core butler worker */ + core->butler_wq = alloc_workqueue("mfc_core/butler", WQ_UNBOUND + | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + if (!core->butler_wq) { + dev_err(&pdev->dev, "failed to create workqueue for butler\n"); + goto err_butler_wq; + } + INIT_WORK(&core->butler_work, mfc_core_butler_worker); + + /* core QoS control worker */ + core->qos_ctrl_wq = alloc_workqueue("mfc_core/qos_ctrl", WQ_UNBOUND + | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + if (!core->qos_ctrl_wq) { + dev_err(&pdev->dev, + "failed to create workqueue for QoS control\n"); + goto err_qos_ctrl_wq; + } +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + INIT_WORK(&core->qos_ctrl_work, mfc_qos_ctrl_worker); +#endif + + atomic_set(&core->qos_req_cur, 0); + mutex_init(&core->qos_mutex); + mutex_init(&core->pm_qos_mutex); + + mfc_core_info("[QoS] control: mfc_freq(%d), mo(%d), bw(%d)\n", + core->core_pdata->mfc_freq_control, + core->core_pdata->mo_control, + core->core_pdata->bw_control); + mfc_core_info("[QoS]-------------------Default table\n"); + for (i = 0; i < core->core_pdata->num_default_qos_steps; i++) + mfc_core_info + ("[QoS] table[%d] mfc: %d, int: %d, mif: %d, bts_scen: %s(%d)\n", + i, core->core_pdata->default_qos_table[i].freq_mfc, + core->core_pdata->default_qos_table[i].freq_int, + core->core_pdata->default_qos_table[i].freq_mif, + core->core_pdata->default_qos_table[i].name, + core->core_pdata->default_qos_table[i].bts_scen_idx); #if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) ret = samsung_iommu_register_fault_handler(core->device, mfc_core_sysmmu_fault_handler, @@ -365,6 +504,10 @@ static int mfc_core_probe(struct platform_device *pdev) samsung_iommu_unregister_fault_handler(&pdev->dev); err_sysmmu_fault_handler: #endif + destroy_workqueue(core->qos_ctrl_wq); + err_qos_ctrl_wq: + destroy_workqueue(core->butler_wq); + err_butler_wq: if (core->has_2sysmmu) iounmap(core->sysmmu1_base); iounmap(core->sysmmu0_base); @@ -388,6 +531,8 @@ static void mfc_core_remove(struct platform_device *pdev) #if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) samsung_iommu_unregister_fault_handler(&pdev->dev); #endif + flush_workqueue(core->butler_wq); + destroy_workqueue(core->butler_wq); mfc_core_destroy_listable_wq_core(core); mfc_release_common_context(core); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c index d9200bba1bb5..f8a27548b218 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c @@ -19,8 +19,10 @@ #include "mfc_core_hw_reg_api.h" #include "base/mfc_sched.h" +#include "base/mfc_qos.h" #include "base/mfc_buf.h" #include "base/mfc_utils.h" +#include "base/mfc_queue.h" #include "base/mfc_mem.h" static void __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) @@ -109,6 +111,8 @@ static int __mfc_core_deinit(struct mfc_core *core, struct mfc_ctx *ctx) if (core->num_inst == 0) { mfc_core_run_deinit_hw(core); + flush_workqueue(core->butler_wq); + mfc_debug(2, "power off\n"); mfc_core_pm_power_off(core); @@ -121,6 +125,40 @@ static int __mfc_core_deinit(struct mfc_core *core, struct mfc_ctx *ctx) } } + mfc_qos_off(core, ctx); + + return 0; +} + +static int __mfc_force_close_inst(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + enum mfc_inst_state prev_state; + + if (core_ctx->state == MFCINST_FREE) + return 0; + + prev_state = core_ctx->state; + mfc_change_state(core_ctx, MFCINST_RETURN_INST); + mfc_change_op_mode(ctx, MFC_OP_SINGLE); + core->sched->set_work(core, core_ctx); + mfc_clean_core_ctx_int_flags(core_ctx); + if (mfc_core_just_run(core, ctx->num)) { + mfc_err("Failed to run MFC\n"); + mfc_change_state(core_ctx, prev_state); + return -EIO; + } + + /* Wait until instance is returned or timeout occurred */ + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET)) { + mfc_err("Waiting for CLOSE_INSTANCE timed out\n"); + mfc_change_state(core_ctx, prev_state); + return -EIO; + } + + /* Free resources */ + mfc_release_instance_context(core_ctx); + return 0; } @@ -153,7 +191,12 @@ static int __mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx) init_waitqueue_head(&core_ctx->cmd_wq); mfc_core_init_listable_wq_ctx(core_ctx); + spin_lock_init(&core_ctx->buf_queue_lock); core->sched->clear_work(core, core_ctx); + INIT_LIST_HEAD(&core_ctx->qos_list); + INIT_LIST_HEAD(&core_ctx->mb_list); + + mfc_create_queue(&core_ctx->src_buf_queue); if (core->num_inst == 1) { mfc_debug(2, "it is first instance in to core-%d\n", core->id); @@ -252,6 +295,14 @@ static int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx) core->sched->clear_work(core, core_ctx); + /* If a H/W operation is in progress, wait for it complete */ + if (NEED_TO_WAIT_NAL_ABORT(core_ctx)) { + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_NAL_ABORT_RET)) { + mfc_err("Failed to wait nal abort\n"); + core->sched->yield_work(core, core_ctx); + } + } + ret = mfc_core_get_hwlock_ctx(core_ctx); if (ret < 0) { mfc_err("Failed to get hwlock\n"); @@ -265,9 +316,14 @@ static int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx) if (ret) goto err_release_try; + mfc_release_codec_buffers(core_ctx); + mfc_release_instance_context(core_ctx); + mfc_core_release_hwlock_ctx(core_ctx); mfc_core_destroy_listable_wq_ctx(core_ctx); + mfc_delete_queue(&core_ctx->src_buf_queue); + core->core_ctx[core_ctx->num] = 0; kfree(core_ctx); @@ -275,12 +331,326 @@ static int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx) err_release_try: mfc_core_release_hwlock_ctx(core_ctx); + core->sched->yield_work(core, core_ctx); + return ret; +} + +static int __mfc_core_instance_open_dec(struct mfc_ctx *ctx, + struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + int ret = 0; + + /* In case of calling s_fmt twice or more */ + ret = __mfc_force_close_inst(core, ctx); + if (ret) { + mfc_err("Failed to close already opening instance\n"); + mfc_core_release_hwlock_ctx(core_ctx); + core->sched->yield_work(core, core_ctx); + return -EIO; + } + + ret = mfc_alloc_instance_context(core_ctx); + if (ret) { + mfc_err("Failed to allocate dec instance[%d] buffers\n", + ctx->num); + mfc_core_release_hwlock_ctx(core_ctx); + return -ENOMEM; + } + + return 0; +} + +static int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + + if (!core_ctx) { + mfc_core_err("There is no instance\n"); + return -EINVAL; + } + + ret = mfc_core_get_hwlock_ctx(core_ctx); + if (ret < 0) { + mfc_err("Failed to get hwlock\n"); + return ret; + } + + if (ctx->type == MFCINST_DECODER) { + if (__mfc_core_instance_open_dec(ctx, core_ctx)) + return -EAGAIN; + } else { + mfc_err("invalid codec type: %d\n", ctx->type); + return -EINVAL; + } + + mfc_change_state(core_ctx, MFCINST_INIT); + core->sched->set_work(core, core_ctx); + ret = mfc_core_just_run(core, ctx->num); + if (ret) { + mfc_err("Failed to run MFC\n"); + goto err_open; + } + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_OPEN_INSTANCE_RET)) { + mfc_err("failed to wait OPEN_INSTANCE\n"); + mfc_change_state(core_ctx, MFCINST_FREE); + ret = -EIO; + goto err_open; + } + + mfc_core_release_hwlock_ctx(core_ctx); + + mfc_debug(2, "Got instance number inst_no: %d\n", core_ctx->inst_no); + + core->sched->enqueue_work(core, core_ctx); + if (core->sched->is_work(core)) + core->sched->queue_work(core); + + return ret; + +err_open: + mfc_core_release_hwlock_ctx(core_ctx); + core->sched->yield_work(core, core_ctx); + mfc_release_instance_context(core_ctx); + + return ret; +} + +static void mfc_core_instance_cache_flush(struct mfc_core *core, struct mfc_ctx *ctx) +{ + if (core->state == MFCCORE_ERROR) { + mfc_core_info("[MSR] Couldn't cache flush. It's Error state\n"); + return; + } + + core->curr_core_ctx = ctx->num; + + mfc_core_pm_clock_on(core, 0); + mfc_core_run_cache_flush + (core, + core->last_cmd_has_cache_flush ? MFC_NO_CACHEFLUSH : MFC_CACHEFLUSH, + 0); + mfc_core_pm_clock_off(core, 0); +} + +static int mfc_core_instance_move_to(struct mfc_core *core, struct mfc_ctx *ctx) +{ + int ret = 0; + + ret = __mfc_core_instance_init(core, ctx); + if (ret) { + mfc_core_err("Failed to core instance init\n"); + return ret; + } + + if (core->num_inst > 1) { + mfc_ctx_debug(2, "to core-%d already working, send cache_flush only\n", core->id); + mfc_core_instance_cache_flush(core, ctx); + } + + mfc_ctx_info("to core-%d is ready to move\n", core->id); + + return 0; +} + +static int mfc_core_instance_move_from(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret = 0; + int inst_no; + + mfc_clean_core_ctx_int_flags(core_ctx); + core->sched->set_work(core, core_ctx); + + ret = mfc_core_just_run(core, ctx->num); + if (ret) { + mfc_err("Failed to run MFC\n"); + return ret; + } + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_MOVE_INSTANCE_RET)) { + mfc_err("time out during move instance\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_MOVE_INST); + return -EFAULT; + } + inst_no = mfc_core_get_inst_no(); + + ret = __mfc_core_deinit(core, ctx); + if (ret) { + mfc_err("Failed to close instance\n"); + return ret; + } + + mfc_info("inst_no.%d will be changed to no.%d\n", core_ctx->inst_no, inst_no); + core_ctx->inst_no = inst_no; + return ret; } +static void mfc_core_instance_dpb_flush(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int index = 0, i, ret; + int prev_state; + + if (core->state == MFCCORE_ERROR || core_ctx->state == MFCINST_ERROR) + goto cleanup; + + ret = mfc_core_get_hwlock_ctx(core_ctx); + if (ret < 0) { + mfc_err("Failed to get hwlock\n"); + MFC_TRACE_CTX_LT("[ERR][Release] failed to get hwlock (shutdown: %d)\n", + core->shutdown); + if (core->shutdown) + goto cleanup; + return; + } + + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->err_buf_queue); + + mutex_lock(&dec->dpb_mutex); + for (i = 0; i < MFC_MAX_DPBS; i++) + dec->dpb[i].queued = 0; + mutex_unlock(&dec->dpb_mutex); + + dec->queued_dpb = 0; + ctx->is_dpb_realloc = 0; + dec->last_dpb_max_index = 0; + + if (!dec->inter_res_change) { + dec->dpb_table_used = 0; + dec->dynamic_used = 0; + if (dec->is_dynamic_dpb) { + mfc_cleanup_iovmm(ctx); + dec->dynamic_set = 0; + core_ctx->dynamic_set = 0; + } else { + dec->dynamic_set = MFC_ALL_AVAILABLE_DPB; + } + } else { + mfc_cleanup_iovmm_except_used(ctx); + mfc_print_dpb_table(ctx); + } + + while (index < MFC_MAX_BUFFERS) { + index = find_next_bit(ctx->dst_ctrls_avail, MFC_MAX_BUFFERS, index); + if (index < MFC_MAX_BUFFERS) + call_cop(ctx, reset_buf_ctrls, &ctx->dst_ctrls[index]); + index++; + } + + mutex_lock(&ctx->drc_wait_mutex); + if (ctx->wait_state & WAIT_STOP) { + ctx->wait_state &= ~(WAIT_STOP); + mfc_debug(2, "clear WAIT_STOP %d\n", ctx->wait_state); + MFC_TRACE_CORE_CTX("** DEC clear WAIT_STOP(wait_state %d)\n", + ctx->wait_state); + + if (ctx->ready_to_be_multi_view_enable) { + ctx->ready_to_be_multi_view_enable = 0; + ctx->multi_view_enable = 1; + mfc_debug(3, "[MV-HEVC] enabled\n"); + } + } + mutex_unlock(&ctx->drc_wait_mutex); + + if (core_ctx->state == MFCINST_FINISHING) + mfc_change_state(core_ctx, MFCINST_RUNNING); + + if (NEED_TO_DPB_FLUSH(core_ctx) && !ctx->dec_priv->inter_res_change) { + prev_state = core_ctx->state; + mfc_change_state(core_ctx, MFCINST_DPB_FLUSHING); + core->sched->set_work(core, core_ctx); + mfc_clean_core_ctx_int_flags(core_ctx); + mfc_info("try to DPB flush\n"); + ret = mfc_core_just_run(core, ctx->num); + if (ret) { + mfc_err("Failed to run MFC\n"); + mfc_core_release_hwlock_ctx(core_ctx); + core->sched->yield_work(core, core_ctx); + return; + } + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_DPB_FLUSH_RET)) { + mfc_err("time out during DPB flush\n"); + core->logging_data->cause |= BIT(MFC_CAUSE_FAIL_DPB_FLUSH); + } + + mfc_change_state(core_ctx, prev_state); + } + + mfc_debug(2, "decoder destination stop sequence done\n"); + + core->sched->clear_work(core, core_ctx); + mfc_core_release_hwlock_ctx(core_ctx); + + core->sched->enqueue_work(core, core_ctx); + if (core->sched->is_work(core)) + core->sched->queue_work(core); + + return; + +cleanup: + mfc_core_info("[MSR] Cleanup dst buffers. It's Error state\n"); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->err_buf_queue); +} + +static int mfc_core_instance_init_buf(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + + core->sched->set_work(core, core_ctx); + mfc_clean_core_ctx_int_flags(core_ctx); + if (mfc_core_just_run(core, ctx->num)) { + mfc_err("Failed to run MFC\n"); + return -EIO; + } + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_INIT_BUFFERS_RET)) { + mfc_err("[RM] init buffer timeout\n"); + return -EIO; + } + + return 0; +} + +static int mfc_core_request_work(struct mfc_core *core, + enum mfc_request_work work, + struct mfc_ctx *ctx) +{ + switch (work) { + case MFC_WORK_BUTLER: + mfc_core_debug(3, "request_work: butler\n"); + if (core->sched->is_work(core)) + core->sched->queue_work(core); + break; + case MFC_WORK_TRY: + mfc_core_debug(3, "request_work: try_run\n"); + mfc_core_try_run(core); + break; + default: + mfc_core_err("not supported request work type: %#x\n", work); + return -EINVAL; + } + + return 0; +} + static const struct mfc_core_ops mfc_core_ops = { .instance_init = mfc_core_instance_init, .instance_deinit = mfc_core_instance_deinit, + .instance_open = mfc_core_instance_open, + .instance_cache_flush = mfc_core_instance_cache_flush, + .instance_move_to = mfc_core_instance_move_to, + .instance_move_from = mfc_core_instance_move_from, + .instance_dpb_flush = mfc_core_instance_dpb_flush, + .instance_init_buf = mfc_core_instance_init_buf, + .request_work = mfc_core_request_work, }; const struct mfc_core_ops *mfc_get_core_ops(void) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c index def7ac2a2007..a70b2b472c06 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c @@ -16,6 +16,8 @@ #include "mfc_core_hw_reg_api.h" +#include "base/mfc_qos.h" + void mfc_core_pm_init(struct mfc_core *core) { spin_lock_init(&core->pm.clklock); @@ -78,6 +80,9 @@ int mfc_core_pm_clock_on(struct mfc_core *core, bool qos_update) mfc_core_debug(2, "clk_ref = %d\n", state); MFC_TRACE_LOG_CORE("clk_ref = %d", state); + if (qos_update && state == 1) + mfc_qos_update(core, 1); + return 0; } @@ -113,6 +118,9 @@ void mfc_core_pm_clock_off(struct mfc_core *core, bool qos_update) mfc_core_debug(2, "clk_ref = %d\n", state); MFC_TRACE_LOG_CORE("clk_ref = %d", state); + + if (qos_update && state == 0) + mfc_qos_update(core, 0); } int mfc_core_pm_power_on(struct mfc_core *core) @@ -126,6 +134,15 @@ int mfc_core_pm_power_on(struct mfc_core *core) goto err_power_on; } +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + if (core->dev->pdata->idle_clk_ctrl) { + mfc_core_debug(2, "request mfc idle clk OFF\n"); + exynos_pm_qos_add_request(&core->qos_req_mfc_noidle, + core->core_pdata->pm_qos_id, + core->dev->pdata->mfc_freqs[0]); + } +#endif + #if (IS_ENABLED(CONFIG_COMMON_CLK_SAMSUNG)) core->pm.clock = clk_get(core->device, "aclk_mfc"); if (IS_ERR(core->pm.clock)) { @@ -167,6 +184,14 @@ int mfc_core_pm_power_off(struct mfc_core *core) clk_unprepare(core->pm.clock); clk_put(core->pm.clock); } + +#ifdef CONFIG_MFC_USE_BUS_DEVFREQ + if (core->dev->pdata->idle_clk_ctrl) { + exynos_pm_qos_remove_request(&core->qos_req_mfc_noidle); + mfc_core_debug(2, "request mfc idle clk ON\n"); + } +#endif + mfc_core_mfc_always_off(core); ret = pm_runtime_put_sync(core->pm.device); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c index a2f69a064d3d..34731229338d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c @@ -13,6 +13,7 @@ #include "mfc_core_sync.h" #include "base/mfc_sched.h" +#include "base/mfc_qos.h" #include "base/mfc_utils.h" static inline void __mfc_print_workbits(struct mfc_core *core, int prio, int num) @@ -36,6 +37,42 @@ static inline void __mfc_clear_all_prio_bits(struct mfc_core *core) spin_unlock_irqrestore(&core->prio_work_lock, flags); } +static int __mfc_ctx_ready_set_bit_prio(struct mfc_core_ctx *core_ctx, bool set) + +{ + struct mfc_core *core; + struct mfc_ctx *ctx; + unsigned long flags; + int p, is_ready = 0; + + if (!core_ctx) { + mfc_pr_err("no mfc core_ctx device to run\n"); + return is_ready; + } + + core = core_ctx->core; + if (!core) { + mfc_err("no mfc core device to run\n"); + return is_ready; + } + + ctx = core_ctx->ctx; + if (!ctx) { + mfc_err("no mfc ctx device to run\n"); + return is_ready; + } + + spin_lock_irqsave(&core->prio_work_lock, flags); + + p = mfc_get_prio(core, ctx->rt, ctx->prio); + is_ready = mfc_ctx_ready_set_bit_raw(core_ctx, &core->prio_work_bits[p], set); + __mfc_print_workbits(core, p, core_ctx->num); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + return is_ready; +} + static void mfc_create_work_prio(struct mfc_core *core) { int num_prio = core->dev->pdata->pbs_num_prio; @@ -61,6 +98,27 @@ static void mfc_clear_all_work_prio(struct mfc_core *core) __mfc_clear_all_prio_bits(core); } +static int mfc_is_work_prio(struct mfc_core *core) +{ + unsigned long flags; + int i, ret = 0; + + spin_lock_irqsave(&core->prio_work_lock, flags); + for (i = 0; i < core->total_num_prio; i++) { + if (core->prio_work_bits[i]) { + ret = 1; + break; + } + } + spin_unlock_irqrestore(&core->prio_work_lock, flags); + return ret; +} + +static void mfc_queue_work_prio(struct mfc_core *core) +{ + queue_work(core->butler_wq, &core->butler_work); +} + static void mfc_set_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) { struct mfc_ctx *ctx = core_ctx->ctx; @@ -91,10 +149,283 @@ static void mfc_clear_work_prio(struct mfc_core *core, struct mfc_core_ctx *core spin_unlock_irqrestore(&core->prio_work_lock, flags); } +static int mfc_enqueue_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + return __mfc_ctx_ready_set_bit_prio(core_ctx, true); +} + +static int mfc_dequeue_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + return __mfc_ctx_ready_set_bit_prio(core_ctx, false); +} + +static void mfc_yield_work_prio(struct mfc_core *core, struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + int p; + + spin_lock_irqsave(&core->prio_work_lock, flags); + + p = mfc_get_prio(core, ctx->rt, ctx->prio); + __clear_bit(core_ctx->num, &core->prio_work_bits[p]); + __mfc_print_workbits(core, p, core_ctx->num); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + mfc_core_try_run(core); +} + +static unsigned long __mfc_check_lower_prio_inst(struct mfc_core *core, int prio) +{ + unsigned long sum = 0; + int i; + + for (i = prio + 1; i < core->total_num_prio; i++) + sum |= core->prio_work_bits[i]; + + return sum; +} + +static void __mfc_update_max_runtime(struct mfc_core *core, unsigned long bits) +{ + struct mfc_core_ctx *core_ctx; + int max_runtime = 0, runtime; + int i, num; + + if (core->dev->debugfs.sched_perf_disable) + return; + + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (test_bit(i, &bits)) { + core_ctx = core->core_ctx[i]; + if (!core_ctx) + continue; + /* if runtime is 0, use default 30fps (33msec) */ + runtime = core_ctx->avg_runtime ? core_ctx->avg_runtime : + MFC_DEFAULT_RUNTIME; + if (runtime > max_runtime) { + max_runtime = runtime; + num = i; + } + } + } + + if (max_runtime) + mfc_core_debug(2, "[PRIO][c:%d] max runtime is %d usec\n", num, max_runtime); + + core->max_runtime = max_runtime; +} + +static int __mfc_core_get_new_ctx_prio(struct mfc_core *core, int prio, int *highest, + bool predict) +{ + struct mfc_core_ctx *core_ctx; + unsigned long bits = 0; + int new_ctx_index; + int i, perf = 0, skip_curr; + + new_ctx_index = (core->last_core_ctx[prio] + 1) % MFC_NUM_CONTEXTS; + + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (test_bit(new_ctx_index, &core->prio_work_bits[prio])) { + if (*highest < 0) + *highest = new_ctx_index; + + /* If predict, do not get curr ctx */ + skip_curr = 0; + if (predict && new_ctx_index == core->curr_core_ctx) { + mfc_core_debug(2, "[PRIO][PREDICT](%d) skip curr ctx %d\n", + prio, new_ctx_index); + skip_curr = 1; + } + + /* If the performance is insufficient, run this */ + core_ctx = core->core_ctx[new_ctx_index]; + perf = mfc_rate_check_perf_ctx(core_ctx->ctx, core->max_runtime); + if (!perf && !skip_curr) { + mfc_core_debug(2, "[PRIO]%s(%d) perf insufficient: %d\n", + (predict ? "[PREDICT]" : ""), + prio, new_ctx_index); + return new_ctx_index; + } + + /* If the perf of all instances is satisfied, run the highest */ + bits |= BIT(new_ctx_index); + if (((core->prio_work_bits[prio] & ~(bits)) == 0) && + !__mfc_check_lower_prio_inst(core, prio)) { + mfc_core_debug(2, "[PRIO]%s(%d) the highest priority %d\n", + (predict ? "[PREDICT]" : ""), + prio, *highest); + return *highest; + } + } + /* If there is no ready context in prio, return */ + if ((core->prio_work_bits[prio] & ~(bits)) == 0) + return -1; + + new_ctx_index = (new_ctx_index + 1) % MFC_NUM_CONTEXTS; + } + + return -1; +} + +/* This should be called with prio_work_lock */ +static int __mfc_core_get_new_ctx(struct mfc_core *core, bool predict) +{ + int new_ctx_index = 0, highest = -1; + int i; + + for (i = 0; i < core->total_num_prio; i++) { + if (!core->prio_work_bits[i]) + continue; + + mfc_core_debug(2, "[PRIO]%s(%d) Previous context: %d (bits %08lx)\n", + (predict ? "[PREDICT]" : ""), + i, core->last_core_ctx[i], core->prio_work_bits[i]); + + new_ctx_index = __mfc_core_get_new_ctx_prio(core, i, &highest, predict); + if (new_ctx_index >= 0) { + mfc_core_debug(2, "[PRIO]%s(%d) get new_ctx %d\n", + (predict ? "[PREDICT]" : ""), i, new_ctx_index); + return new_ctx_index; + } + } + + return -1; +} + +static int mfc_pick_next_work_prio(struct mfc_core *core) +{ + unsigned long flags, work_bits, hweight; + int new_ctx_index = -1; + + if (!mfc_is_work_prio(core)) { + mfc_core_debug(2, "[PRIO] No ctx to run\n"); + return -EAGAIN; + } + + if (core->preempt_core_ctx > MFC_NO_INSTANCE_SET) { + new_ctx_index = core->preempt_core_ctx; + mfc_core_debug(2, "[PRIO] preempt_core_ctx %d\n", new_ctx_index); + return new_ctx_index; + } + + spin_lock_irqsave(&core->prio_work_lock, flags); + + work_bits = __mfc_check_lower_prio_inst(core, -1); + mfc_core_debug(2, "[PRIO] all work_bits %#lx\n", work_bits); + + /* if single instance is ready, run it */ + hweight = hweight64(work_bits); + if (hweight == 1) { + new_ctx_index = __ffs(work_bits); + mfc_core_debug(2, "[PRIO] new_ctx_idx %d (single)\n", new_ctx_index); + spin_unlock_irqrestore(&core->prio_work_lock, flags); + return new_ctx_index; + } + + __mfc_update_max_runtime(core, work_bits); + + /* if there is predicted next ctx, run it */ + if (core->next_ctx_idx >= 0 && test_bit(core->next_ctx_idx, &work_bits)) { + new_ctx_index = core->next_ctx_idx; + mfc_core_debug(2, "[PRIO] new_ctx_idx %d (predict)\n", new_ctx_index); + spin_unlock_irqrestore(&core->prio_work_lock, flags); + return new_ctx_index; + } + + new_ctx_index = __mfc_core_get_new_ctx(core, 0); + mfc_core_debug(2, "[PRIO] new_ctx_idx %d\n", new_ctx_index); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + return new_ctx_index; +} + +static int mfc_get_next_work_prio(struct mfc_core *core) +{ + unsigned long flags, work_bits, hweight; + int new_ctx_index; + + if (core->dev->num_inst) + return -1; + + spin_lock_irqsave(&core->prio_work_lock, flags); + + work_bits = __mfc_check_lower_prio_inst(core, -1); + hweight = hweight64(work_bits); + /* Nothing to predict because only one instance is ready */ + if (hweight <= 1) { + spin_unlock_irqrestore(&core->prio_work_lock, flags); + return -1; + } + + new_ctx_index = __mfc_core_get_new_ctx(core, 1); + core->next_ctx_idx = new_ctx_index; + mfc_core_debug(2, "[PRIO][PREDICT] new_ctx_idx %d\n", new_ctx_index); + + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + return new_ctx_index; +} + +static int mfc_change_prio_work_prio(struct mfc_core *core, struct mfc_ctx *ctx, + int cur_rt, int cur_prio, int new_rt, int new_prio) +{ + unsigned long flags; + int cur_p, new_p; + + spin_lock_irqsave(&core->prio_work_lock, flags); + + if (new_prio > core->num_prio) + new_prio = core->num_prio; + + /* Check current priority's work_bit */ + cur_p = mfc_get_prio(core, cur_rt, cur_prio); + new_p = mfc_get_prio(core, new_rt, new_prio); + if (cur_p == new_p) { + ctx->prio = new_prio; + ctx->rt = new_rt; + spin_unlock_irqrestore(&core->prio_work_lock, flags); + return 0; + } + + mfc_core_debug(2, "[PRIO] cur_p %d -> new_p %d is changed (%d %d -> %d %d)\n", + cur_p, new_p, cur_rt, cur_prio, new_rt, new_prio); + + if (test_bit(ctx->num, &core->prio_work_bits[cur_p])) { + __clear_bit(ctx->num, &core->prio_work_bits[cur_p]); + mfc_core_debug(2, "[PRIO][c:%d] prio change from %d (bits %08lx)\n", + ctx->num, cur_p, core->prio_work_bits[cur_p]); + + /* Update current priority's work_bit */ + __set_bit(ctx->num, &core->prio_work_bits[new_p]); + mfc_core_debug(2, "[PRIO][c:%d] prio change to %d (bits %08lx)\n", + ctx->num, new_p, core->prio_work_bits[new_p]); + } + + /* These must be updated within the spin_lock for synchronization. */ + ctx->prio = new_prio; + ctx->rt = new_rt; + + spin_unlock_irqrestore(&core->prio_work_lock, flags); + + return 0; +} + struct mfc_sched_class mfc_sched_prio = { .create_work = mfc_create_work_prio, .init_work = mfc_init_work_prio, .clear_all_work = mfc_clear_all_work_prio, + .queue_work = mfc_queue_work_prio, + .is_work = mfc_is_work_prio, + .pick_next_work = mfc_pick_next_work_prio, + .get_next_work = mfc_get_next_work_prio, .set_work = mfc_set_work_prio, .clear_work = mfc_clear_work_prio, + .enqueue_work = mfc_enqueue_work_prio, + .dequeue_work = mfc_dequeue_work_prio, + .yield_work = mfc_yield_work_prio, + .change_prio_work = mfc_change_prio_work_prio, }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c index dd59dc352e34..8eb68294c0b1 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c @@ -1,14 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * mfc_dec_v4l2.c - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * mfc_dec_v4l2.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> */ #include <linux/vmalloc.h> diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h index 04652a71cd23..08fe4ed5cf3f 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later * - * mfc_dec_v4l2.h - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * Copyright (c) 2025 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * mfc_dec_v4l2.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> */ #ifndef __MFC_DEC_V4L2_H -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035644epcas5p178155478c949c231c14a131b00f23bc1@epcas5p1.samsung.com>]
* [PATCH 20/29] media: mfc: Add H264 decoder support [not found] ` <CGME20250930035644epcas5p178155478c949c231c14a131b00f23bc1@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Extend device‑tree with properties for secure firmware, DRM, codec capabilities, format/stride, resolution checks, and security controls. - Introduce per‑codec and device‑wide bitrate limits. - Implement runtime management: scheduler workers, dedicated workqueues, and required mutex/spinlock synchronization. - Refine decoder‑context handling (full init/cleanup, CRC dump, DPB handling, vb2 queue setup, QoS parsing). - Add polling with error‑state handling. - Expand DebugFS to expose core‑balance, feature flags, format support, QoS data, and queue metrics. - Update macros, include missing headers, improve logging, adjust scheduler/PBS configuration, and revise buffer‑size structures. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 443 ++++++++++++++++++ .../media/platform/samsung/exynos-mfc/mfc.c | 420 ++++++++++++++++- .../platform/samsung/exynos-mfc/mfc_debugfs.c | 60 ++- 3 files changed, 915 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi index 49c61958467e..40cac2b20804 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi @@ -67,25 +67,142 @@ mfc: mfc@19cd0000 { /* MFC version */ ip_ver = <0x1600010C>; + /* Secure Firmware Loading */ + secure_fw_loading = <1>; + /* MFC firmware name */ fw_name = "mfc_fw_v16.0.bin"; /* Debug mode */ debug_mode = <1>; + max_num_drm_inst = <3>; + + /* NAL-Q size */ + nal_q_entry_size = <768>; + nal_q_dump_size = <376>; + /* Features <on/off version> */ + skype = <1 0x0>; + black_bar = <1 0x0>; + color_aspect_dec = <1 0x0>; + static_info_dec = <1 0x0>; + color_aspect_enc = <1 0x0>; + static_info_enc = <1 0x180314>; + vp9_stride_align = <1 0x0>; mem_clear = <1 0x0>; /* Support from v11.0 (except 11.2) */ wait_fw_status = <1 0x190122>; + /* DRM switch predict for cache flush */ + drm_switch_predict = <1 0x0>; + /* Use metadata interface */ + metadata_interface = <1 0x200910>; + /* Average QP of encoder per frame */ + average_qp = <1 0x201030>; + /* MV search mode */ + mv_search_mode = <1 0x201118>; + /* Encoder IDR flag */ + enc_idr_flag = <1 0x210611>; + /* Encoder min quality mode */ + min_quality_mode = <1 0x210705>; + /* Encoder time stamp delta */ + enc_ts_delta = <1 0x211027>; + /* Encoder I limit RC mode for WFD */ + wfd_rc_mode = <1 0x211229>; /* Scheduler 0: round-robin, 1: PBS */ scheduler = <1>; /* The number of priority in PBS */ pbs_num_prio = <1>; + /* Support AV1 Film Grain Feature */ + av1_film_grain = <1 0x200717>; + + /* Decoder stride align (default: 16, AMD GPU: 256) */ + stride_align = <256>; + /* Decoder stride calculation type (new: 1, old: 0) */ + stride_type = <1>; + + /* Formats */ + support_10bit = <1>; + support_422 = <0>; + support_rgb = <1>; + + /* Resolution check (0: do not check, 1: FHD, 2: 4K, 3: 8K) */ + support_check_res = <3>; + + /* error type for sync_point display */ + /* (1: concealment display, 2: error display, 3: error no display) */ + display_err_type = <2>; + + /* FW base security ctrl */ + security_ctrl = <1>; + /* output buffer Q framerate */ + display_framerate = <0>; + + /* Encoder default parameter: max number is 100 */ + enc_param_num = <25>; + enc_param_addr = <0xF7B4 0xF7B8 0xF7B0 0xF798 0xFA2C + 0xF790 0xFA34 0xFA38 0xFA3C 0xF7C0 + 0xF7C8 0xF7CC 0xFA60 0xFDD4 0xFDDC + 0xFB54 0xFB58 0xFBA8 0xFD90 0xFD94 + 0xFD40 0xFD48 0xFD4C 0xFD50 0xFD80>; + enc_param_val = <0x80 0x80 0x0 0x4000 0x3FD00 + 0x0 0x0 0x2710 0x3E8 0x0 + 0x0 0x0 0x0 0x8050D211 0x0 + 0x3011 0x0 0x0 0x2D 0xA00 + 0x1D 0xF4240 0x33003300 0x2 0x1>; + + /* BW <peak, read, write> : KB/UHD frame */ + bw_enc_h264 = <45456 56112 11170>; + bw_enc_hevc = <46756 52766 9763>; + bw_enc_hevc_10bit = <53865 64753 12556>; + bw_enc_vp8 = <64000 67318 22518>; + bw_enc_vp9 = <72326 59726 16530>; + bw_enc_vp9_10bit = <149085 114928 31419>; + bw_enc_mpeg4 = <44647 55324 9531>; + bw_dec_h264 = <32605 34381 21263>; + bw_dec_hevc = <29973 28851 17538>; + bw_dec_hevc_10bit = <52859 46245 31351>; + bw_dec_vp8 = <28672 30468 22324>; + bw_dec_vp9 = <18351 18947 16877>; + bw_dec_vp9_10bit = <42384 34452 31766>; + bw_dec_av1 = <23787 19570 15856>; + bw_dec_av1_10bit = <41407 35490 29699>; + bw_dec_mpeg4 = <31540 25368 15770>; + + /* QoS bitrate */ + num_mfc_freq = <7>; + mfc_freqs = <160000 267000 332000 400000 533000 664000 800000>; + + /* QoS weight (%) */ + dynamic_weight = <1>; + qos_weight_h264_hevc = <100>; + qos_weight_vp8_vp9 = <100>; + qos_weight_av1 = <70>; + qos_weight_other_codec = <25>; + qos_weight_3plane = <80>; + qos_weight_10bit = <75>; + qos_weight_422 = <70>; + qos_weight_bframe = <50>; + qos_weight_num_of_ref = <60>; + qos_weight_gpb = <50>; + qos_weight_num_of_tile = <75>; + qos_weight_super64_bframe = <60>; + qos_weight_mbaff = <60>; + + /* core balance(%) for resource managing */ + core_balance = <54>; + /* MFC IOVA threshold (MB) */ iova_threshold = <1700>; + /* need control for mfc idle clock */ + idle_clk_ctrl = <1>; + + /* QoS level for pm_qos dynamic control */ + qos_ctrl_level = <1>; + /* Sub nodes for MFC core */ #address-cells = <2>; #size-cells = <2>; @@ -135,6 +252,15 @@ mfc_core0: MFC-0@19cd0000 { axid_mask = <0xFFFF>; tsmux_axid = <0x1>; + /* QoS */ + num_default_qos_steps = <10>; + num_encoder_qos_steps = <7>; + max_mb = <5093269>; + max_hw_mb = <3888000>; + mfc_freq_control = <1>; + mo_control = <1>; + bw_control = <1>; + /* mem-log buffer size */ memlog_size = <0x80000>; memlog_sfr_size = <0x1000>; @@ -148,6 +274,160 @@ mfc_core0: MFC-0@19cd0000 { iommu@19c70000 { reg = <0x0 0x19C70000 0x0 0x9000>; }; + + /* Default QoS table */ + mfc_default_qos_table { + mfc_d_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <133000>; + freq_int = <133000>; + freq_mif = <421000>; + bts_scen = "default"; + time_fw = <1238>; + }; + mfc_d_qos_variant_1 { + thrd_mb = <546599>; + freq_mfc = <267000>; + freq_int = <133000>; + freq_mif = <546000>; + bts_scen = "default"; + time_fw = <842>; + }; + mfc_d_qos_variant_2 { + thrd_mb = <1167159>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <676000>; + bts_scen = "default"; + time_fw = <667>; + }; + mfc_d_qos_variant_3 { + thrd_mb = <1859381>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <578>; + }; + mfc_d_qos_variant_4 { + thrd_mb = <2078433>; + freq_mfc = <468000>; + freq_int = <200000>; + freq_mif = <1014000>; + bts_scen = "default"; + time_fw = <483>; + }; + mfc_d_qos_variant_5 { + thrd_mb = <2563082>; + freq_mfc = <533000>; + freq_int = <332000>; + freq_mif = <1352000>; + bts_scen = "default"; + time_fw = <362>; + }; + mfc_d_qos_variant_6 { + thrd_mb = <3173773>; + freq_mfc = <663000>; + freq_int = <400000>; + freq_mif = <1352000>; + bts_scen = "default"; + time_fw = <306>; + }; + mfc_d_qos_variant_7 { + thrd_mb = <3716529>; + freq_mfc = <745000>; + freq_int = <533000>; + freq_mif = <1539000>; + bts_scen = "default"; + time_fw = <267>; + }; + mfc_d_qos_variant_8 { + thrd_mb = <4282126>; + freq_mfc = <745000>; + freq_int = <663000>; + freq_mif = <2028000>; + bts_scen = "default"; + time_fw = <235>; + }; + mfc_d_qos_variant_9 { + thrd_mb = <4855818>; + freq_mfc = <800000>; + freq_int = <800000>; + freq_mif = <3172000>; + bts_scen = "mfc_uhd_10bit"; + time_fw = <175>; + }; + }; + + /* Encoder only QoS table */ + mfc_encoder_qos_table { + mfc_e_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <133000>; + freq_int = <133000>; + freq_mif = <421000>; + bts_scen = "default"; + time_fw = <1238>; + }; + mfc_e_qos_variant_1 { + thrd_mb = <546599>; + freq_mfc = <267000>; + freq_int = <133000>; + freq_mif = <546000>; + bts_scen = "default"; + time_fw = <842>; + }; + mfc_e_qos_variant_2 { + thrd_mb = <1167159>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <676000>; + bts_scen = "default"; + time_fw = <667>; + }; + mfc_e_qos_variant_3 { + thrd_mb = <1859381>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <578>; + }; + mfc_e_qos_variant_4 { + thrd_mb = <2078433>; + freq_mfc = <533000>; + freq_int = <400000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <471>; + }; + mfc_e_qos_variant_5 { + thrd_mb = <2553457>; + freq_mfc = <468000>; + freq_int = <332000>; + freq_mif = <1539000>; + bts_scen = "mfc_uhd"; + time_fw = <359>; + }; + mfc_e_qos_variant_6 { + thrd_mb = <3175870>; + freq_mfc = <663000>; + freq_int = <663000>; + freq_mif = <1716000>; + bts_scen = "default"; + time_fw = <287>; + }; + }; + + /* QoS table for performance boost mode */ + mfc_perf_boost_table { + num_cluster = <3>; + freq_cluster = <1742000 1898000 1456000>; + freq_mfc = <666000>; + freq_int = <534000>; + freq_mif = <2730000>; + bts_scen = "mfc_uhd_10bit"; + }; }; mfc_core1: MFC-1@19ed0000 { @@ -173,6 +453,15 @@ mfc_core1: MFC-1@19ed0000 { share_sysmmu = <0>; axid_mask = <0xFFFF>; + /* QoS */ + num_default_qos_steps = <10>; + num_encoder_qos_steps = <7>; + max_mb = <5315425>; + max_hw_mb = <3888000>; + mfc_freq_control = <1>; + mo_control = <1>; + bw_control = <1>; + /* Device virtual address */ #dma-address-cells = <1>; #dma-size-cells = <1>; @@ -182,6 +471,160 @@ mfc_core1: MFC-1@19ed0000 { iommu@19e70000 { reg = <0x0 0x19E70000 0x0 0x9000>; }; + + /* Default QoS table */ + mfc_default_qos_table { + mfc_d_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <133000>; + freq_int = <133000>; + freq_mif = <421000>; + bts_scen = "default"; + time_fw = <1238>; + }; + mfc_d_qos_variant_1 { + thrd_mb = <546599>; + freq_mfc = <234000>; + freq_int = <133000>; + freq_mif = <546000>; + bts_scen = "default"; + time_fw = <842>; + }; + mfc_d_qos_variant_2 { + thrd_mb = <1167159>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <676000>; + bts_scen = "default"; + time_fw = <667>; + }; + mfc_d_qos_variant_3 { + thrd_mb = <1859381>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <578>; + }; + mfc_d_qos_variant_4 { + thrd_mb = <2078433>; + freq_mfc = <468000>; + freq_int = <200000>; + freq_mif = <1014000>; + bts_scen = "default"; + time_fw = <483>; + }; + mfc_d_qos_variant_5 { + thrd_mb = <2563082>; + freq_mfc = <533000>; + freq_int = <332000>; + freq_mif = <1352000>; + bts_scen = "default"; + time_fw = <362>; + }; + mfc_d_qos_variant_6 { + thrd_mb = <3173773>; + freq_mfc = <663000>; + freq_int = <400000>; + freq_mif = <1352000>; + bts_scen = "default"; + time_fw = <306>; + }; + mfc_d_qos_variant_7 { + thrd_mb = <3716529>; + freq_mfc = <745000>; + freq_int = <533000>; + freq_mif = <1539000>; + bts_scen = "default"; + time_fw = <267>; + }; + mfc_d_qos_variant_8 { + thrd_mb = <4282126>; + freq_mfc = <745000>; + freq_int = <663000>; + freq_mif = <2028000>; + bts_scen = "default"; + time_fw = <235>; + }; + mfc_d_qos_variant_9 { + thrd_mb = <4855818>; + freq_mfc = <800000>; + freq_int = <800000>; + freq_mif = <3172000>; + bts_scen = "mfc_8k_dec30"; + time_fw = <175>; + }; + }; + + /* Encoder only QoS table */ + mfc_encoder_qos_table { + mfc_e_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <133000>; + freq_int = <133000>; + freq_mif = <421000>; + bts_scen = "default"; + time_fw = <1238>; + }; + mfc_e_qos_variant_1 { + thrd_mb = <546599>; + freq_mfc = <267000>; + freq_int = <133000>; + freq_mif = <546000>; + bts_scen = "default"; + time_fw = <842>; + }; + mfc_e_qos_variant_2 { + thrd_mb = <1167159>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <676000>; + bts_scen = "default"; + time_fw = <667>; + }; + mfc_e_qos_variant_3 { + thrd_mb = <1859381>; + freq_mfc = <332000>; + freq_int = <200000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <578>; + }; + mfc_e_qos_variant_4 { + thrd_mb = <2078433>; + freq_mfc = <533000>; + freq_int = <400000>; + freq_mif = <845000>; + bts_scen = "default"; + time_fw = <471>; + }; + mfc_e_qos_variant_5 { + thrd_mb = <2553457>; + freq_mfc = <468000>; + freq_int = <332000>; + freq_mif = <1539000>; + bts_scen = "mfc_uhd"; + time_fw = <359>; + }; + mfc_e_qos_variant_6 { + thrd_mb = <3175870>; + freq_mfc = <663000>; + freq_int = <663000>; + freq_mif = <1716000>; + bts_scen = "default"; + time_fw = <287>; + }; + }; + + /* QoS table for performance boost mode */ + mfc_perf_boost_table { + num_cluster = <3>; + freq_cluster = <1742000 1898000 1456000>; + freq_mfc = <666000>; + freq_int = <534000>; + freq_mif = <2730000>; + bts_scen = "mfc_uhd_10bit"; + }; }; }; }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc.c b/drivers/media/platform/samsung/exynos-mfc/mfc.c index b5b66083cc8b..fb9a7317e812 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc.c @@ -21,6 +21,8 @@ #include <linux/poll.h> #include <linux/iommu.h> +#include "mfc_dec_v4l2.h" +#include "mfc_dec_vb2.h" #include "mfc_rm.h" #include "mfc_debugfs.h" @@ -29,6 +31,9 @@ #include "mfc_core_hw_reg_api.h" +#include "base/mfc_qos.h" + +#include "base/mfc_queue.h" #include "base/mfc_utils.h" #include "base/mfc_buf.h" #include "base/mfc_mem.h" @@ -41,6 +46,188 @@ struct _mfc_trace g_mfc_trace[MFC_TRACE_COUNT_MAX]; struct _mfc_trace g_mfc_trace_rm[MFC_TRACE_COUNT_MAX]; struct _mfc_trace g_mfc_trace_longterm[MFC_TRACE_COUNT_MAX]; +static void mfc_butler_worker(struct work_struct *work) +{ + struct mfc_dev *dev; + struct mfc_ctx *ctx; + int i; + + dev = container_of(work, struct mfc_dev, butler_work); + + /* If there is multi core instance, it has high priority */ + if (dev->multi_core_inst_bits) { + bool is_switch_to_single; + bool is_multi_mode; + + i = __ffs(dev->multi_core_inst_bits); + ctx = dev->ctx[i]; + if (!ctx) { + mfc_dev_err("[RM] There is no ctx\n"); + return; + } + + /* [DRC] In the case of MFC_OP_SWITCH_TO_SINGLE, + * also need to request with MFC_WORK_TRY. + * Because op_mode is maintained as MFC_OP_SWITCH_TO_SINGLE before subcore_deinit. + * And, subcore_deinit can be started by MFC_WORK_TRY. + */ + is_multi_mode = IS_MULTI_MODE(ctx); + is_switch_to_single = + (ctx->op_mode == MFC_OP_SWITCH_TO_SINGLE && ctx->handle_drc_multi_mode); + if (!is_multi_mode && !is_switch_to_single) + return; + + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + } else { + mfc_rm_request_work(dev, MFC_WORK_BUTLER, NULL); + } +} + +static void __mfc_deinit_dec_ctx(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec = ctx->dec_priv; + unsigned int size; + + if (dec->crc && (ctx->dev->debugfs.sfr_dump & MFC_DUMP_DEC_CRC)) { + if (dec->crc_idx * 4 > SZ_1K) + size = SZ_1K; + else + size = dec->crc_idx * 4; + print_hex_dump + (KERN_ERR, "CRC: ", DUMP_PREFIX_OFFSET, 32, 1, + dec->crc, size, false); + vfree(dec->crc); + } + + mfc_cleanup_iovmm(ctx); + + mfc_delete_queue(&ctx->src_buf_ready_queue); + mfc_delete_queue(&ctx->dst_buf_queue); + mfc_delete_queue(&ctx->err_buf_queue); + mfc_delete_queue(&ctx->meminfo_inbuf_q); + + mfc_mem_cleanup_user_shared_handle(ctx, &dec->sh_handle_dpb); + if (dec->ref_info) + vfree(dec->ref_info); + + kfree(dec); +} + +static int __mfc_init_dec_ctx(struct mfc_ctx *ctx) +{ + struct mfc_dec *dec; + int ret = 0; + int i; + + dec = kzalloc(sizeof(*dec), GFP_KERNEL); + if (!dec) + return -ENOMEM; + + ctx->dec_priv = dec; + + ctx->subcore_inst_no = MFC_NO_INSTANCE_SET; + ctx->curr_src_index = -1; + ctx->user_prio = -1; + + mfc_create_queue(&ctx->src_buf_ready_queue); + mfc_create_queue(&ctx->dst_buf_queue); + mfc_create_queue(&ctx->err_buf_queue); + mfc_create_queue(&ctx->meminfo_inbuf_q); + + for (i = 0; i < MFC_MAX_BUFFERS; i++) { + INIT_LIST_HEAD(&ctx->src_ctrls[i]); + INIT_LIST_HEAD(&ctx->dst_ctrls[i]); + } + bitmap_zero(ctx->src_ctrls_avail, MFC_MAX_BUFFERS); + bitmap_zero(ctx->dst_ctrls_avail, MFC_MAX_BUFFERS); + + ctx->capture_state = QUEUE_FREE; + ctx->output_state = QUEUE_FREE; + + ctx->type = MFCINST_DECODER; + ctx->c_ops = &mfc_ctrls_ops; + ctx->b_ops = &mfc_bufs_ops; + + mfc_dec_set_default_format(ctx); + mfc_rate_reset_framerate(ctx); + + ctx->qos_ratio = 100; + INIT_LIST_HEAD(&ctx->bitrate_list); + INIT_LIST_HEAD(&ctx->src_ts.ts_list); + + dec->display_delay = -1; + dec->is_interlaced = 0; + dec->immediate_display = 0; + dec->is_dts_mode = 0; + dec->inter_res_change = 0; + dec->disp_drc.disp_res_change = 0; + dec->disp_drc.push_idx = 0; + dec->disp_drc.pop_idx = 0; + + dec->is_dynamic_dpb = 1; + dec->dynamic_used = 0; + dec->is_dpb_full = 0; + dec->queued_dpb = 0; + dec->display_index = -1; + dec->dpb_table_used = 0; + dec->sh_handle_dpb.fd = -1; + mutex_init(&dec->dpb_mutex); + + mfc_init_dpb_table(ctx); + + dec->sh_handle_dpb.data_size = sizeof(struct dec_dpb_ref_info) * MFC_MAX_BUFFERS; + dec->ref_info = vmalloc(dec->sh_handle_dpb.data_size); + if (!dec->ref_info) { + mfc_ctx_err("failed to allocate decoder information data\n"); + ret = -ENOMEM; + goto fail_dec_init; + } + for (i = 0; i < MFC_MAX_BUFFERS; i++) + dec->ref_info[i].dpb[0].fd[0] = MFC_INFO_INIT_FD; + + if (ctx->dev->debugfs.sfr_dump & MFC_DUMP_DEC_CRC) { + dec->crc = vmalloc(SZ_1K); + if (!dec->crc) { + ret = -ENOMEM; + goto fail_dec_init; + } + dec->crc_idx = 0; + } + + /* Init videobuf2 queue for OUTPUT */ + ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + ctx->vq_src.drv_priv = ctx; + ctx->vq_src.buf_struct_size = (unsigned int)sizeof(struct mfc_buf); + ctx->vq_src.io_modes = VB2_USERPTR | VB2_DMABUF; + ctx->vq_src.ops = mfc_get_dec_vb2_ops(); + ctx->vq_src.mem_ops = mfc_mem_ops(); + ctx->vq_src.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + ret = vb2_queue_init(&ctx->vq_src); + if (ret) { + mfc_ctx_err("Failed to initialize videobuf2 queue(output)\n"); + goto fail_dec_init; + } + /* Init videobuf2 queue for CAPTURE */ + ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + ctx->vq_dst.drv_priv = ctx; + ctx->vq_dst.buf_struct_size = (unsigned int)sizeof(struct mfc_buf); + ctx->vq_dst.io_modes = VB2_USERPTR | VB2_DMABUF; + ctx->vq_dst.ops = mfc_get_dec_vb2_ops(); + ctx->vq_dst.mem_ops = mfc_mem_ops(); + ctx->vq_dst.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + ret = vb2_queue_init(&ctx->vq_dst); + if (ret) { + mfc_ctx_err("Failed to initialize videobuf2 queue(capture)\n"); + goto fail_dec_init; + } + + return ret; + +fail_dec_init: + __mfc_deinit_dec_ctx(ctx); + return ret; +} + /* Open an MFC node */ static int mfc_open(struct file *file) { @@ -49,6 +236,7 @@ static int mfc_open(struct file *file) int i, ret = 0; enum mfc_node_type node; struct video_device *vdev = NULL; + unsigned long total_mb = 0, max_hw_mb = 0; if (!dev) { mfc_pr_err("no mfc device to run\n"); @@ -60,6 +248,26 @@ static int mfc_open(struct file *file) if (mutex_lock_interruptible(&dev->mfc_mutex)) return -ERESTARTSYS; + /* Check mfc_open() of spec over */ + for (i = 0; i < dev->num_core; i++) + max_hw_mb += dev->core[i]->core_pdata->max_hw_mb; + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (!dev->ctx[i]) + continue; + total_mb += dev->ctx[i]->weighted_mb; + mfc_show_ctx_info(dev->ctx[i]); + } + if (total_mb >= max_hw_mb) { + mfc_dev_info + ("[RM] now MFC work with full spec(mb: %lu / %lu)\n", + total_mb, max_hw_mb); + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + if (!dev->ctx[i]) + continue; + mfc_print_ctx_info(dev->ctx[i]); + } + } + node = mfc_get_node_type(file); if (node == MFCNODE_INVALID) { mfc_dev_err("cannot specify node type\n"); @@ -109,20 +317,32 @@ static int mfc_open(struct file *file) } } + spin_lock_init(&ctx->buf_queue_lock); + spin_lock_init(&ctx->meminfo_queue_lock); spin_lock_init(&ctx->corelock.lock); + spin_lock_init(&ctx->src_ts.ts_lock); + spin_lock_init(&ctx->dst_q_ts.ts_lock); + spin_lock_init(&ctx->dst_dq_ts.ts_lock); + spin_lock_init(&ctx->src_q_ts.ts_lock); mutex_init(&ctx->intlock.core_mutex); mutex_init(&ctx->op_mode_mutex); + mutex_init(&ctx->drc_wait_mutex); init_waitqueue_head(&ctx->corelock.wq); + init_waitqueue_head(&ctx->corelock.migrate_wq); + INIT_LIST_HEAD(&ctx->dst_q_ts.ts_list); + INIT_LIST_HEAD(&ctx->dst_dq_ts.ts_list); + INIT_LIST_HEAD(&ctx->src_q_ts.ts_list); mfc_ctx_change_idle_mode(ctx, MFC_IDLE_MODE_NONE); if (mfc_is_decoder_node(node)) { - ctx->type = MFCINST_DECODER; + ret = __mfc_init_dec_ctx(ctx); dev->num_dec_inst++; } else { - ctx->type = MFCINST_ENCODER; dev->num_enc_inst++; } + if (ret) + goto err_ctx_init; if (dev->num_inst == 1) { /* all of the ctx list */ @@ -131,6 +351,12 @@ static int mfc_open(struct file *file) /* idle mode */ spin_lock_init(&dev->idle_bits_lock); } + if (mfc_is_decoder_node(node)) + ret = call_cop(ctx, init_ctx_ctrls, ctx); + if (ret) { + mfc_ctx_err("failed in init_ctx_ctrls\n"); + goto err_ctx_init; + } mfc_ctx_info ("NORMAL %s instance is opened [%d]\n", @@ -155,11 +381,16 @@ static int mfc_open(struct file *file) ("[INFO] %s opened (ctx:%d, total:%d)\n", mfc_is_decoder_node(node) ? "DEC" : "ENC", ctx->num, dev->num_inst); + queue_work(dev->butler_wq, &dev->butler_work); + mutex_unlock(&dev->mfc_mutex); return ret; /* Deinit when failure occurred */ err_inst_init: + call_cop(ctx, cleanup_ctx_ctrls, ctx); + +err_ctx_init: if (mfc_is_decoder_node(node)) dev->num_dec_inst--; else @@ -192,10 +423,13 @@ static int mfc_release(struct file *file) { struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct mfc_dev *dev = ctx->dev; + struct mfc_ctx *move_ctx; int ret = 0; + int i; unsigned long flags; mutex_lock(&dev->mfc_mutex); + mutex_lock(&dev->mfc_migrate_mutex); mfc_ctx_info ("%s instance release is called [%d]\n", @@ -215,6 +449,12 @@ static int mfc_release(struct file *file) * So, we need to performed stop_streaming * before instance de-init(CLOSE_INSTANCE). */ + if (ctx->type == MFCINST_DECODER) { + vb2_queue_release(&ctx->vq_src); + vb2_queue_release(&ctx->vq_dst); + + call_cop(ctx, cleanup_ctx_ctrls, ctx); + } ret = mfc_rm_instance_deinit(dev, ctx); if (ret) { @@ -224,13 +464,27 @@ static int mfc_release(struct file *file) dev->num_inst--; - if (ctx->type == MFCINST_DECODER) + if (IS_MULTI_CORE_DEVICE(dev)) + mfc_rm_load_balancing(ctx, MFC_RM_LOAD_DELETE_UPDATE); + + if (ctx->type == MFCINST_DECODER) { + __mfc_deinit_dec_ctx(ctx); dev->num_dec_inst--; - else if (ctx->type == MFCINST_ENCODER) + } else if (ctx->type == MFCINST_ENCODER) { dev->num_enc_inst--; + } MFC_TRACE_CTX_LT("[INFO] Release finished (ctx:%d, total:%d)\n", ctx->num, dev->num_inst); + /* If ctx is move_ctx in migration worker, clear move_ctx */ + for (i = 0; i < dev->move_ctx_cnt; i++) { + move_ctx = dev->move_ctx[i]; + if (move_ctx && move_ctx->num == ctx->num) { + dev->move_ctx[i] = NULL; + break; + } + } + spin_lock_irqsave(&dev->ctx_list_lock, flags); dev->ctx[ctx->num] = NULL; kfree(ctx); @@ -238,17 +492,49 @@ static int mfc_release(struct file *file) mfc_dev_info("mfc driver release finished [%d]\n", dev->num_inst); + queue_work(dev->butler_wq, &dev->butler_work); + end_release: + mutex_unlock(&dev->mfc_migrate_mutex); mutex_unlock(&dev->mfc_mutex); return ret; } +/* Poll */ +static __poll_t mfc_poll(struct file *file, struct poll_table_struct *wait) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + unsigned long req_events = poll_requested_events(wait); + __poll_t ret = 0; + + mfc_ctx_debug_enter(); + + if (mfc_rm_query_state(ctx, EQUAL, MFCINST_ERROR)) { + if (req_events & (POLLOUT | POLLWRNORM)) + mfc_ctx_err("SRC: Call on POLL after unrecoverable error\n"); + else + mfc_ctx_err("DST: Call on POLL after unrecoverable error\n"); + return EPOLLERR; + } + + if (req_events & (POLLOUT | POLLWRNORM)) { + mfc_ctx_debug(2, "wait source buffer\n"); + ret = vb2_poll(&ctx->vq_src, file, wait); + } else if (req_events & (POLLIN | POLLRDNORM)) { + mfc_ctx_debug(2, "wait destination buffer\n"); + ret = vb2_poll(&ctx->vq_dst, file, wait); + } + + mfc_ctx_debug_leave(); + return ret; +} + /* v4l2 ops */ static const struct v4l2_file_operations mfc_fops = { .owner = THIS_MODULE, .open = mfc_open, .release = mfc_release, - .poll = NULL, + .poll = mfc_poll, .unlocked_ioctl = video_ioctl2, }; @@ -278,6 +564,9 @@ static void __mfc_parse_dt_resource(struct mfc_dev *dev, struct device_node *np) of_property_read_u32_index(np_tmp, "info", idx++, &codec_mode); resource = &dev->pdata->mfc_resource[codec_mode]; of_property_read_u32_index(np_tmp, "info", idx++, (u32 *)&resource->op_core_type); + of_property_read_u32_index(np_tmp, "info", idx++, &resource->max_kbps); + if (resource->max_kbps > dev->max_kbps) + dev->max_kbps = resource->max_kbps; } } @@ -309,17 +598,104 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) /* Resource of standard */ __mfc_parse_dt_resource(mfc, np); + /* Features */ + of_property_read_u32_array(np, "skype", &pdata->skype.support, 2); + of_property_read_u32_array + (np, "black_bar", + &pdata->black_bar.support, 2); + of_property_read_u32_array + (np, "color_aspect_dec", + &pdata->color_aspect_dec.support, 2); + of_property_read_u32_array + (np, "static_info_dec", + &pdata->static_info_dec.support, 2); + of_property_read_u32_array + (np, "vp9_stride_align", + &pdata->vp9_stride_align.support, 2); of_property_read_u32_array (np, "mem_clear", &pdata->mem_clear.support, 2); of_property_read_u32_array (np, "wait_fw_status", &pdata->wait_fw_status.support, 2); + of_property_read_u32_array + (np, "hevc_pic_output_flag", + &pdata->hevc_pic_output_flag.support, 2); + + /* H/W limitation or option */ + of_property_read_u32(np, "stride_align", &pdata->stride_align); + of_property_read_u32(np, "stride_type", &pdata->stride_type); + of_property_read_u32(np, "stream_buf_limit", &pdata->stream_buf_limit); + of_property_read_u32(np, "support_8K_cavlc", &pdata->support_8K_cavlc); + + /* Formats */ + of_property_read_u32(np, "support_422", &pdata->support_422); + + /* Resolution */ + of_property_read_u32(np, "support_check_res", &pdata->support_check_res); + + /* HWACG */ + of_property_read_u32(np, "support_hwacg", &pdata->support_hwacg); + + /* display_err_type */ + of_property_read_u32(np, "display_err_type", &pdata->display_err_type); + + /* output buffer Q framerate */ + of_property_read_u32(np, "display_framerate", &pdata->display_framerate); + + of_property_read_u32_array + (np, "bw_dec_h264", + &pdata->mfc_bw_info.bw_dec_h264.peak, 3); + + /* QoS weight */ + of_property_read_u32(np, "dynamic_weight", &pdata->dynamic_weight); + of_property_read_u32 + (np, "qos_weight_h264_hevc", + &pdata->qos_weight.weight_h264_hevc); + of_property_read_u32 + (np, "qos_weight_3plane", + &pdata->qos_weight.weight_3plane); + of_property_read_u32 + (np, "qos_weight_num_of_tile", + &pdata->qos_weight.weight_num_of_tile); + of_property_read_u32 + (np, "qos_weight_mbaff", + &pdata->qos_weight.weight_mbaff); + + /* Bitrate control for QoS */ + of_property_read_u32(np, "num_mfc_freq", &pdata->num_mfc_freq); + if (pdata->num_mfc_freq) + of_property_read_u32_array + (np, "mfc_freqs", + pdata->mfc_freqs, pdata->num_mfc_freq); + + /* Core balance(%) for resource managing */ + of_property_read_u32(np, "core_balance", &pdata->core_balance); + + /* MFC IOVA threshold */ + of_property_read_u32(np, "iova_threshold", &pdata->iova_threshold); + + /* MFC idle clock control */ + of_property_read_u32(np, "idle_clk_ctrl", &pdata->idle_clk_ctrl); + + /* QoS level for pm_qos dynamic control */ + of_property_read_u32(np, "qos_ctrl_level", &pdata->qos_ctrl_level); + + /* Memlog size */ + of_property_read_u32(np, "memlog_size", &pdata->memlog_size); + of_property_read_u32(np, "memlog_sfr_size", &pdata->memlog_sfr_size); + + /* offset for saving result of regression */ + of_property_read_u32 + (np, "reg_h264_loop_filter_disable", + &pdata->reg_h264_loop_filter_disable); /* Scheduler */ of_property_read_u32(np, "scheduler", &pdata->scheduler); of_property_read_u32(np, "pbs_num_prio", &pdata->pbs_num_prio); + of_property_read_u32(np, "support_mv_hevc", &pdata->support_mv_hevc); + return 0; } @@ -341,6 +717,11 @@ static struct video_device *__mfc_video_device_register vfd->minor = -1; vfd->release = video_device_release; + if (IS_DEC_NODE(node_num)) + vfd->ioctl_ops = mfc_get_dec_v4l2_ioctl_ops(); + else if (IS_ENC_NODE(node_num)) + vfd->ioctl_ops = NULL; + vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; @@ -413,6 +794,7 @@ static int mfc_probe(struct platform_device *pdev) dma_set_mask(&pdev->dev, DMA_BIT_MASK(dev->pdata->dma_bit_mask)); mutex_init(&dev->mfc_mutex); + mutex_init(&dev->mfc_migrate_mutex); ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); if (ret) @@ -437,6 +819,24 @@ static int mfc_probe(struct platform_device *pdev) } /* end of node setting*/ + /* instance migration worker */ + dev->migration_wq = alloc_workqueue("mfc/inst_migration", WQ_UNBOUND + | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + if (!dev->migration_wq) { + dev_err(&pdev->dev, "failed to create workqueue for migration wq\n"); + goto err_migration_work; + } + INIT_WORK(&dev->migration_work, mfc_rm_migration_worker); + + /* main butler worker */ + dev->butler_wq = alloc_workqueue("mfc/butler", WQ_UNBOUND + | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + if (!dev->butler_wq) { + dev_err(&pdev->dev, "failed to create workqueue for butler\n"); + goto err_butler_wq; + } + INIT_WORK(&dev->butler_work, mfc_butler_worker); + /* for DVA reservation */ if (dev->pdata->reserved_start) { dev->domain = iommu_get_domain_for_dev(dev->device); @@ -461,6 +861,10 @@ static int mfc_probe(struct platform_device *pdev) /* Deinit MFC if probe had failed */ err_iova_reserve: + destroy_workqueue(dev->butler_wq); +err_butler_wq: + destroy_workqueue(dev->migration_wq); +err_migration_work: video_unregister_device(dev->vfd_enc); alloc_vdev_enc: video_unregister_device(dev->vfd_dec); @@ -468,6 +872,7 @@ static int mfc_probe(struct platform_device *pdev) v4l2_device_unregister(&dev->v4l2_dev); err_v4l2_dev: mutex_destroy(&dev->mfc_mutex); + mutex_destroy(&dev->mfc_migrate_mutex); err_res_mem: return ret; } @@ -482,6 +887,10 @@ static void mfc_remove(struct platform_device *pdev) platform_driver_unregister(&mfc_core_driver); mfc_unconfigure_dma_memory(dev); of_reserved_mem_device_release(dev->device); + flush_workqueue(dev->butler_wq); + destroy_workqueue(dev->butler_wq); + flush_workqueue(dev->migration_wq); + destroy_workqueue(dev->migration_wq); mfc_deinit_debugfs(dev); video_unregister_device(dev->vfd_enc); @@ -665,6 +1074,7 @@ static const struct dev_pm_ops mfc_pm_ops = { struct mfc_ctx_buf_size mfc_ctx_buf_size = { .dev_ctx = PAGE_ALIGN(0x7800), /* 30KB */ + .h264_dec_ctx = PAGE_ALIGN(0x200000), /* 1.6MB */ .dbg_info_buf = PAGE_ALIGN(0x1000), /* 4KB for DEBUG INFO */ }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c index 5baa76a6b405..59cd6f3945ff 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c @@ -14,18 +14,34 @@ #include "mfc_debugfs.h" +#include "base/mfc_queue.h" + static int __mfc_info_show(struct seq_file *s, void *unused) { struct mfc_dev *dev = s->private; struct mfc_core *core = NULL; + struct mfc_ctx *ctx = NULL; struct mfc_core_ctx *core_ctx = NULL; int i, j; + char *codec_name = NULL, *fmt_name = NULL; seq_puts(s, ">>> MFC common device information\n"); seq_printf(s, " [DEBUG MODE] dt: %s sysfs: %s\n", dev->pdata->debug_mode ? "enabled" : "disabled", dev->debugfs.debug_mode_en ? "enabled" : "disabled"); - + seq_printf(s, " [FEATURES] skype: %d(0x%x), black_bar: %d(0x%x)\n", + dev->pdata->skype.support, dev->pdata->skype.version, + dev->pdata->black_bar.support, + dev->pdata->black_bar.version); + seq_printf(s, " color_aspect_dec: %d(0x%x)\n", + dev->pdata->color_aspect_dec.support, + dev->pdata->color_aspect_dec.version); + seq_printf(s, " static_info_dec: %d(0x%x)\n", + dev->pdata->static_info_dec.support, + dev->pdata->static_info_dec.version); + seq_printf(s, " [FORMATS] 10bit: %s, 422: %s\n", + dev->pdata->support_10bit ? "supported" : "not supported", + dev->pdata->support_422 ? "supported" : "not supported"); seq_printf(s, " [LOWMEM] is_low_mem: %d\n", IS_LOW_MEM); for (j = 0; j < dev->num_core; j++) { @@ -54,9 +70,46 @@ static int __mfc_info_show(struct seq_file *s, void *unused) for (i = 0; i < MFC_NUM_CONTEXTS; i++) { core_ctx = core->core_ctx[i]; if (core_ctx) { - seq_printf(s, " [CORECTX:%d] state: %d\n", - i, core_ctx->state); + seq_printf(s, " [CORECTX:%d] state: %d, queue(src: %d, dst: %d)\n", + i, core_ctx->state, + mfc_get_queue_count(&core_ctx->ctx->buf_queue_lock, + &core_ctx->src_buf_queue), + mfc_get_queue_count(&core_ctx->ctx->buf_queue_lock, + &core_ctx->dst_buf_queue)); + } + } + } + seq_puts(s, ">>> MFC instance information\n"); + for (i = 0; i < MFC_NUM_CONTEXTS; i++) { + ctx = dev->ctx[i]; + if (ctx) { + if (ctx->type == MFCINST_DECODER) { + codec_name = ctx->src_fmt->name; + fmt_name = ctx->dst_fmt->name; + } else { + codec_name = ctx->dst_fmt->name; + fmt_name = ctx->src_fmt->name; } + + seq_printf(s, " [CTX:%d] %s%s %s, size: %dx%d@%ldfps(ts: %lufps, tmu: %dfps, op: %lufps), crop: %d %d %d %d\n", + ctx->num, codec_name, ctx->multi_view_enable ? "(MV-HEVC)" : "", + fmt_name, + ctx->img_width, ctx->img_height, + ctx->framerate / 1000, + ctx->last_framerate / 1000, + ctx->dev->tmu_fps, + ctx->operating_framerate, + ctx->crop_width, ctx->crop_height, + ctx->crop_left, ctx->crop_top); + seq_printf(s, " main core: %d, op_mode: %d(stream: %d), idle_mode: %d, prio %d, rt %d, queue(src: %d, dst: %d, ref: %d)\n", + ctx->op_core_num[MFC_CORE_MAIN], + ctx->op_mode, ctx->stream_op_mode, ctx->idle_mode, + ctx->prio, ctx->rt, + mfc_get_queue_count(&ctx->buf_queue_lock, + &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); + seq_puts(s, "\n"); } } @@ -175,6 +228,7 @@ void mfc_init_debugfs(struct mfc_dev *dev) debugfs_create_u32("sfr_dump", 0644, debugfs->root, &dev->debugfs.sfr_dump); debugfs_create_u32("feature_option", 0644, debugfs->root, &dev->debugfs.feature_option); + debugfs_create_u32("core_balance", 0644, debugfs->root, &dev->debugfs.core_balance); debugfs_create_u32("logging_option", 0644, debugfs->root, &dev->debugfs.logging_option); debugfs_create_u32("sched_perf_disable", 0644, debugfs->root, &dev->debugfs.sched_perf_disable); -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035646epcas5p2f4a9694c7f89ffe27384f8b7b8227802@epcas5p2.samsung.com>]
* [PATCH 21/29] media: mfc: Add multi‑codec support & QoS improvements [not found] ` <CGME20250930035646epcas5p2f4a9694c7f89ffe27384f8b7b8227802@epcas5p2.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Enable HEVC, AV1, VP8/9, MPEG‑4 (incl. MVC, VC‑1 RCV) . - Extend DPB/buffer structures for AV1 and high‑resolution/multiframe streams. - Add codec‑specific QoS weight parameters (10‑bit, 4:2:2, B‑frames) and update DT bandwidth entries. - Enhance format tables with colour‑range/space and HDR parsing for VP9. - Detect display‑resolution changes and multiframe flags for VP9/AV1. - Introduce utility helpers (CRC, aspect‑ratio, colour primaries) and minor safety fixes. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_buf.c | 70 +++++++++ .../samsung/exynos-mfc/base/mfc_common.h | 42 ++++- .../samsung/exynos-mfc/base/mfc_data_struct.h | 20 +++ .../samsung/exynos-mfc/base/mfc_format.h | 136 ++++++++++++++++ .../samsung/exynos-mfc/base/mfc_qos.c | 58 +++++++ .../samsung/exynos-mfc/base/mfc_queue.c | 5 + .../samsung/exynos-mfc/base/mfc_utils.c | 8 +- .../media/platform/samsung/exynos-mfc/mfc.c | 53 +++++++ .../platform/samsung/exynos-mfc/mfc_core.c | 2 + .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 9 ++ .../samsung/exynos-mfc/mfc_core_cmd.c | 11 ++ .../samsung/exynos-mfc/mfc_core_isr.c | 147 ++++++++++++++++-- .../samsung/exynos-mfc/mfc_core_reg_api.c | 46 +++++- .../samsung/exynos-mfc/mfc_core_reg_api.h | 75 ++++++++- .../samsung/exynos-mfc/mfc_core_run.c | 4 + .../platform/samsung/exynos-mfc/mfc_dec_vb2.c | 1 + 16 files changed, 665 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c index bd1baf34e0b0..84f97ca230bb 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c @@ -116,8 +116,25 @@ int mfc_alloc_instance_context(struct mfc_core_ctx *core_ctx) switch (ctx->codec_mode) { case MFC_REG_CODEC_H264_DEC: case MFC_REG_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_HEVC_DEC: core_ctx->instance_ctx_buf.size = buf_size->h264_dec_ctx; break; + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_H263_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + case MFC_REG_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP9_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: + core_ctx->instance_ctx_buf.size = buf_size->other_dec_ctx; + break; + case MFC_REG_CODEC_AV1_DEC: + core_ctx->instance_ctx_buf.size = buf_size->av1_dec_ctx; + break; default: core_ctx->instance_ctx_buf.size = 0; mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode); @@ -155,6 +172,59 @@ static void __mfc_dec_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) /* Codecs have different memory requirements */ switch (ctx->codec_mode) { case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + ctx->mv_buf.size = dec->mv_count * ctx->mv_size; + break; + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + if (dec->loop_filter_mpeg4) { + ctx->loopfilter_luma_size = ALIGN(ctx->raw_buf.plane_size[0], SZ_256); + ctx->loopfilter_chroma_size = ALIGN(ctx->raw_buf.plane_size[1] + + ctx->raw_buf.plane_size[2], SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size + + (NUM_MPEG4_LF_BUF * (ctx->loopfilter_luma_size + + ctx->loopfilter_chroma_size)); + } else { + core_ctx->codec_buf.size = ctx->scratch_buf_size; + } + break; + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + break; + case MFC_REG_CODEC_MPEG2_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + break; + case MFC_REG_CODEC_H263_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + break; + case MFC_REG_CODEC_VP8_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = ctx->scratch_buf_size; + break; + case MFC_REG_CODEC_VP9_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + + DEC_STATIC_BUFFER_SIZE; + break; + case MFC_REG_CODEC_AV1_DEC: + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + + DEC_AV1_STATIC_BUFFER_SIZE(ctx->img_width, ctx->img_height); + ctx->mv_buf.size = dec->mv_count * ctx->mv_size; + break; + case MFC_REG_CODEC_HEVC_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); core_ctx->codec_buf.size = ctx->scratch_buf_size; ctx->mv_buf.size = dec->mv_count * ctx->mv_size; diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h index de22c28d1625..5392c8566e42 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h @@ -153,7 +153,47 @@ /* Decoder codec mode check */ #define IS_H264_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_DEC) +#define IS_H264_MVC_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_MVC_DEC) +#define IS_MPEG4_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG4_DEC) +#define IS_FIMV1_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV1_DEC) +#define IS_FIMV2_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV2_DEC) +#define IS_FIMV3_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV3_DEC) +#define IS_FIMV4_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV4_DEC) +#define IS_VC1_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VC1_DEC) +#define IS_VC1_RCV_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VC1_RCV_DEC) +#define IS_MPEG2_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG2_DEC) +#define IS_HEVC_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_DEC) +#define IS_VP8_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP8_DEC) +#define IS_VP9_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP9_DEC) +#define IS_AV1_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_AV1_DEC) +#define IS_MV_HEVC_DEC(ctx, profile) \ + ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_DEC && \ + (profile) == MFC_REG_D_PROFILE_MULTIVIEW_HEVC_MAIN) + +#define CODEC_NOT_CODED(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_MPEG4_DEC(_ctx) || IS_VC1_DEC(_ctx) || IS_VC1_RCV_DEC(_ctx) || \ + IS_VP9_DEC(_ctx)); \ +}) +#define CODEC_INTERLACED(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx) || IS_MPEG2_DEC(_ctx) || \ + IS_MPEG4_DEC(_ctx) || IS_VC1_DEC(_ctx) || IS_VC1_RCV_DEC(_ctx)); \ +}) +#define CODEC_MBAFF(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx)); \ +}) +#define CODEC_MULTIFRAME(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_MPEG4_DEC(_ctx) || IS_VP9_DEC(_ctx) || IS_FIMV2_DEC(_ctx) || \ + IS_FIMV3_DEC(_ctx) || IS_FIMV4_DEC(_ctx) || IS_AV1_DEC(_ctx)); \ +}) +#define CODEC_422FORMAT(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_HEVC_DEC(_ctx) || IS_VP9_DEC(_ctx)); \ +}) #define ON_RES_CHANGE(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ ((_ctx->state >= MFCINST_RES_CHANGE_INIT) && \ @@ -177,7 +217,7 @@ }) #define CODEC_HAS_IDR(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ - (IS_H264_DEC(_ctx)); \ + (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx) || IS_HEVC_DEC(_ctx)); \ }) /* diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h index 34b4b13b4f01..6b93fe3ab138 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h @@ -503,6 +503,8 @@ struct mfc_fw { struct mfc_ctx_buf_size { size_t dev_ctx; size_t h264_dec_ctx; + size_t av1_dec_ctx; + size_t other_dec_ctx; size_t dbg_info_buf; }; @@ -710,6 +712,14 @@ struct mfc_bw_data { struct mfc_bw_info { struct mfc_bw_data bw_dec_h264; + struct mfc_bw_data bw_dec_hevc; + struct mfc_bw_data bw_dec_hevc_10bit; + struct mfc_bw_data bw_dec_vp8; + struct mfc_bw_data bw_dec_vp9; + struct mfc_bw_data bw_dec_vp9_10bit; + struct mfc_bw_data bw_dec_av1; + struct mfc_bw_data bw_dec_av1_10bit; + struct mfc_bw_data bw_dec_mpeg4; }; /* @@ -723,6 +733,7 @@ struct mfc_qos { unsigned int freq_int; unsigned int freq_mif; unsigned int mo_value; + unsigned int mo_10bit_value; unsigned int time_fw; unsigned int bts_scen_idx; const char *name; @@ -747,8 +758,17 @@ struct mfc_qos_ctrl { struct mfc_qos_weight { unsigned int weight_h264_hevc; + unsigned int weight_vp8_vp9; + unsigned int weight_av1; + unsigned int weight_other_codec; unsigned int weight_3plane; + unsigned int weight_10bit; + unsigned int weight_422; + unsigned int weight_bframe; + unsigned int weight_num_of_ref; + unsigned int weight_gpb; unsigned int weight_num_of_tile; + unsigned int weight_super64_bframe; unsigned int weight_mbaff; }; diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h index 3307c2eeaebb..0d48f2373e8d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h @@ -127,6 +127,142 @@ static struct mfc_fmt mfc_formats[] = { .num_planes = 1, .mem_planes = 1, }, + { + .name = "DEC H264/MVC", + .fourcc = V4L2_PIX_FMT_H264_MVC, + .codec_mode = MFC_REG_CODEC_H264_MVC_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC H263", + .fourcc = V4L2_PIX_FMT_H263, + .codec_mode = MFC_REG_CODEC_H263_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC MPEG1", + .fourcc = V4L2_PIX_FMT_MPEG1, + .codec_mode = MFC_REG_CODEC_MPEG2_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC MPEG2", + .fourcc = V4L2_PIX_FMT_MPEG2, + .codec_mode = MFC_REG_CODEC_MPEG2_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC MPEG4", + .fourcc = V4L2_PIX_FMT_MPEG4, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC FIMV", + .fourcc = V4L2_PIX_FMT_FIMV, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC FIMV1", + .fourcc = V4L2_PIX_FMT_FIMV1, + .codec_mode = MFC_REG_CODEC_FIMV1_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC FIMV2", + .fourcc = V4L2_PIX_FMT_FIMV2, + .codec_mode = MFC_REG_CODEC_FIMV2_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC FIMV3", + .fourcc = V4L2_PIX_FMT_FIMV3, + .codec_mode = MFC_REG_CODEC_FIMV3_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC FIMV4", + .fourcc = V4L2_PIX_FMT_FIMV4, + .codec_mode = MFC_REG_CODEC_FIMV4_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC XviD", + .fourcc = V4L2_PIX_FMT_XVID, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC VC1", + .fourcc = V4L2_PIX_FMT_VC1_ANNEX_G, + .codec_mode = MFC_REG_CODEC_VC1_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC VC1 RCV", + .fourcc = V4L2_PIX_FMT_VC1_ANNEX_L, + .codec_mode = MFC_REG_CODEC_VC1_RCV_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC VP8", + .fourcc = V4L2_PIX_FMT_VP8, + .codec_mode = MFC_REG_CODEC_VP8_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC VP9", + .fourcc = V4L2_PIX_FMT_VP9, + .codec_mode = MFC_REG_CODEC_VP9_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC AV1", + .fourcc = V4L2_PIX_FMT_AV1, + .codec_mode = MFC_REG_CODEC_AV1_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "DEC HEVC", + .fourcc = V4L2_PIX_FMT_HEVC, + .codec_mode = MFC_REG_CODEC_HEVC_DEC, + .type = MFC_FMT_STREAM | MFC_FMT_DEC, + .num_planes = 1, + .mem_planes = 1, + }, }; #endif /* __MFC_FORMAT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c index f6548543f07c..9922c2396b94 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c @@ -38,6 +38,7 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l switch (ctx->codec_mode) { case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: weight = (weight * 100) / qos_weight->weight_h264_hevc; mfc_ctx_debug(3, "[QoS] h264, hevc codec, weight: %d\n", weight / 10); if (num_planes == 3) { @@ -45,6 +46,63 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); } break; + + case MFC_REG_CODEC_VP8_DEC: + weight = (weight * 100) / qos_weight->weight_vp8_vp9; + mfc_ctx_debug(3, "[QoS] vp8, vp9 codec, weight: %d\n", weight / 10); + if (num_planes == 3) { + weight = (weight * 100) / qos_weight->weight_3plane; + mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); + } + break; + + case MFC_REG_CODEC_HEVC_DEC: + weight = (weight * 100) / qos_weight->weight_h264_hevc; + mfc_ctx_debug(3, "[QoS] h264, hevc codec, weight: %d\n", weight / 10); + if (num_planes == 3) { + weight = (weight * 100) / qos_weight->weight_3plane; + mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); + } else { + if (ctx->is_422) { + weight = (weight * 100) / qos_weight->weight_422; + mfc_ctx_debug(3, "[QoS] 422foramt, weight: %d\n", weight / 10); + } + } + break; + + case MFC_REG_CODEC_AV1_DEC: + weight = (weight * 100) / qos_weight->weight_av1; + mfc_ctx_debug(3, "[QoS] av1 codec, weight: %d\n", weight / 10); + break; + + case MFC_REG_CODEC_VP9_DEC: + weight = (weight * 100) / qos_weight->weight_vp8_vp9; + mfc_ctx_debug(3, "[QoS] vp8, vp9 codec, weight: %d\n", weight / 10); + + if (num_planes == 3) { + weight = (weight * 100) / qos_weight->weight_3plane; + mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); + } else { + if (ctx->is_422) { + weight = (weight * 100) / qos_weight->weight_422; + mfc_ctx_debug(3, "[QoS] 422foramt, weight: %d\n", weight / 10); + } + } + break; + + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: + case MFC_REG_CODEC_H263_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + case MFC_REG_CODEC_MPEG2_DEC: + weight = (weight * 100) / qos_weight->weight_other_codec; + mfc_ctx_debug(3, "[QoS] other codec, weight: %d\n", weight / 10); + break; + default: mfc_ctx_err("[QoS] wrong codec_mode (%d), no weight\n", ctx->codec_mode); } diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c index f56e800c55f0..6dc9bc7a1873 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c @@ -154,6 +154,11 @@ struct mfc_buf *mfc_get_del_if_consumed(struct mfc_ctx *ctx, consumed, strm_size); } + if (remained && IS_MULTI_MODE(ctx) && !CODEC_MULTIFRAME(ctx)) { + mfc_ctx_info("[2CORE][MULTIFRAME] multicore mode couldn't handle multiframe\n"); + remained = 0; + } + if (consumed > 0 && remained > min_bytes && IS_NO_ERROR(error) && !exceed) { /* do not delete from queue */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c index b0698b2bb0c0..83cdae3dee57 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c @@ -187,9 +187,15 @@ void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct } mfc_ctx_debug(2, "[FRAME] total plane size: %d\n", raw->total_plane_size); - if (IS_H264_DEC(ctx)) { + if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx)) { ctx->mv_size = DEC_MV_SIZE_MB(ctx->img_width, ctx->img_height); ctx->mv_size = ALIGN(ctx->mv_size, 32); + } else if (IS_HEVC_DEC(ctx)) { + ctx->mv_size = DEC_HEVC_MV_SIZE(ctx->img_width, ctx->img_height); + ctx->mv_size = ALIGN(ctx->mv_size, 32); + } else if (IS_AV1_DEC(ctx)) { + ctx->mv_size = DEC_AV1_MV_SIZE(ctx->img_width, ctx->img_height); + ctx->mv_size = ALIGN(ctx->mv_size, 32); } else { ctx->mv_size = 0; } diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc.c b/drivers/media/platform/samsung/exynos-mfc/mfc.c index fb9a7317e812..293a353c49fa 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc.c @@ -646,18 +646,69 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) of_property_read_u32_array (np, "bw_dec_h264", &pdata->mfc_bw_info.bw_dec_h264.peak, 3); + of_property_read_u32_array + (np, "bw_dec_hevc", + &pdata->mfc_bw_info.bw_dec_hevc.peak, 3); + of_property_read_u32_array + (np, "bw_dec_hevc_10bit", + &pdata->mfc_bw_info.bw_dec_hevc_10bit.peak, 3); + of_property_read_u32_array + (np, "bw_dec_vp8", + &pdata->mfc_bw_info.bw_dec_vp8.peak, 3); + of_property_read_u32_array + (np, "bw_dec_vp9", + &pdata->mfc_bw_info.bw_dec_vp9.peak, 3); + of_property_read_u32_array + (np, "bw_dec_vp9_10bit", + &pdata->mfc_bw_info.bw_dec_vp9_10bit.peak, 3); + of_property_read_u32_array + (np, "bw_dec_av1", + &pdata->mfc_bw_info.bw_dec_av1.peak, 3); + of_property_read_u32_array + (np, "bw_dec_av1_10bit", + &pdata->mfc_bw_info.bw_dec_av1_10bit.peak, 3); + of_property_read_u32_array + (np, "bw_dec_mpeg4", + &pdata->mfc_bw_info.bw_dec_mpeg4.peak, 3); /* QoS weight */ of_property_read_u32(np, "dynamic_weight", &pdata->dynamic_weight); of_property_read_u32 (np, "qos_weight_h264_hevc", &pdata->qos_weight.weight_h264_hevc); + of_property_read_u32 + (np, "qos_weight_vp8_vp9", + &pdata->qos_weight.weight_vp8_vp9); + of_property_read_u32 + (np, "qos_weight_av1", + &pdata->qos_weight.weight_av1); + of_property_read_u32 + (np, "qos_weight_other_codec", + &pdata->qos_weight.weight_other_codec); of_property_read_u32 (np, "qos_weight_3plane", &pdata->qos_weight.weight_3plane); + of_property_read_u32 + (np, "qos_weight_10bit", + &pdata->qos_weight.weight_10bit); + of_property_read_u32 + (np, "qos_weight_422", + &pdata->qos_weight.weight_422); + of_property_read_u32 + (np, "qos_weight_bframe", + &pdata->qos_weight.weight_bframe); + of_property_read_u32 + (np, "qos_weight_num_of_ref", + &pdata->qos_weight.weight_num_of_ref); + of_property_read_u32 + (np, "qos_weight_gpb", + &pdata->qos_weight.weight_gpb); of_property_read_u32 (np, "qos_weight_num_of_tile", &pdata->qos_weight.weight_num_of_tile); + of_property_read_u32 + (np, "qos_weight_super64_bframe", + &pdata->qos_weight.weight_super64_bframe); of_property_read_u32 (np, "qos_weight_mbaff", &pdata->qos_weight.weight_mbaff); @@ -1075,6 +1126,8 @@ static const struct dev_pm_ops mfc_pm_ops = { struct mfc_ctx_buf_size mfc_ctx_buf_size = { .dev_ctx = PAGE_ALIGN(0x7800), /* 30KB */ .h264_dec_ctx = PAGE_ALIGN(0x200000), /* 1.6MB */ + .av1_dec_ctx = PAGE_ALIGN(0x19000), /* 100KB */ + .other_dec_ctx = PAGE_ALIGN(0xF000), /* 60KB */ .dbg_info_buf = PAGE_ALIGN(0x1000), /* 4KB for DEBUG INFO */ }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c index af6fd088fad3..aad3273ce2ba 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c @@ -77,6 +77,8 @@ static int __mfc_core_parse_mfc_qos_platdata(struct device_node *np, of_property_read_u32(np_qos, "freq_int", &qosdata->freq_int); of_property_read_u32(np_qos, "freq_mif", &qosdata->freq_mif); of_property_read_u32(np_qos, "mo_value", &qosdata->mo_value); + of_property_read_u32(np_qos, "mo_10bit_value", + &qosdata->mo_10bit_value); of_property_read_u32(np_qos, "time_fw", &qosdata->time_fw); of_property_read_string(np_qos, "bts_scen", &qosdata->name); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c index 56dc3e734d02..38f09d6ef2dd 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c @@ -63,6 +63,7 @@ static int mfc_core_get_buf_ctrls(struct mfc_core *core, struct mfc_ctx *ctx, struct list_head *head) { struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dec *dec = ctx->dec_priv; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -77,6 +78,14 @@ static int mfc_core_get_buf_ctrls(struct mfc_core *core, buf_ctrl->val = value; buf_ctrl->has_new = 1; + if (IS_VP9_DEC(ctx) && dec) { + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG) + buf_ctrl->val = dec->color_range; + else if (buf_ctrl->id == + V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES) + buf_ctrl->val = dec->color_space; + } + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_FRAME_ERROR_TYPE) buf_ctrl->val = mfc_get_frame_error_type(ctx, value); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c index fe7946bb49e7..aaf216741575 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c @@ -230,6 +230,10 @@ void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx) reg |= ((dec->idr_decoding & MFC_REG_D_DEC_OPT_IDR_DECODING_MASK) << MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT); + /* VC1 RCV: Discard to parse additional header as default */ + if (IS_VC1_RCV_DEC(ctx)) + reg |= BIT(MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT); + /* conceal control to specific color */ reg |= (0x4 << MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); @@ -248,6 +252,13 @@ void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx) MFC_CORE_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); + if (IS_FIMV1_DEC(ctx)) { + mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n", + ctx->img_width, ctx->img_height); + MFC_CORE_WRITEL(ctx->img_width, MFC_REG_D_SET_FRAME_WIDTH); + MFC_CORE_WRITEL(ctx->img_height, MFC_REG_D_SET_FRAME_HEIGHT); + } + mfc_core_set_pixel_format(core, ctx, ctx->dst_fmt->fourcc); reg = 0; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c index 94cc3c4dfdc5..aa2c0b618c19 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c @@ -126,10 +126,11 @@ static unsigned int __mfc_handle_frame_field(struct mfc_core *core, unsigned int interlace_type = 0, is_interlace = 0; unsigned int field; - if (IS_H264_DEC(ctx)) { - dec->is_mbaff = mfc_core_is_mbaff_picture(); + if (CODEC_INTERLACED(ctx)) is_interlace = mfc_core_is_interlace_picture(); - } + + if (CODEC_MBAFF(ctx)) + dec->is_mbaff = mfc_core_is_mbaff_picture(); if (is_interlace) { interlace_type = mfc_core_get_interlace_type(); @@ -482,6 +483,27 @@ static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, } } + if (IS_VP9_DEC(ctx) && + MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { + if (dec->color_space != MFC_REG_D_COLOR_UNKNOWN) { + mfc_set_mb_flag(dst_mb, + MFC_FLAG_HDR_COLOUR_DESC); + mfc_ctx_debug(2, "[HDR] color space parsed\n"); + } + mfc_set_mb_flag(dst_mb, MFC_FLAG_HDR_VIDEO_SIGNAL_TYPE); + mfc_ctx_debug(2, "[HDR] color range parsed\n"); + } + + if ((IS_VP9_DEC(ctx) && mfc_core_get_disp_res_change()) || + (IS_AV1_DEC(ctx) && mfc_core_get_disp_res_change_av1())) { + mfc_ctx_info("[FRAME][DRC] display resolution changed\n"); + mutex_lock(&ctx->drc_wait_mutex); + ctx->wait_state = WAIT_G_FMT; + mfc_core_get_img_size(core, ctx, MFC_GET_RESOL_SIZE); + mfc_set_mb_flag(dst_mb, MFC_FLAG_DISP_RES_CHANGE); + mutex_unlock(&ctx->drc_wait_mutex); + } + if (dec->black_bar_updated) { mfc_set_mb_flag(dst_mb, MFC_FLAG_BLACKBAR_DETECT); mfc_ctx_debug(3, "[BLACKBAR] black bar detected\n"); @@ -498,6 +520,11 @@ static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, mfc_ctx_debug(2, "[FRAME] Last display frame\n"); } + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_MULTIFRAME); + mfc_ctx_debug(2, "[MULTIFRAME] multiframe detected\n"); + } + if (ctx->dst_fmt->mem_planes == 1) { vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, raw->total_plane_size); @@ -542,6 +569,8 @@ static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, mutex_unlock(&dec->dpb_mutex); } else { + if (IS_AV1_DEC(ctx) && mfc_core_get_multiple_show_frame()) + dec->is_multiple_show = 1; mfc_print_dpb_queue_with_lock(core->core_ctx[ctx->num], dec); } @@ -708,11 +737,18 @@ static struct mfc_buf *__mfc_handle_frame_output(struct mfc_core *core, { struct mfc_dec *dec = ctx->dec_priv; unsigned int frame_type; + int mvc_view_id; frame_type = mfc_core_get_disp_frame_type(); + mvc_view_id = mfc_core_get_mvc_disp_view_id(); - if (!ctx->multi_view_enable || ctx->select_view_irq == MFC_VIEW_ID_SUB) - ctx->sequence++; + if (IS_H264_MVC_DEC(ctx)) { + if (mvc_view_id == 0) + ctx->sequence++; + } else { + if (!ctx->multi_view_enable || ctx->select_view_irq == MFC_VIEW_ID_SUB) + ctx->sequence++; + } if (dec->immediate_display == 1) frame_type = mfc_core_get_dec_frame_type(); @@ -721,7 +757,8 @@ static struct mfc_buf *__mfc_handle_frame_output(struct mfc_core *core, /* If frame is same as previous then skip and do not dequeue */ if (frame_type == MFC_REG_DISPLAY_FRAME_NOT_CODED) - return NULL; + if (!CODEC_NOT_CODED(ctx)) + return NULL; /* Dequeued display buffer for user */ return __mfc_handle_frame_output_del(core, ctx, err); @@ -894,6 +931,7 @@ static void __mfc_handle_frame_input(struct mfc_core *core, struct mfc_ctx *ctx, unsigned int err) { + struct mfc_dev *dev = ctx->dev; struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; struct mfc_dec *dec = ctx->dec_priv; struct mfc_buf *src_mb; @@ -945,6 +983,54 @@ static void __mfc_handle_frame_input(struct mfc_core *core, mfc_clear_mb_flag(src_mb); + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe && + mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM][MULTIFRAME] last frame is decoding only\n"); + } + + /* + * VP8 decoder has decoding only frame, + * it will be used for reference frame only not displayed. + * So, driver inform to user this input has no destination. + */ + if (((IS_VP8_DEC(ctx) || IS_VP9_DEC(ctx)) && + mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY) || + mfc_core_get_int_reason() == MFC_REG_R2H_CMD_FIELD_DONE_RET) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM] %s decoding only stream has no buffer to DQ\n", + ctx->src_fmt->name); + } + + /* + * Because AV1 has a no show frame, there are two cases that + * driver should inform to user this input has no destination buffer. + * 1) If it's decoding only and it's not showable frame, + * it will be used for reference frame only not displayed. + * 2) If the buffer that has already DQ to display comes to new display, + * it is multiple show frame. + */ + if (IS_AV1_DEC(ctx)) { + if ((mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY) && + !mfc_core_get_showable_frame()) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM] AV1 no showable frame has no buffer to DQ\n"); + } + if (dec->is_multiple_show) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + dec->is_multiple_show = 0; + mfc_info("[STREAM] AV1 multiple show frame has no buffer to DQ\n"); + } + } + + /* If pic_output_flag is 0 in HEVC, it is no destination buffer */ + if (IS_HEVC_DEC(ctx) && + MFC_FEATURE_SUPPORT(dev, dev->pdata->hevc_pic_output_flag) && + !mfc_core_get_hevc_pic_output_flag()) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM] HEVC pic_output_flag off has no buffer to DQ\n"); + } + if (mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY && mfc_core_get_dec_y_addr() == 0) { mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); @@ -955,6 +1041,8 @@ static void __mfc_handle_frame_input(struct mfc_core *core, mfc_err("failed in core_get_buf_ctrls\n"); dec->consumed = 0; + if (IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) + dec->has_multiframe = 0; if (ctx->multi_view_enable && ctx->select_view == 0) mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); @@ -978,7 +1066,7 @@ static void __mfc_handle_frame(struct mfc_core *core, unsigned int res_change, need_dpb_change, need_scratch_change; struct mfc_buf *mfc_buf = NULL; bool qos_update = false; - int index; + int index, profile; dst_frame_status = mfc_core_get_disp_status(); res_change = mfc_core_get_res_change(); @@ -1048,6 +1136,15 @@ static void __mfc_handle_frame(struct mfc_core *core, index = mfc_buf->vb.vb2_buf.index; call_bop(ctx, core_restore_buf_ctrls, ctx, &ctx->src_ctrls[index]); } + + /* It could because of sub-view header (MV-HEVC) */ + if (!ctx->multi_view_enable) { + profile = mfc_core_get_profile(); + if (IS_MV_HEVC_DEC(ctx, profile)) { + mfc_debug(2, "Ready to enable, possibly a sub-view header.\n"); + ctx->ready_to_be_multi_view_enable = 1; + } + } return; } @@ -1110,7 +1207,7 @@ static void __mfc_handle_frame(struct mfc_core *core, } /* Detection for QoS weight */ - if (!dec->num_of_tile_over_4 && + if (!dec->num_of_tile_over_4 && !IS_HEVC_DEC(ctx) && mfc_core_get_num_of_tile() >= 4) { dec->num_of_tile_over_4 = 1; qos_update = true; @@ -1185,7 +1282,7 @@ static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; struct mfc_dec *dec = ctx->dec_priv; struct mfc_buf *src_mb; - int i, is_interlace; + int i, is_interlace, profile; unsigned int strm_size, consumed; if (ctx->src_fmt->fourcc != V4L2_PIX_FMT_FIMV1) { @@ -1196,13 +1293,34 @@ static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) mfc_info("[STREAM] resolution w: %d, h: %d\n", ctx->img_width, ctx->img_height); } - ctx->dpb_count = mfc_core_get_dpb_count(); + if (IS_AV1_DEC(ctx) || (IS_VP9_DEC(ctx) && UNDER_4K_RES(ctx))) + ctx->dpb_count = mfc_core_get_dpb_count() + 7 - MFC_EXTRA_DPB; + else + ctx->dpb_count = mfc_core_get_dpb_count(); mfc_ctx_debug(2, "dpb_count: %d\n", ctx->dpb_count); ctx->scratch_buf_size = mfc_core_get_scratch_size(); mfc_core_dec_get_crop_info(core, ctx); dec->mv_count = mfc_core_get_mv_count(); + profile = mfc_core_get_profile(); + + if (CODEC_422FORMAT(ctx) && dev->pdata->support_422) { + if (mfc_core_get_chroma_format() == MFC_REG_D_CHROMA_422) { + ctx->is_422 = 1; + mfc_info("[STREAM] 422 chroma format\n"); + } + } + + if (IS_MV_HEVC_DEC(ctx, profile)) { + if (ctx->ready_to_be_multi_view_enable) { + mfc_debug(2, "It will be enabled later, pending DPB_FLUSH.\n"); + } else { + mfc_debug(2, "[MV-HEVC] enabled\n"); + ctx->multi_view_enable = 1; + ctx->select_view = MFC_VIEW_ID_MAIN; + } + } if (ctx->img_width == 0 || ctx->img_height == 0) { mfc_err("[STREAM] wrong resolution w: %d, h: %d\n", @@ -1243,7 +1361,7 @@ static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) strm_size = mfc_dec_get_strm_size(ctx, src_mb); mfc_debug(2, "[STREAM] header size, %d, %#x, consumed, %d, %#x\n", strm_size, strm_size, consumed, consumed); - if ((IS_H264_DEC(ctx)) && + if ((IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx)) && (consumed > 0 && strm_size > consumed)) { dec->consumed += consumed; mfc_debug(2, "[STREAM] there is remained bytes(%d) after header parsing\n", @@ -1257,6 +1375,13 @@ static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) mfc_debug(2, "[FRAME] display delay for first frame %d\n", dec->frame_display_delay); + if (IS_VP9_DEC(ctx)) { + dec->color_range = mfc_core_get_color_range(); + dec->color_space = mfc_core_get_color_space(); + mfc_debug(2, "color range: %d, color space: %d, It's valid for VP9\n", + dec->color_range, dec->color_space); + } + mfc_change_state(core_ctx, MFCINST_HEAD_PARSED); return 0; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c index 6950b8451c3d..0cc5d1d9433e 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c @@ -52,7 +52,8 @@ unsigned int mfc_get_frame_error_type(struct mfc_ctx *ctx, unsigned int err) return MFC_ERR_FRAME_NO_ERR; } - if (mfc_get_warn(err) == MFC_REG_ERR_BROKEN_LINK) { + if ((IS_VC1_RCV_DEC(ctx) && (mfc_get_warn(err) == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED)) || + (mfc_get_warn(err) == MFC_REG_ERR_BROKEN_LINK)) { mfc_ctx_debug(2, "[FRAME] Broken frame error (%d)\n", mfc_get_warn(err)); return MFC_ERR_FRAME_BROKEN; } else if (mfc_get_warn(err) == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED) { @@ -104,6 +105,7 @@ int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx) int buf_size; int align_gap; unsigned int reg = 0; + unsigned int av1_static_buf_size = 0; buf_addr = core_ctx->codec_buf.daddr; buf_size = core_ctx->codec_buf.size; @@ -124,14 +126,50 @@ int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx) buf_addr += ctx->scratch_buf_size; buf_size -= ctx->scratch_buf_size; - if (IS_H264_DEC(ctx)) + if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx) || IS_AV1_DEC(ctx)) MFC_CORE_WRITEL(ctx->mv_size, MFC_REG_D_MV_BUFFER_SIZE); + if (IS_VP9_DEC(ctx)) { + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_D_STATIC_BUFFER_ADDR); + MFC_CORE_WRITEL(DEC_STATIC_BUFFER_SIZE, MFC_REG_D_STATIC_BUFFER_SIZE); + buf_addr += DEC_STATIC_BUFFER_SIZE; + buf_size -= DEC_STATIC_BUFFER_SIZE; + } else if (IS_AV1_DEC(ctx)) { + av1_static_buf_size = DEC_AV1_STATIC_BUFFER_SIZE(ctx->img_width, ctx->img_height); + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_D_STATIC_BUFFER_ADDR); + MFC_CORE_WRITEL(av1_static_buf_size, MFC_REG_D_STATIC_BUFFER_SIZE); + buf_addr += av1_static_buf_size; + buf_size -= av1_static_buf_size; + } + + if (IS_MPEG4_DEC(ctx) && dec->loop_filter_mpeg4) { + mfc_debug(2, "Add DPB for loop filter of MPEG4\n"); + for (i = 0; i < NUM_MPEG4_LF_BUF; i++) { + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_D_POST_FILTER_LUMA_DPB0 + (4 * i)); + buf_addr += ctx->loopfilter_luma_size; + buf_size -= ctx->loopfilter_luma_size; + + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_D_POST_FILTER_CHROMA_DPB0 + (4 * i)); + buf_addr += ctx->loopfilter_chroma_size; + buf_size -= ctx->loopfilter_chroma_size; + } + reg |= ((dec->loop_filter_mpeg4 & MFC_REG_D_INIT_BUF_OPT_LF_CTRL_MASK) + << MFC_REG_D_INIT_BUF_OPT_LF_CTRL_SHIFT); + } + reg |= (dec->is_dynamic_dpb << MFC_REG_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT); + if (CODEC_NOT_CODED(ctx)) { + reg |= BIT(MFC_REG_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT); + mfc_debug(2, "Notcoded frame copy mode start\n"); + } + /* 16byte align, It is valid only for VP9 */ reg &= ~BIT(MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); - + if (IS_VP9_DEC(ctx) && MFC_FEATURE_SUPPORT(dev, dev->pdata->vp9_stride_align)) { + reg &= ~(0x3 << MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); + reg |= (0x2 << MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); + } reg &= ~BIT(MFC_REG_D_INIT_BUF_OPT_TWO_MODE_ENABLE_SHIFT); if (IS_MULTI_MODE(ctx)) { reg |= BIT(MFC_REG_D_INIT_BUF_OPT_TWO_MODE_ENABLE_SHIFT); @@ -158,7 +196,7 @@ int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx) frame_size_mv = ctx->mv_size; MFC_CORE_WRITEL(dec->mv_count, MFC_REG_D_NUM_MV); - if (IS_H264_DEC(ctx)) { + if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx) || IS_AV1_DEC(ctx)) { if (ctx->mv_buffer_allocated && buf_size && buf_size > ctx->mv_buf.dma_buf->size) { mfc_info("[MEMINFO] Not enough MV buf size %d alloc size %zu\n", diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h index e7c28b2f2b5d..08f74bd56f3f 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h @@ -89,12 +89,15 @@ >> MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT)\ & MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_MASK) +#define mfc_core_get_aspect_ratio() MFC_CORE_READL(MFC_REG_D_DISPLAY_ASPECT_RATIO) #define mfc_core_get_img_width() MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_WIDTH) #define mfc_core_get_img_height() MFC_CORE_READL(MFC_REG_D_DISPLAY_FRAME_HEIGHT) #define mfc_core_get_disp_y_addr() MFC_CORE_DMA_READL(MFC_REG_D_DISPLAY_LUMA_ADDR) #define mfc_core_get_dec_y_addr() MFC_CORE_DMA_READL(MFC_REG_D_DECODED_LUMA_ADDR) #define mfc_core_get_crc_luma() MFC_CORE_READL(MFC_REG_D_DISPLAY_FIRST_PLANE_CRC) #define mfc_core_get_crc_chroma() MFC_CORE_READL(MFC_REG_D_DISPLAY_SECOND_PLANE_CRC) +#define mfc_core_get_crc_luma_2bit() MFC_CORE_READL(MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC) +#define mfc_core_get_crc_chroma_2bit() MFC_CORE_READL(MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC) /* kind of interrupt */ #define mfc_core_get_int_err() MFC_CORE_READL(MFC_REG_ERROR_CODE) @@ -104,10 +107,13 @@ #define mfc_core_get_dpb_count() MFC_CORE_READL(MFC_REG_D_MIN_NUM_DPB) #define mfc_core_get_min_dpb_size(x) \ MFC_CORE_READL(MFC_REG_D_MIN_FIRST_PLANE_DPB_SIZE + ((x) * 4)) +#define mfc_core_get_min_dpb_size_2bit(x) \ + MFC_CORE_READL(MFC_REG_D_MIN_FIRST_PLANE_2BIT_DPB_SIZE + ((x) * 4)) #define mfc_core_get_scratch_size() MFC_CORE_READL(MFC_REG_D_MIN_SCRATCH_BUFFER_SIZE) #define mfc_core_get_stride_size(x) \ MFC_CORE_READL(MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE + ((x) * 4)) - +#define mfc_core_get_stride_size_2bit(x) \ + MFC_CORE_READL(MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE + ((x) * 4)) #define mfc_core_get_mv_count() MFC_CORE_READL(MFC_REG_D_MIN_NUM_MV) #define mfc_core_get_inst_no() MFC_CORE_READL(MFC_REG_RET_INSTANCE_ID) #define mfc_core_get_sei_avail() MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) @@ -133,14 +139,27 @@ #define mfc_core_get_sei_avail_mastering_display() ((MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) \ >> MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) \ & MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK) - +#define mfc_core_get_sei_avail_st_2094_40() ((MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) \ + >> MFC_REG_D_SEI_AVAIL_ST_2094_40_SHIFT) \ + & MFC_REG_D_SEI_AVAIL_ST_2094_40_MASK) +#define mfc_core_get_sei_nal_meta_status() ((MFC_CORE_READL(MFC_REG_METADATA_STATUS) \ + >> MFC_REG_SEI_NAL_STATUS_SHIFT) \ + & MFC_REG_SEI_NAL_STATUS_MASK) #define mfc_core_get_video_signal_type() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ >> MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) \ & MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK) #define mfc_core_get_colour_description() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ >> MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT) \ & MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK) - +#define mfc_core_get_primaries() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_COLOUR_PRIMARIES_SHIFT) \ + & MFC_REG_D_COLOUR_PRIMARIES_MASK) +#define mfc_core_get_transfer() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_TRANSFER_CHARACTERISTICS_SHIFT) \ + & MFC_REG_D_TRANSFER_CHARACTERISTICS_MASK) +#define mfc_core_get_matrix_coeff() ((MFC_CORE_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_MATRIX_COEFFICIENTS_SHIFT) \ + & MFC_REG_D_MATRIX_COEFFICIENTS_MASK) #define mfc_core_get_black_bar_pos_x() ((MFC_CORE_READL(MFC_REG_D_BLACK_BAR_START_POS) \ >> MFC_REG_D_BLACK_BAR_START_X_SHIFT) \ & MFC_REG_D_BLACK_BAR_START_X_MASK) @@ -160,12 +179,25 @@ & MFC_REG_D_MVC_VIEW_ID_DEC_MASK) #define mfc_core_get_mvc_view_id_disp_order() (MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ & MFC_REG_D_MVC_VIEW_ID_DISP_MASK) +#define mfc_core_get_mvc_left_view_id() ((MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ + >> MFC_REG_D_MVC_LEFT_VIEW_ID_SHIFT) \ + & MFC_REG_D_MVC_LEFT_VIEW_ID_MASK) #define mfc_core_get_mvc_right_view_id() ((MFC_CORE_READL(MFC_REG_D_MVC_VIEW_ID) \ >> MFC_REG_D_MVC_RIGHT_VIEW_ID_SHIFT) \ & MFC_REG_D_MVC_RIGHT_VIEW_ID_MASK) #define mfc_core_get_profile() (MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ & MFC_REG_D_DECODED_PIC_PROFILE_MASK) - +#define mfc_core_get_level() ((MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_PIC_LEVEL_SHIFT) \ + & MFC_REG_D_PIC_LEVEL_MASK) +#define mfc_core_get_luma_bit_depth_minus8() ((MFC_CORE_READL \ + (MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_SHIFT) \ + & MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_MASK) +#define mfc_core_get_chroma_bit_depth_minus8() ((MFC_CORE_READL \ + (MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT) \ + & MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_MASK) #define mfc_core_get_display_delay() \ ((MFC_CORE_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ >> MFC_REG_D_DISPLAY_DELAY_SHIFT) \ @@ -177,10 +209,34 @@ #define mfc_core_get_dec_used_flag() (((unsigned long)(MFC_CORE_READL \ (MFC_REG_D_USED_DPB_FLAG_UPPER)) << 32) | \ MFC_CORE_READL(MFC_REG_D_USED_DPB_FLAG_LOWER)) - +#define mfc_core_get_chroma_format() (MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ + & MFC_REG_D_CHROMA_FORMAT_MASK) +#define mfc_core_get_color_range() ((MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ + >> MFC_REG_D_COLOR_RANGE_SHIFT) \ + & MFC_REG_D_COLOR_RANGE_MASK) +#define mfc_core_get_color_space() ((MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ + >> MFC_REG_D_COLOR_SPACE_SHIFT) \ + & MFC_REG_D_COLOR_SPACE_MASK) #define mfc_core_get_num_of_tile() ((MFC_CORE_READL(MFC_REG_D_DECODED_STATUS) \ >> MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT) \ & MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK) +#define mfc_core_get_lcu_size() (MFC_CORE_READL(MFC_REG_D_HEVC_INFO) \ + & MFC_REG_D_HEVC_INFO_LCU_SIZE_MASK) +#define mfc_core_get_disp_res_change() ((MFC_CORE_READL(MFC_REG_D_VP9_INFO) \ + >> MFC_REG_D_VP9_INFO_DISP_RES_SHIFT) \ + & MFC_REG_D_VP9_INFO_DISP_RES_MASK) +#define mfc_core_get_disp_res_change_av1() ((MFC_CORE_READL(MFC_REG_D_AV1_INFO) \ + >> MFC_REG_D_AV1_INFO_DISP_RES_SHIFT) \ + & MFC_REG_D_AV1_INFO_DISP_RES_MASK) +#define mfc_core_get_showable_frame() ((MFC_CORE_READL(MFC_REG_D_AV1_INFO) \ + >> MFC_REG_D_AV1_INFO_SHOWABLE_FRAME_SHIFT) \ + & MFC_REG_D_AV1_INFO_SHOWABLE_FRAME_MASK) +#define mfc_core_get_multiple_show_frame() ((MFC_CORE_READL(MFC_REG_D_AV1_INFO) \ + >> MFC_REG_D_AV1_INFO_MULTIPLE_SHOW_SHIFT) \ + & MFC_REG_D_AV1_INFO_MULTIPLE_SHOW_MASK) +#define mfc_core_get_hevc_pic_output_flag() ((MFC_CORE_READL(MFC_REG_D_HEVC_INFO) \ + >> MFC_REG_D_HEVC_INFO_PIC_OUTPUT_FLAG_SHIFT) \ + & MFC_REG_D_HEVC_INFO_PIC_OUTPUT_FLAG_MASK) static inline void mfc_core_dec_get_crop_info(struct mfc_core *core, struct mfc_ctx *ctx) @@ -201,6 +257,15 @@ static inline void mfc_core_dec_get_crop_info(struct mfc_core *core, dec->cr_bot = bottom; } +static inline void mfc_core_clear_roi_enable(struct mfc_core *core) +{ + unsigned int reg = 0; + + reg = MFC_CORE_READL(MFC_REG_E_RC_ROI_CTRL); + reg &= ~(0x1); + MFC_CORE_WRITEL(reg, MFC_REG_E_RC_ROI_CTRL); +} + static inline void mfc_core_update_tag(struct mfc_core *core, struct mfc_ctx *ctx, int tag) { diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c index 118108f910e2..127d19c4d1cb 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c @@ -369,6 +369,10 @@ int mfc_core_run_dec_frame(struct mfc_core *core, struct mfc_ctx *ctx) last_frame = __mfc_check_last_frame(core_ctx, src_mb); ret = mfc_core_cmd_dec_one_frame(core, ctx, last_frame, src_index); + if (dec->consumed && IS_MULTI_MODE(ctx) && !CODEC_MULTIFRAME(ctx)) { + mfc_debug(2, "[STREAM][2CORE] clear consumed for next core\n"); + dec->consumed = 0; + } return ret; } diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c index 3097a6c0bf14..626c8db5f93b 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c @@ -9,6 +9,7 @@ * Himanshu Dewangan, <h.dewangan@samsung.com> */ +#include "mfc_dec_v4l2.h" #include "mfc_dec_vb2.h" #include "mfc_rm.h" -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035651epcas5p2a45576829011bbf653c725b352c65140@epcas5p2.samsung.com>]
* [PATCH 22/29] media: mfc: Add H.264 encoder support with buffer and QoS improvements [not found] ` <CGME20250930035651epcas5p2a45576829011bbf653c725b352c65140@epcas5p2.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Integrat H.264 encoding. - Allocate encoder‑specific context buffers and ROI memory. - Add detection macro and broadened codec‑type validation for QoS utilities. - Introduce encoder‑aware QoS tables and refined weight calculations (B‑frames, reference count). - Update source‑queue cleanup, framerate fallback, and timestamp‑delta handling. - Make stride and source‑size helpers encoder‑aware; exposed B‑frame detection utility. - Expand context structures with encoder buffers, private fields, ROI, and parameters. - Add platform flags for encoder‑specific QoS steps and feature support (e.g., RGB). Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_buf.c | 132 ++++++++++ .../samsung/exynos-mfc/base/mfc_buf.h | 3 + .../samsung/exynos-mfc/base/mfc_common.h | 24 +- .../samsung/exynos-mfc/base/mfc_data_struct.h | 231 ++++++++++++++++++ .../samsung/exynos-mfc/base/mfc_qos.c | 34 ++- .../samsung/exynos-mfc/base/mfc_queue.c | 31 +++ .../samsung/exynos-mfc/base/mfc_queue.h | 2 + .../exynos-mfc/base/mfc_rate_calculate.c | 30 ++- .../exynos-mfc/base/mfc_rate_calculate.h | 8 +- .../samsung/exynos-mfc/base/mfc_utils.c | 111 +++++++++ .../samsung/exynos-mfc/base/mfc_utils.h | 52 ++++ .../media/platform/samsung/exynos-mfc/mfc.c | 3 + 12 files changed, 654 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c index 84f97ca230bb..0186fe3327f1 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c @@ -132,6 +132,9 @@ int mfc_alloc_instance_context(struct mfc_core_ctx *core_ctx) case MFC_REG_CODEC_FIMV4_DEC: core_ctx->instance_ctx_buf.size = buf_size->other_dec_ctx; break; + case MFC_REG_CODEC_H264_ENC: + core_ctx->instance_ctx_buf.size = buf_size->h264_enc_ctx; + break; case MFC_REG_CODEC_AV1_DEC: core_ctx->instance_ctx_buf.size = buf_size->av1_dec_ctx; break; @@ -248,6 +251,64 @@ static void __mfc_dec_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) NUM_MPEG4_LF_BUF); } +static void __mfc_enc_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_enc *enc; + unsigned int mb_width, mb_height; + + enc = ctx->enc_priv; + enc->tmv_buffer_size = 0; + + mb_width = WIDTH_MB(ctx->crop_width); + mb_height = HEIGHT_MB(ctx->crop_height); + + /* default recon buffer size, it can be changed in case of 422, 10bit */ + enc->luma_dpb_size = + ALIGN(ENC_LUMA_DPB_SIZE(ctx->crop_width, ctx->crop_height), SZ_64); + enc->chroma_dpb_size = + ALIGN(ENC_CHROMA_DPB_SIZE(ctx->crop_width, ctx->crop_height), SZ_64); + + if (ctx->min_dpb_size[0] > enc->luma_dpb_size || + ctx->min_dpb_size[1] > enc->chroma_dpb_size) { + mfc_debug(2, + "[MEMINFO] recon DPB size changed (Luma: %zu -> %d, Chroma %zu -> %d)\n", + enc->luma_dpb_size, + ctx->min_dpb_size[0], + enc->chroma_dpb_size, + ctx->min_dpb_size[1]); + enc->luma_dpb_size = ctx->min_dpb_size[0]; + enc->chroma_dpb_size = ctx->min_dpb_size[1]; + } + + /* Codecs have different memory requirements */ + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_ENC: + enc->me_buffer_size = + ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), SZ_256); + + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + enc->tmv_buffer_size + + (ctx->dpb_count * (enc->luma_dpb_size + + enc->chroma_dpb_size + enc->me_buffer_size)); + break; + default: + core_ctx->codec_buf.size = 0; + mfc_err("invalid codec type: %d\n", ctx->codec_mode); + break; + } + + mfc_debug(2, + "[MEMINFO] scratch: %zu, TMV: %zu, (recon luma: %zu, chroma: %zu, me: %zu) x count %d\n", + ctx->scratch_buf_size, + enc->tmv_buffer_size, + enc->luma_dpb_size, + enc->chroma_dpb_size, + enc->me_buffer_size, + ctx->dpb_count); +} + /* Allocate codec buffers */ int mfc_alloc_codec_buffers(struct mfc_core_ctx *core_ctx) { @@ -259,6 +320,8 @@ int mfc_alloc_codec_buffers(struct mfc_core_ctx *core_ctx) if (ctx->type == MFCINST_DECODER) { __mfc_dec_calc_codec_buffer_size(core_ctx); + } else if (ctx->type == MFCINST_ENCODER) { + __mfc_enc_calc_codec_buffer_size(core_ctx); } else { mfc_err("invalid type: %d\n", ctx->type); return -EINVAL; @@ -401,6 +464,75 @@ void mfc_release_dbg_info_buffer(struct mfc_core *core) mfc_mem_special_buf_free(core->dev, &core->dbg_info_buf); } +/* Allocation buffer of ROI macroblock information */ +static int __mfc_alloc_enc_roi_buffer(struct mfc_core_ctx *core_ctx, + size_t size, + struct mfc_special_buf *roi_buf) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_dev *dev = core->dev; + + roi_buf->size = size; + roi_buf->buftype = MFCBUF_NORMAL; + + if (!roi_buf->dma_buf) { + snprintf(roi_buf->name, MFC_NUM_SPECIAL_BUF_NAME, "ctx%d ROI", core_ctx->num); + if (mfc_mem_special_buf_alloc(dev, roi_buf)) { + mfc_err("[ROI] Allocating ROI buffer failed\n"); + return -ENOMEM; + } + } + memset(roi_buf->vaddr, 0, roi_buf->size); + + return 0; +} + +/* Wrapper : allocation ROI buffers */ +int mfc_alloc_enc_roi_buffer(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_enc *enc = ctx->enc_priv; + unsigned int mb_width, mb_height; + size_t size; + int i; + + mb_width = WIDTH_MB(ctx->crop_width); + mb_height = HEIGHT_MB(ctx->crop_height); + + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_ENC: + size = ((((mb_width * (mb_height + 1) / 2) + 15) / 16) * 16) * 2; + break; + default: + mfc_debug(2, + "ROI not supported codec type(%d). Allocate with default size\n", + ctx->codec_mode); + size = mb_width * mb_height; + break; + } + + for (i = 0; i < MFC_MAX_EXTRA_BUF; i++) { + if (__mfc_alloc_enc_roi_buffer(core_ctx, size, &enc->roi_buf[i]) < 0) { + mfc_err("[ROI] Allocating remapping buffer[%d] failed\n", i); + return -ENOMEM; + } + } + + return 0; +} + +/* Release buffer of ROI macroblock information */ +void mfc_release_enc_roi_buffer(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_enc *enc = ctx->enc_priv; + int i; + + for (i = 0; i < MFC_MAX_EXTRA_BUF; i++) + if (enc->roi_buf[i].dma_buf) + mfc_mem_special_buf_free(ctx->dev, &enc->roi_buf[i]); +} + /* Allocate firmware */ int mfc_alloc_firmware(struct mfc_core *core) { diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h index 6907cf6ac775..67bdfaed5dd6 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h @@ -26,6 +26,9 @@ void mfc_release_codec_buffers(struct mfc_core_ctx *core_ctx); int mfc_alloc_scratch_buffer(struct mfc_core_ctx *core_ctx); void mfc_release_scratch_buffer(struct mfc_core_ctx *core_ctx); +int mfc_alloc_enc_roi_buffer(struct mfc_core_ctx *core_ctx); +void mfc_release_enc_roi_buffer(struct mfc_core_ctx *core_ctx); + int mfc_alloc_firmware(struct mfc_core *core); int mfc_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf, diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h index 5392c8566e42..bec6f88d5e44 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h @@ -170,6 +170,9 @@ ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_DEC && \ (profile) == MFC_REG_D_PROFILE_MULTIVIEW_HEVC_MAIN) +/* Encoder codec mode check */ +#define IS_H264_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_ENC) + #define CODEC_NOT_CODED(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ (IS_MPEG4_DEC(_ctx) || IS_VC1_DEC(_ctx) || IS_VC1_RCV_DEC(_ctx) || \ @@ -217,7 +220,16 @@ }) #define CODEC_HAS_IDR(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ - (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx) || IS_HEVC_DEC(_ctx)); \ + (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx) || IS_HEVC_DEC(_ctx) || \ + IS_H264_ENC(_ctx)); \ +}) + +// Buffer container +#define IS_BUFFER_BATCH_MODE(ctx) ((ctx)->batch_mode == 1) +#define IS_NO_HEADER_GENERATE(ctx, p) ({ \ + typeof(ctx) _ctx = (ctx); \ + typeof(p) _p = (p); \ + (_p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME); \ }) /* @@ -313,6 +325,13 @@ (_fps >= 240)); \ }) +#define IS_MULTI_MODE_ENC_RES(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + (IS_MULTI_MODE_RES(_ctx) || \ + (OVER_UHD_RES(_ctx) && _ctx->operating_framerate >= 60000) || \ + (OVER_UHD_RES(_ctx) && mfc_is_enc_bframe(_ctx))); \ +}) + #define IS_BLACKBAR_OFF(ctx) ((ctx)->crop_height > 2160) #define IS_SINGLE_FD(ctx, fmt) ((!(ctx)->rgb_bpp) && ((fmt)->mem_planes == 1)) @@ -404,6 +423,9 @@ static inline int mfc_core_get_pwr_ref_cnt(struct mfc_core *core) static inline int mfc_core_get_clk_ref_cnt(struct mfc_core *core) { + if (core->dev->pdata->support_hwacg == MFC_HWACG_HWFW_CTRL) + return 1; + return atomic_read(&core->clk_ref); } diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h index 6b93fe3ab138..6d34905a1cba 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h @@ -505,6 +505,9 @@ struct mfc_ctx_buf_size { size_t h264_dec_ctx; size_t av1_dec_ctx; size_t other_dec_ctx; + size_t h264_enc_ctx; + size_t hevc_enc_ctx; + size_t other_enc_ctx; size_t dbg_info_buf; }; @@ -711,6 +714,13 @@ struct mfc_bw_data { }; struct mfc_bw_info { + struct mfc_bw_data bw_enc_h264; + struct mfc_bw_data bw_enc_hevc; + struct mfc_bw_data bw_enc_hevc_10bit; + struct mfc_bw_data bw_enc_vp8; + struct mfc_bw_data bw_enc_vp9; + struct mfc_bw_data bw_enc_vp9_10bit; + struct mfc_bw_data bw_enc_mpeg4; struct mfc_bw_data bw_dec_h264; struct mfc_bw_data bw_dec_hevc; struct mfc_bw_data bw_dec_hevc_10bit; @@ -734,6 +744,7 @@ struct mfc_qos { unsigned int freq_mif; unsigned int mo_value; unsigned int mo_10bit_value; + unsigned int mo_uhd_enc60_value; unsigned int time_fw; unsigned int bts_scen_idx; const char *name; @@ -792,6 +803,7 @@ struct mfc_platdata { /* Formats */ unsigned int support_10bit; unsigned int support_422; + unsigned int support_rgb; /* Resolution */ unsigned int support_check_res; @@ -807,11 +819,26 @@ struct mfc_platdata { struct mfc_feature black_bar; struct mfc_feature color_aspect_dec; struct mfc_feature static_info_dec; + struct mfc_feature color_aspect_enc; + struct mfc_feature static_info_enc; struct mfc_feature vp9_stride_align; struct mfc_feature mem_clear; struct mfc_feature wait_fw_status; + struct mfc_feature average_qp; + struct mfc_feature mv_search_mode; + struct mfc_feature enc_idr_flag; + struct mfc_feature min_quality_mode; + struct mfc_feature enc_capability; + struct mfc_feature enc_ts_delta; + struct mfc_feature wfd_rc_mode; + struct mfc_feature max_i_frame_size; struct mfc_feature hevc_pic_output_flag; + /* Encoder default parameter */ + unsigned int enc_param_num; + unsigned int enc_param_addr[MFC_MAX_DEFAULT_PARAM]; + unsigned int enc_param_val[MFC_MAX_DEFAULT_PARAM]; + struct mfc_bw_info mfc_bw_info; unsigned int dynamic_weight; struct mfc_qos_weight qos_weight; @@ -835,7 +862,14 @@ struct mfc_platdata { unsigned int scheduler; unsigned int pbs_num_prio; + + unsigned int enc_rgb_csc_by_fw; + /* HWAPG */ + unsigned int support_hwapg; + /* HWACG */ enum mfc_hwacg_type support_hwacg; + + unsigned int support_enc_mode1; unsigned int support_mv_hevc; }; @@ -858,6 +892,7 @@ struct mfc_core_platdata { unsigned int tsmux_masterid; /* QoS */ unsigned int num_default_qos_steps; + unsigned int num_encoder_qos_steps; unsigned int max_mb; unsigned int max_hw_mb; unsigned int mfc_freq_control; @@ -994,6 +1029,9 @@ struct mfc_core_ops { /* for DEC */ void (*instance_dpb_flush)(struct mfc_core *core, struct mfc_ctx *ctx); int (*instance_init_buf)(struct mfc_core *core, struct mfc_ctx *ctx); + /* for ENC */ + void (*instance_q_flush)(struct mfc_core *core, struct mfc_ctx *ctx); + void (*instance_finishing)(struct mfc_core *core, struct mfc_ctx *ctx); }; struct dump_info { @@ -1148,6 +1186,150 @@ struct mfc_core { struct mfc_core_memlog memlog; }; +/** + * + */ +struct mfc_h264_enc_params { + enum v4l2_mpeg_video_h264_profile profile; + u8 level; + u8 interlace; + u16 open_gop_size; + u8 open_gop; + u8 _8x8_transform; + s8 loop_filter_alpha; + s8 loop_filter_beta; + enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; + enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; + u8 rc_frame_qp; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_min_qp_p; + u8 rc_max_qp_p; + u8 rc_min_qp_b; + u8 rc_max_qp_b; + u8 rc_mb_dark; + u8 rc_mb_smooth; + u8 rc_mb_static; + u8 rc_mb_activity; + u8 rc_p_frame_qp; + u8 rc_b_frame_qp; + u8 ar_vui; + u8 sei_gen_enable; + u8 sei_fp_curr_frame_0; + + enum v4l2_mpeg_video_h264_vui_sar_idc ar_vui_idc; + u16 ext_sar_width; + u16 ext_sar_height; + + enum v4l2_mpeg_video_h264_hierarchical_coding_type hier_qp_type; + u32 hier_bit_layer[7]; + u8 hier_qp_layer[7]; + u8 hier_qp_enable; + u8 num_hier_layer; + u8 hier_ref_type; + u8 enable_ltr; + u8 num_of_ltr; + u32 set_priority; + u32 base_priority; + + enum v4l2_mpeg_video_h264_sei_fp_arrangement_type sei_fp_arrangement_type; + u32 fmo_enable; + u32 fmo_slice_map_type; + u32 fmo_slice_num_grp; + u32 fmo_run_length[4]; + u32 fmo_sg_dir; + u32 fmo_sg_rate; + u32 aso_enable; + u32 aso_slice_order[8]; + + u32 prepend_sps_pps_to_idr; + u32 vui_enable; +}; + +/** + * + */ +struct mfc_enc_params { + enum v4l2_mpeg_video_multi_slice_mode slice_mode; + u32 slice_mb; + u32 slice_bit; + u32 slice_mb_row; + + u32 gop_ctrl; + u32 gop_size; + u32 intra_refresh_mb; + u32 i_frm_ctrl_mode; + u32 i_frm_ctrl; + + u8 pad; + u8 pad_luma; + u8 pad_cb; + u8 pad_cr; + + u8 rc_mb; /* H.264: MFCv5, MPEG4/H.263: MFCv6 */ + u8 rc_pvc; + u8 rc_frame; + u8 drop_control; + u32 rc_bitrate; + u32 rc_framerate; + u16 rc_reaction_coeff; + u16 rc_frame_delta; /* MFC6.1 Only */ + u32 rc_framerate_res; + u32 max_i_frame_size; /* when RC_MODE is 5(CBR_I_LIMIT_WFD = CBR_BS) */ + + u32 config_qp; + u32 dynamic_qp; + + u8 frame_tag; + u8 ratio_intra; + u8 num_b_frame; /* H.264, HEVC, MPEG4 */ + u8 num_refs_for_p; /* H.264, HEVC, VP8, VP9 */ + enum v4l2_mpeg_video_header_mode seq_hdr_mode; + enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; + u16 vbv_buf_size; + u8 num_hier_max_layer; + u8 hier_bitrate_ctrl; + u8 weighted_enable; + u8 roi_enable; + u8 ivf_header_disable; /* VP8, VP9 */ + u8 fixed_target_bit; + u8 min_quality_mode; /* H.264, HEVC when RC_MODE is 2(VBR) */ + u8 wp_two_pass_enable; + u8 adaptive_gop_enable; + + u32 check_color_range; + u32 color_range; + u32 colour_primaries; + u32 transfer_characteristics; + u32 matrix_coefficients; + + u32 static_info_enable; + u32 max_pic_average_light; + u32 max_content_light; + u32 max_display_luminance; + u32 min_display_luminance; + u32 white_point; + u32 display_primaries_0; + u32 display_primaries_1; + u32 display_primaries_2; + u32 chroma_qp_offset_cb; /* H.264, HEVC */ + u32 chroma_qp_offset_cr; /* H.264, HEVC */ + + u32 mv_search_mode; + u32 mv_hor_pos_l0; + u32 mv_hor_pos_l1; + u32 mv_ver_pos_l0; + u32 mv_ver_pos_l1; + u32 mv_hor_range; + u32 mv_ver_range; + + u8 timing_info_enable; /* H.264, HEVC */ + + union { + struct mfc_h264_enc_params h264; + } codec; +}; + struct mfc_ctx_ctrl_val { int has_new; int val; @@ -1234,6 +1416,14 @@ struct temporal_layer_info { unsigned int temporal_layer_bitrate[VIDEO_MAX_TEMPORAL_LAYERS]; }; +struct mfc_enc_roi_info { + char *addr; + int size; + int upper_qp; + int lower_qp; + bool enable; +}; + struct mfc_user_shared_handle { int fd; struct dma_buf *dma_buf; @@ -1379,6 +1569,43 @@ struct mfc_dec { unsigned char frame_cnt; }; +struct mfc_enc { + unsigned int dst_buf_size; + unsigned int header_size; + + enum v4l2_mpeg_mfc51_video_frame_type frame_type; + enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; + + unsigned int idr_flag; + + size_t luma_dpb_size; + size_t chroma_dpb_size; + size_t me_buffer_size; + size_t tmv_buffer_size; + + unsigned int slice_mode; + unsigned int slice_size_mb; + unsigned int slice_size_bits; + unsigned int in_slice; + unsigned int buf_full; + + int config_qp; + + struct mfc_fmt *uncomp_fmt; + + int fake_src; + int empty_data; + + int roi_index; + struct mfc_special_buf roi_buf[MFC_MAX_EXTRA_BUF]; + struct mfc_enc_roi_info roi_info[MFC_MAX_EXTRA_BUF]; + + struct mfc_enc_params params; + + struct mfc_user_shared_handle sh_handle_svc; + struct mfc_user_shared_handle sh_handle_roi; +}; + struct mfc_resolution { int width; int height; @@ -1414,6 +1641,7 @@ struct mfc_multi_view_buf_info { struct mfc_ctx { struct mfc_dev *dev; struct mfc_dec *dec_priv; + struct mfc_enc *enc_priv; int num; int prio; @@ -1542,6 +1770,9 @@ struct mfc_ctx { dma_addr_t last_src_addr; dma_addr_t last_dst_addr[MFC_MAX_PLANES]; + /* buffer container */ + int batch_mode; + bool mem_type_10bit; unsigned long gdc_ready_buf_ino; diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c index 9922c2396b94..40541e2d626f 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c @@ -20,17 +20,25 @@ static inline int __mfc_core_get_qos_steps(struct mfc_core *core, int table_type) { - return core->core_pdata->num_default_qos_steps; + if (table_type == MFC_QOS_TABLE_TYPE_ENCODER) + return core->core_pdata->num_encoder_qos_steps; + else + return core->core_pdata->num_default_qos_steps; } static inline struct mfc_qos *__mfc_core_get_qos_table(struct mfc_core *core, int table_type) { - return core->core_pdata->default_qos_table; + if (table_type == MFC_QOS_TABLE_TYPE_ENCODER) + return core->core_pdata->encoder_qos_table; + else + return core->core_pdata->default_qos_table; } static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned long mb) { + struct mfc_enc *enc = ctx->enc_priv; struct mfc_dec *dec = ctx->dec_priv; + struct mfc_enc_params *p; struct mfc_qos_weight *qos_weight = &ctx->dev->pdata->qos_weight; u32 num_planes = ctx->dst_fmt->num_planes; int weight = 1000; @@ -39,6 +47,8 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l switch (ctx->codec_mode) { case MFC_REG_CODEC_H264_DEC: case MFC_REG_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_H264_MVC_ENC: weight = (weight * 100) / qos_weight->weight_h264_hevc; mfc_ctx_debug(3, "[QoS] h264, hevc codec, weight: %d\n", weight / 10); if (num_planes == 3) { @@ -107,6 +117,16 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l mfc_ctx_err("[QoS] wrong codec_mode (%d), no weight\n", ctx->codec_mode); } + if (enc) { + p = &enc->params; + if (mfc_is_enc_bframe(ctx)) { + weight = (weight * 100) / qos_weight->weight_bframe; + mfc_ctx_debug(3, "[QoS] B frame encoding, weight: %d\n", weight / 10); + } else if (IS_H264_ENC(ctx) && (p->num_refs_for_p >= 2)) { + weight = (weight * 100) / qos_weight->weight_num_of_ref; + mfc_ctx_debug(3, "[QoS] num of ref >= 2, weight: %d\n", weight / 10); + } + } if (dec) { if (dec->num_of_tile_over_4) { weight = (weight * 100) / qos_weight->weight_num_of_tile; @@ -223,7 +243,10 @@ void mfc_qos_get_portion(struct mfc_core *core, struct mfc_ctx *ctx) if (!ctx->mfc_qos_portion) return; - table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + if (ctx->type == MFCINST_ENCODER) + table_type = MFC_QOS_TABLE_TYPE_ENCODER; + else + table_type = MFC_QOS_TABLE_TYPE_DEFAULT; num_qos_steps = __mfc_core_get_qos_steps(core, table_type); qos_table = __mfc_core_get_qos_table(core, table_type); @@ -390,7 +413,8 @@ bool mfc_qos_mb_calculate(struct mfc_core *core, struct mfc_core_ctx *core_ctx, if (ctx->type == MFCINST_DECODER) table_type = MFC_QOS_TABLE_TYPE_DEFAULT; - + else + table_type = MFC_QOS_TABLE_TYPE_ENCODER; num_qos_steps = __mfc_core_get_qos_steps(core, table_type); if (atomic_read(&core->qos_req_cur)) { @@ -652,6 +676,8 @@ void __mfc_qos_calculate(struct mfc_core *core, struct mfc_ctx *ctx, int delete) if (dec_found) table_type = MFC_QOS_TABLE_TYPE_DEFAULT; + else + table_type = MFC_QOS_TABLE_TYPE_ENCODER; num_qos_steps = __mfc_core_get_qos_steps(core, table_type); qos_table = __mfc_core_get_qos_table(core, table_type); diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c index 6dc9bc7a1873..81e649bb4e1e 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c @@ -539,6 +539,37 @@ void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue) spin_unlock_irqrestore(plock, flags); } +void mfc_cleanup_enc_src_queue(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + unsigned long flags; + struct mfc_buf *mfc_buf = NULL; + struct mfc_buf_queue *queue = &core_ctx->src_buf_queue; + int i; + + spin_lock_irqsave(&ctx->buf_queue_lock, flags); + + while (!list_empty(&queue->head)) { + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); + + for (i = 0; i < mfc_buf->vb.vb2_buf.num_planes; i++) { + if (IS_BUFFER_BATCH_MODE(ctx)) + mfc_bufcon_put_daddr(ctx, mfc_buf, i); + vb2_set_plane_payload(&mfc_buf->vb.vb2_buf, i, 0); + } + + vb2_buffer_done(&mfc_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + list_del(&mfc_buf->list); + queue->count--; + } + + INIT_LIST_HEAD(&queue->head); + queue->count = 0; + ctx->batch_mode = 0; + + spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); +} + void mfc_print_dpb_queue(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec) { struct mfc_ctx *ctx = core_ctx->ctx; diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h index 055e7a23a527..cfe889e0dcc9 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h @@ -145,6 +145,8 @@ void mfc_return_buf_to_ready_queue(struct mfc_ctx *ctx, void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue); +void mfc_cleanup_enc_src_queue(struct mfc_core_ctx *core_ctx); + void mfc_print_dpb_queue(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec); void mfc_print_dpb_queue_with_lock(struct mfc_core_ctx *core_ctx, struct mfc_dec *dec); int mfc_get_available_dpb_count(struct mfc_core_ctx *core_ctx); diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c index 94a555c900d7..c88101d1d1c1 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c @@ -293,6 +293,7 @@ static unsigned long __mfc_rate_get_fps_by_timestamp(struct mfc_ctx *ctx, struct mfc_ts_control *ts, struct timespec64 *time, int type) { + struct list_head *head = &ts->ts_list; struct mfc_timestamp *temp_ts; int found; int index = 0; @@ -304,6 +305,13 @@ static unsigned long __mfc_rate_get_fps_by_timestamp(struct mfc_ctx *ctx, unsigned long flags; u64 current_time; + if (IS_BUFFER_BATCH_MODE(ctx)) { + if (ctx->dev->debugfs.debug_ts == 1) + mfc_ctx_info("[BUFCON][TS] Keep framerate if buffer batch mode is used, %ldfps\n", + ctx->framerate); + return ctx->framerate; + } + spin_lock_irqsave(&ts->ts_lock, flags); if (list_empty(&ts->ts_list)) { __mfc_rate_add_timestamp(ctx, ts, time, &ts->ts_list); @@ -362,6 +370,19 @@ static unsigned long __mfc_rate_get_fps_by_timestamp(struct mfc_ctx *ctx, spin_unlock_irqrestore(&ts->ts_lock, flags); } + /* Calculation the last frame fps for drop control */ + if (ctx->type == MFCINST_ENCODER) { + temp_ts = list_entry(head->prev, struct mfc_timestamp, list); + if (temp_ts->interval > USEC_PER_SEC) { + if (ts->ts_is_full) + mfc_ctx_info("[TS] ts interval(%d) couldn't over 1sec(1fps)\n", + temp_ts->interval); + ts->ts_last_interval = 0; + } else { + ts->ts_last_interval = temp_ts->interval; + } + } + if (!ts->ts_is_full) { if (ctx->dev->debugfs.debug_ts == 1) mfc_ctx_info("[TS] ts doesn't full, keep %ld fps\n", ctx->framerate); @@ -581,7 +602,14 @@ int mfc_rate_check_perf_ctx(struct mfc_ctx *ctx, int max_runtime) op_fps = ctx->operating_framerate; if (op_fps == 0) { - op_fps = ctx->src_q_framerate; + if (ctx->type == MFCINST_ENCODER && ctx->enc_priv->params.rc_framerate) + op_fps = ctx->enc_priv->params.rc_framerate; + else + /* + * In case of non-real-time, check the buffer queueing rate + * because the non-real-time is best effort scenario. (ex. video editing) + */ + op_fps = ctx->src_q_framerate; mfc_ctx_debug(2, "[PRIO][rt %d] use fps: %d\n", ctx->rt, op_fps); } diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h index 2452e6ee56dd..530ad6fed489 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h @@ -45,6 +45,8 @@ static inline void mfc_rate_reset_framerate(struct mfc_ctx *ctx) { if (ctx->type == MFCINST_DECODER) ctx->framerate = DEC_DEFAULT_FPS; + else if (ctx->type == MFCINST_ENCODER) + ctx->framerate = ENC_DEFAULT_FPS; mfc_ctx_debug(3, "[QoS] reset ctx->framrate: %lu\n", ctx->framerate); } @@ -80,7 +82,11 @@ static inline unsigned long mfc_rate_get_rt_framerate(struct mfc_ctx *ctx, enum framerate = ctx->operating_framerate; - if (rt == MFC_RT_UNDEFINED || rt == MFC_NON_RT) { + if (rt == MFC_RT) { + if (framerate == 0 && ctx->type == MFCINST_ENCODER && + ctx->enc_priv->params.rc_framerate) + framerate = ctx->enc_priv->params.rc_framerate; + } else if (rt == MFC_RT_UNDEFINED || rt == MFC_NON_RT) { framerate = ctx->framerate; } else { if (ctx->src_ts.ts_is_full) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c index 83cdae3dee57..6dba87fb951b 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c @@ -108,6 +108,59 @@ static void __mfc_set_dec_stride(struct mfc_ctx *ctx, } } +static void __mfc_set_enc_stride(struct mfc_ctx *ctx, + struct mfc_raw_info *raw, + struct mfc_fmt *fmt) +{ + int i, y_stride, stride_align = 16; + + y_stride = ctx->bytesperline[0]; + if (!y_stride) + y_stride = ALIGN(ctx->img_width, stride_align); + + for (i = 0; i < MFC_MAX_PLANES; i++) { + raw->stride[i] = 0; + raw->stride_2bits[i] = 0; + } + + switch (fmt->fourcc) { + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + case V4L2_PIX_FMT_NV12MT_16X16: + case V4L2_PIX_FMT_NV12MT: + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + /* use user stride */ + for (i = 0; i < ctx->src_fmt->num_planes; i++) { + raw->stride[i] = ctx->bytesperline[i]; + if (!raw->stride[i]) + raw->stride[i] = ALIGN(ctx->img_width, stride_align); + } + break; + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_RGB32X: + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_ARGB32: + case V4L2_PIX_FMT_RGB32: + raw->stride[0] = y_stride * (ctx->rgb_bpp / 8); + break; + default: + mfc_ctx_err("Invalid pixelformat : %s\n", fmt->name); + break; + } + + for (i = 0; i < ctx->src_fmt->num_planes; i++) { + if ((raw->stride[i] % stride_align) != 0) { + mfc_ctx_err("[FRAME] Forced to change stride[%d] %d for %dbyte alignment\n", + i, raw->stride[i], stride_align); + raw->stride[i] = ALIGN(raw->stride[i], stride_align); + } + } +} + void mfc_set_linear_stride_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt) { /* @@ -117,6 +170,8 @@ void mfc_set_linear_stride_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, s */ if (ctx->type == MFCINST_DECODER) __mfc_set_dec_stride(ctx, raw, fmt); + else + __mfc_set_enc_stride(ctx, raw, fmt); } void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt) @@ -201,6 +256,62 @@ void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct } } +void mfc_enc_calc_src_size(struct mfc_ctx *ctx) +{ + struct mfc_raw_info *raw; + int i, extra; + + raw = &ctx->raw_buf; + raw->total_plane_size = 0; + extra = MFC_LINEAR_BUF_SIZE; + + mfc_set_linear_stride_size(ctx, raw, ctx->src_fmt); + + for (i = 0; i < raw->num_planes; i++) { + raw->plane_size[i] = 0; + raw->plane_size_2bits[i] = 0; + } + + switch (ctx->src_fmt->fourcc) { + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) / 2 + extra; + raw->plane_size[2] = raw->stride[2] * ALIGN(ctx->img_height, 16) / 2 + extra; + break; + case V4L2_PIX_FMT_NV12MT_16X16: + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) / 2 + extra; + break; + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + raw->plane_size[0] = raw->stride[0] * ALIGN(ctx->img_height, 16) + extra; + raw->plane_size[1] = raw->stride[1] * ALIGN(ctx->img_height, 16) + extra; + break; + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_RGB32X: + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_ARGB32: + case V4L2_PIX_FMT_RGB32: + raw->plane_size[0] = raw->stride[0] * ctx->img_height; + break; + default: + mfc_ctx_err("Invalid pixel format(%d)\n", ctx->src_fmt->fourcc); + break; + } + + for (i = 0; i < raw->num_planes; i++) { + raw->total_plane_size += raw->plane_size[i]; + mfc_ctx_debug(2, "[FRAME] Plane[%d] size = %d, stride = %d\n", + i, raw->plane_size[i], raw->stride[i]); + } + + mfc_ctx_debug(2, "[FRAME] total plane size: %d\n", raw->total_plane_size); +} + void mfc_calc_base_addr(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct mfc_fmt *fmt) { diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h index dedfb049e6fc..a127f330fe16 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h @@ -212,10 +212,37 @@ static inline int mfc_check_mb_flag(struct mfc_buf *mfc_buf, enum mfc_mb_flag f) return 0; } +static inline int mfc_is_enc_bframe(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc; + struct mfc_enc_params *p; + int hier_qp_type = -EINVAL; + u8 num_hier_layer = 0; + + if (ctx->type != MFCINST_ENCODER) + return 0; + enc = ctx->enc_priv; + if (!enc) + return 0; + + p = &enc->params; + if (IS_H264_ENC(ctx)) { + num_hier_layer = p->codec.h264.num_hier_layer; + hier_qp_type = (int)p->codec.h264.hier_qp_type; + } + if (enc->params.num_b_frame || + (num_hier_layer >= 2 && + hier_qp_type == V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B)) + return 1; + + return 0; +} + int mfc_check_vb_with_fmt(struct mfc_fmt *fmt, struct vb2_buffer *vb); int mfc_check_resolution(struct mfc_ctx *ctx); void mfc_set_linear_stride_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt); void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx, struct mfc_raw_info *raw, struct mfc_fmt *fmt); +void mfc_enc_calc_src_size(struct mfc_ctx *ctx); void mfc_calc_base_addr(struct mfc_ctx *ctx, struct vb2_buffer *vb, struct mfc_fmt *fmt); void mfc_set_view_buf_info(struct mfc_ctx *ctx, int mem_planes, int num_fd_depth_map, int num_fd_sub_view_meta); @@ -355,6 +382,31 @@ static inline void mfc_ctx_change_idle_mode(struct mfc_ctx *ctx, ctx->idle_mode = idle_mode; } +static inline int mfc_enc_get_ts_delta(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + int ts_delta = 0; + + if (!ctx->src_ts.ts_last_interval) { + ts_delta = p->rc_framerate_res / p->rc_framerate; + mfc_ctx_debug(3, "[DFR] default delta: %d\n", ts_delta); + } else { + /* + * FRAME_DELTA specifies the amount of + * increment of frame modulo base time. + * - delta unit = framerate resolution / fps + * - fps = 1000000(usec per sec) / timestamp interval + * For the sophistication of calculation, we will divide later. + * Excluding H.263, resolution is fixed to 10000, + * so thie is also divided into pre-calculated 100. + * (Preventing both overflow and calculation duplication) + */ + ts_delta = ctx->src_ts.ts_last_interval / 100; + } + return ts_delta; +} + static inline void mfc_print_ctx_info(struct mfc_ctx *ctx) { struct mfc_fmt *codec = NULL; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc.c b/drivers/media/platform/samsung/exynos-mfc/mfc.c index 293a353c49fa..db17448eae13 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc.c @@ -1128,6 +1128,9 @@ struct mfc_ctx_buf_size mfc_ctx_buf_size = { .h264_dec_ctx = PAGE_ALIGN(0x200000), /* 1.6MB */ .av1_dec_ctx = PAGE_ALIGN(0x19000), /* 100KB */ .other_dec_ctx = PAGE_ALIGN(0xF000), /* 60KB */ + .h264_enc_ctx = PAGE_ALIGN(0x19000), /* 100KB */ + .hevc_enc_ctx = PAGE_ALIGN(0xC800), /* 50KB */ + .other_enc_ctx = PAGE_ALIGN(0xC800), /* 50KB */ .dbg_info_buf = PAGE_ALIGN(0x1000), /* 4KB for DEBUG INFO */ }; -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035654epcas5p1cbb6f3d0fe0dd25758085d041f020846@epcas5p1.samsung.com>]
* [PATCH 23/29] media: mfc: Add encoder parameters, ROI & QoS support [not found] ` <CGME20250930035654epcas5p1cbb6f3d0fe0dd25758085d041f020846@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Introduce a generic encoder‑parameter framework (slice mode, ASO order, QP config, timestamp delta). - Expose full V4L2 encoder controls (frame tag, RC limits, level/profile, ROI, weighted prediction, hierarchical coding). - Implemente ROI handling by building ROI registers from per‑buffer data. - Update encoder resource manager: fixed core integration, excluded from migration/load‑balancing, ensured proper finalization per buffer type, and add encoder‑specific QoS step table. - Disable bitrate‑driven load‑balancing for encoders; framerate updates now apply only to non‑encoder contexts. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../samsung/exynos-mfc/mfc_core_enc_param.c | 848 ++++++++++++++++++ .../samsung/exynos-mfc/mfc_core_enc_param.h | 23 + .../samsung/exynos-mfc/mfc_ctx_ctrl.c | 803 +++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_rm.c | 89 +- .../platform/samsung/exynos-mfc/mfc_rm.h | 2 + 6 files changed, 1755 insertions(+), 12 deletions(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index b6b312ae7f22..a257d5b0a576 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -13,7 +13,7 @@ exynos_mfc-y += mfc_core_hwlock.o mfc_core_intlock.o mfc_core_run.o exynos_mfc-y += mfc_core_pm.o exynos_mfc-y += mfc_core_sync.o mfc_core_sched_prio.o #Core HW access layer -exynos_mfc-y += mfc_core_buf_ctrl.o mfc_core_cmd.o +exynos_mfc-y += mfc_core_enc_param.o mfc_core_buf_ctrl.o mfc_core_cmd.o exynos_mfc-y += mfc_core_hw_reg_api.o mfc_core_reg_api.o #Plugin interface layer #Plugin control layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c new file mode 100644 index 000000000000..9ff949df04ab --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_core_enc_param.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_core_enc_param.h" + +#include "mfc_core_reg_api.h" + +/* Definition */ +#define VBR_BIT_SAVE 20 +#define CBR_FIX_MAX 10 +#define CBR_I_LIMIT_WFD 6 +#define CBR_I_LIMIT_MAX 5 + +static int mfc_transfer_to_rgb_format_ctrl[][2] = { + { MFC_TRANSFER_RESERVED, 1}, + { MFC_TRANSFER_BT709, 1}, + { MFC_TRANSFER_UNSPECIFIED, 1}, + { MFC_TRANSFER_RESERVED, 1}, + { MFC_TRANSFER_GAMMA_22, 1}, + { MFC_TRANSFER_GAMMA_28, 1}, + { MFC_TRANSFER_SMPTE_170M, 0}, + { MFC_TRANSFER_SMPTE_240M, 1}, + { MFC_TRANSFER_LINEAR, 1}, + { MFC_TRANSFER_LOGARITHMIC, 1}, + { MFC_TRANSFER_LOGARITHMIC_S, 1}, + { MFC_TRANSFER_XvYCC, 1}, + { MFC_TRANSFER_BT1361, 1}, + { MFC_TRANSFER_SRGB, 1}, + { MFC_TRANSFER_BT2020_1, 1}, + { MFC_TRANSFER_BT2020_2, 1}, + { MFC_TRANSFER_ST2084, 1}, + { MFC_TRANSFER_ST428, 1}, + { MFC_TRANSFER_HLG, 1}, +}; + +void mfc_core_set_slice_mode(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + + /* multi-slice control */ + if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) + MFC_CORE_RAW_WRITEL((enc->slice_mode + 0x4), MFC_REG_E_MSLICE_MODE); + else if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW) + MFC_CORE_RAW_WRITEL((enc->slice_mode - 0x2), MFC_REG_E_MSLICE_MODE); + else if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES) + MFC_CORE_RAW_WRITEL((enc->slice_mode + 0x3), MFC_REG_E_MSLICE_MODE); + else + MFC_CORE_RAW_WRITEL(enc->slice_mode, MFC_REG_E_MSLICE_MODE); + + /* multi-slice MB number or bit size */ + if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB || + enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW) { + MFC_CORE_RAW_WRITEL(enc->slice_size_mb, MFC_REG_E_MSLICE_SIZE_MB); + } else if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES || + enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES) { + MFC_CORE_RAW_WRITEL(enc->slice_size_bits, MFC_REG_E_MSLICE_SIZE_BITS); + } else { + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_MSLICE_SIZE_MB); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_MSLICE_SIZE_BITS); + } +} + +void mfc_core_set_aso_slice_order_h264(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_h264_enc_params *p_264 = &p->codec.h264; + int i; + + if (p_264->aso_enable) { + for (i = 0; i < 8; i++) + MFC_CORE_RAW_WRITEL + (p_264->aso_slice_order[i], + MFC_REG_E_H264_ASO_SLICE_ORDER_0 + i * 4); + } +} + +void mfc_core_set_enc_config_qp(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + + if (!p->rc_frame && !p->rc_mb && p->dynamic_qp) { + reg = MFC_CORE_READL(MFC_REG_E_FIXED_PICTURE_QP); + reg &= ~(0xFF000000); + reg |= (enc->config_qp & 0xFF) << 24; + MFC_CORE_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + } +} + +void mfc_core_set_enc_ts_delta(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + int ts_delta; + + ts_delta = mfc_enc_get_ts_delta(ctx); + + reg = MFC_CORE_READL(MFC_REG_E_TIME_STAMP_DELTA); + reg &= ~(0xFFFF); + reg |= (ts_delta & 0xFFFF); + MFC_CORE_WRITEL(reg, MFC_REG_E_TIME_STAMP_DELTA); + if (ctx->src_ts.ts_last_interval) + mfc_ctx_debug(3, "[DFR] fps %d -> %ld, delta: %d, reg: %#x\n", + p->rc_framerate, USEC_PER_SEC / ctx->src_ts.ts_last_interval, + ts_delta, reg); + else + mfc_ctx_debug(3, "[DFR] fps %d -> 0, delta: %d, reg: %#x\n", + p->rc_framerate, ts_delta, reg); +} + +static void __mfc_set_gop_size(struct mfc_core *core, + struct mfc_ctx *ctx, + int ctrl_mode) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + + if (ctrl_mode) { + p->i_frm_ctrl_mode = 1; + /* + * gop_ctrl 1: gop_size means the I frame interval + * gop_ctrl 0: gop_size means the number of P frames. + */ + if (p->gop_ctrl) { + p->i_frm_ctrl = p->gop_size; + } else { + p->i_frm_ctrl = p->gop_size * (p->num_b_frame + 1); + if (p->i_frm_ctrl >= 0x3FFFFFFF) { + mfc_ctx_info("I frame interval is bigger than max: %d\n", + p->i_frm_ctrl); + p->i_frm_ctrl = 0x3FFFFFFF; + } + } + } else { + p->i_frm_ctrl_mode = 0; + p->i_frm_ctrl = p->gop_size; + } + + mfc_ctx_debug(2, "I frame interval: %d, (P: %d, B: %d), ctrl mode: %d, gop ctrl: %d\n", + p->i_frm_ctrl, + p->gop_ctrl ? (p->gop_size / (p->num_b_frame + 1)) : p->gop_size, + p->num_b_frame, p->i_frm_ctrl_mode, p->gop_ctrl); + + /* pictype : IDR period, number of B */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_GOP_CONFIG); + mfc_clear_set_bits(reg, 0xFFFF, 0, p->i_frm_ctrl); + mfc_clear_set_bits(reg, 0x1, 19, p->i_frm_ctrl_mode); + /* if B frame is used, the performance falls by half */ + mfc_clear_set_bits(reg, 0x3, 16, p->num_b_frame); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_GOP_CONFIG); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_GOP_CONFIG2); + mfc_clear_set_bits(reg, 0x3FFF, 0, (p->i_frm_ctrl >> 16)); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_GOP_CONFIG2); +} + +static void __mfc_set_default_params(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + int i; + + mfc_ctx_debug(2, "Set default param - enc_param_num: %d\n", + dev->pdata->enc_param_num); + for (i = 0; i < dev->pdata->enc_param_num; i++) { + if (i >= MFC_MAX_DEFAULT_PARAM) { + mfc_ctx_err("enc_param_num(%d) is over max number(%d)\n", + dev->pdata->enc_param_num, + MFC_MAX_DEFAULT_PARAM); + break; + } + MFC_CORE_RAW_WRITEL + (dev->pdata->enc_param_val[i], dev->pdata->enc_param_addr[i]); + mfc_ctx_debug(2, "Set default param[%d] - addr:0x%x, val:0x%x\n", + i, dev->pdata->enc_param_addr[i], + dev->pdata->enc_param_val[i]); + } +} + +static void __mfc_init_regs(struct mfc_core *core, struct mfc_ctx *ctx) +{ + /* Register initialization */ + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_FRAME_INSERTION); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_ROI_BUFFER_ADDR); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_PARAM_CHANGE); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_PICTURE_TAG); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_METADATA_BUFFER_ADDR); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_METADATA_BUFFER_SIZE); +} + +static int __mfc_get_rgb_format_ctrl(struct mfc_ctx *ctx, struct mfc_enc_params *p) +{ + int ret = 0; + + /* + * User set color VUI information as below regardless of the standard. + * --------------------------------------------- + * VP9 | others + * ----------------------|---------------------- + * color space only | primaries, transfer + * (primaries interface) | ,matrix + * --------------------------------------------- + * However, in case of RGB encoding, the F/W need to know + * which to use RGB pixel format transform characteristic. + * So, driver converts it based on the user's VUI information. + * Return value + * 0: ITU-R BT.601 + * 1: ITU-R BT.709 + * If Set to 3, use the coefficients of CSC formula determined by firmware + * on COLOR_SPACE and COLOUR_PRIMARIES of E_VIDEO_SIGNAL_TYPE. + * 3: Determined by firmware + */ + + if (ctx->dev->pdata->enc_rgb_csc_by_fw) { + ret = 3; + mfc_ctx_debug(2, "[RGB] coefficients of CSC formula using VUI by F/W\n"); + } else { + ret = mfc_transfer_to_rgb_format_ctrl[p->transfer_characteristics][1]; + mfc_ctx_debug(2, "[RGB] transfer %d converts to RGB format ctrl %s\n", + p->transfer_characteristics, ret ? "BT.709" : "BT.601"); + } + + return ret; +} + +static void __mfc_set_video_signal_type(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + + if ((ctx->src_fmt->type & MFC_FMT_RGB) && !dev->pdata->enc_rgb_csc_by_fw) { + /* VIDEO_SIGNAL_TYPE_FLAG */ + mfc_set_bits(reg, 0x1, 31, 0x1); + /* COLOUR_DESCRIPTION_PRESENT_FLAG */ + mfc_set_bits(reg, 0x1, 24, 0x1); + } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && + p->check_color_range) { + /* VIDEO_SIGNAL_TYPE_FLAG */ + mfc_set_bits(reg, 0x1, 31, 0x1); + /* COLOR_RANGE */ + if (!(ctx->src_fmt->type & MFC_FMT_RGB)) + mfc_set_bits(reg, 0x1, 25, p->color_range); + + if (p->colour_primaries && + p->transfer_characteristics && + p->matrix_coefficients != 3) { + /* COLOUR_DESCRIPTION_PRESENT_FLAG */ + mfc_set_bits(reg, 0x1, 24, 0x1); + /* COLOUR_PRIMARIES */ + mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); + /* TRANSFER_CHARACTERISTICS */ + mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); + /* MATRIX_COEFFICIENTS */ + mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); + } + mfc_ctx_debug(2, "[HDR] %s ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", + "H264", + p->color_range ? "Full" : "Limited", p->colour_primaries, + p->transfer_characteristics, p->matrix_coefficients); + } + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); +} + +static void __mfc_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + unsigned int fps = ctx->operating_framerate / 1000; + + mfc_ctx_debug_enter(); + + __mfc_init_regs(core, ctx); + __mfc_set_default_params(core, ctx); + + /* width */ + MFC_CORE_RAW_WRITEL(ctx->crop_width, MFC_REG_E_CROPPED_FRAME_WIDTH); + /* height */ + MFC_CORE_RAW_WRITEL(ctx->crop_height, MFC_REG_E_CROPPED_FRAME_HEIGHT); + /* cropped offset */ + mfc_set_bits(reg, MFC_REG_E_FRAME_CROP_OFFSET_MASK, + MFC_REG_E_FRAME_CROP_OFFSET_LEFT, ctx->crop_left); + mfc_set_bits(reg, MFC_REG_E_FRAME_CROP_OFFSET_MASK, + MFC_REG_E_FRAME_CROP_OFFSET_TOP, ctx->crop_top); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FRAME_CROP_OFFSET); + + /* multi-slice control */ + /* multi-slice MB number or bit size */ + enc->slice_mode = p->slice_mode; + + if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) { + enc->slice_size_mb = p->slice_mb; + } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES || + p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES) { + enc->slice_size_bits = p->slice_bit; + } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW) { + enc->slice_size_mb = p->slice_mb_row * ((ctx->crop_width + 15) / 16); + } else { + enc->slice_size_mb = 0; + enc->slice_size_bits = 0; + } + + mfc_core_set_slice_mode(core, ctx); + + /* config qp */ + enc->config_qp = p->config_qp; + + /* cyclic intra refresh */ + MFC_CORE_RAW_WRITEL(p->intra_refresh_mb, MFC_REG_E_IR_SIZE); + + mfc_core_set_pixel_format(core, ctx, ctx->src_fmt->fourcc); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_ENC_OPTIONS); + /* frame skip mode */ + mfc_clear_set_bits(reg, 0x3, 0, p->frame_skip_mode); + /* seq header ctrl */ + mfc_clear_set_bits(reg, 0x1, 2, p->seq_hdr_mode); + /* cyclic intra refresh */ + mfc_clear_bits(reg, 0x1, 4); + if (p->intra_refresh_mb) + mfc_set_bits(reg, 0x1, 4, 0x1); + /* disable seq header generation if OTF mode */ + mfc_clear_bits(reg, 0x1, 6); + + /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ + mfc_clear_bits(reg, 0x1, 9); + + /* Predict motion search mode */ + mfc_clear_set_bits(reg, 0x3, 22, p->mv_search_mode); + + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_ENC_OPTIONS); + + if (p->mv_hor_range) { + reg = MFC_CORE_RAW_READL(MFC_REG_E_MV_HOR_RANGE); + mfc_clear_set_bits(reg, 0x3fff, 0, p->mv_hor_range); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_MV_HOR_RANGE); + } + if (p->mv_ver_range) { + reg = MFC_CORE_RAW_READL(MFC_REG_E_MV_VER_RANGE); + mfc_clear_set_bits(reg, 0x3fff, 0, p->mv_ver_range); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_MV_VER_RANGE); + } + + if (p->mv_search_mode == 2) { + reg = MFC_CORE_RAW_READL(MFC_REG_E_MV_HOR_RANGE); + mfc_clear_set_bits(reg, 0xff, 16, p->mv_hor_pos_l0); + mfc_clear_set_bits(reg, 0xff, 24, p->mv_hor_pos_l1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_MV_HOR_RANGE); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_MV_VER_RANGE); + mfc_clear_set_bits(reg, 0xff, 16, p->mv_ver_pos_l0); + mfc_clear_set_bits(reg, 0xff, 24, p->mv_ver_pos_l1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_MV_VER_RANGE); + mfc_ctx_debug(2, "MV search mode(%d), HOR (L0: %d, L1: %d), VER (L0: %d, L1: %d)\n", + p->mv_search_mode, + p->mv_hor_pos_l0, p->mv_hor_pos_l1, + p->mv_ver_pos_l0, p->mv_ver_pos_l1); + } + + if (ctx->src_fmt->type & MFC_FMT_RGB) { + reg = MFC_CORE_RAW_READL(MFC_REG_PIXEL_FORMAT); + mfc_clear_set_bits(reg, 0x1, 8, p->color_range); + mfc_clear_set_bits(reg, 0x3, 6, __mfc_get_rgb_format_ctrl(ctx, p)); + mfc_ctx_debug(2, "[RGB] enc color_range %d, primaries %d, transfer %d\n", + p->color_range, p->colour_primaries, + p->transfer_characteristics); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_PIXEL_FORMAT); + } + + /* padding control & value */ + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_PADDING_CTRL); + if (p->pad) { + reg = 0; + /** enable */ + mfc_set_bits(reg, 0x1, 31, 0x1); + /** cr value */ + mfc_set_bits(reg, 0xFF, 16, p->pad_cr); + /** cb value */ + mfc_set_bits(reg, 0xFF, 8, p->pad_cb); + /** y value */ + mfc_set_bits(reg, 0xFF, 0, p->pad_luma); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PADDING_CTRL); + } + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /* macroblock level rate control */ + mfc_clear_set_bits(reg, 0x1, 8, p->rc_mb); + /* frame-level rate control */ + mfc_clear_set_bits(reg, 0x1, 9, p->rc_frame); + /* drop control */ + mfc_clear_set_bits(reg, 0x1, 10, p->drop_control); + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->enc_ts_delta)) + mfc_clear_set_bits(reg, 0x1, 20, 1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* + * Delta value for framerate is timestamp(ms * 10) diff. + * ex) 30fps: 333, 60fps: 166 + * Resolution unit is most sophisticated value + * that can be determined within 16bit. + * F/W calculates fps through resolution / delta. + * ex) 10000 / 166 = 60fps + */ + p->rc_frame_delta = p->rc_framerate_res / p->rc_framerate; + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_FRAME_RATE); + mfc_clear_set_bits(reg, 0xFFFF, 16, p->rc_framerate_res); + mfc_clear_set_bits(reg, 0xFFFF, 0, p->rc_frame_delta); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); + + /* bit rate */ + ctx->kbps = p->rc_bitrate / SZ_1K; + MFC_CORE_RAW_WRITEL(p->rc_bitrate, MFC_REG_E_RC_BIT_RATE); + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->max_i_frame_size)) { + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_OPTIONS); + mfc_clear_set_bits(reg, 0xFFFF, 0, p->max_i_frame_size); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_OPTIONS); + } + + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_MODE); + mfc_clear_bits(reg, 0x7, 0); + mfc_clear_bits(reg, 0x3, 4); + mfc_clear_bits(reg, 0xFF, 8); + if (p->rc_frame) { + if (p->rc_reaction_coeff <= CBR_I_LIMIT_MAX) { + mfc_set_bits(reg, 0x7, 0, MFC_REG_E_RC_CBR_I_LIMIT_VT); + /* + * Ratio of intra for max frame size + * is controlled when only CBR_I_LIMIT_VT mode. + * And CBR_I_LIMIT_VT mode is valid for H.264, HEVC codec + */ + if (p->ratio_intra) + mfc_set_bits(reg, 0xFF, 8, p->ratio_intra); + } else if (p->rc_reaction_coeff <= CBR_FIX_MAX) { + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->wfd_rc_mode) && + p->rc_reaction_coeff <= CBR_I_LIMIT_WFD) { + mfc_set_bits(reg, 0x7, 0, MFC_REG_E_RC_CBR_I_LIMIT_WFD); + } else { + mfc_set_bits(reg, 0x7, 0, MFC_REG_E_RC_CBR_FIX); + } + } else { + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->wfd_rc_mode) && + p->rc_reaction_coeff <= VBR_BIT_SAVE) { + mfc_set_bits(reg, 0x7, 0, MFC_REG_E_RC_VBR_BS); + } else { + mfc_set_bits(reg, 0x7, 0, MFC_REG_E_RC_VBR); + } + } + + if (p->rc_mb) + mfc_set_bits(reg, 0x3, 4, p->rc_pvc); + } + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->min_quality_mode) && p->min_quality_mode) { + mfc_set_bits(reg, 0x1, 7, p->min_quality_mode); + mfc_ctx_debug(2, "MIN quality mode is enabled\n"); + } + + mfc_ctx_debug(3, "RC_MODE) rc coeff: %d, wfd_rc_mode: %d, rc_mode: %#x, max I size: %d\n", + p->rc_reaction_coeff, + MFC_FEATURE_SUPPORT(dev, dev->pdata->wfd_rc_mode), + reg, p->max_i_frame_size); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_MODE); + + /* high quality mode */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_HIGH_QUALITY_MODE); + if (p->wp_two_pass_enable) { + mfc_clear_set_bits(reg, 0x1, 0, p->wp_two_pass_enable); + mfc_ctx_debug(2, "WP two pass encoding is enabled\n"); + } + if (p->adaptive_gop_enable) { + mfc_clear_set_bits(reg, 0x1, 4, p->adaptive_gop_enable); + mfc_ctx_debug(2, "Adaptive gop is enabled\n"); + } + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HIGH_QUALITY_MODE); + + /* extended encoder ctrl */ + /** vbv buffer size */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_VBV_BUFFER_SIZE); + mfc_clear_bits(reg, 0xFF, 0); + if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) + mfc_set_bits(reg, 0xFF, 0, p->vbv_buf_size); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VBV_BUFFER_SIZE); + + /* Video signal type */ + __mfc_set_video_signal_type(core, ctx); + + /* Check performance decrease options */ + if (!fps) + fps = p->rc_framerate; + if (IS_MFC_MAX_PERF(ctx, fps)) { + if (mfc_is_enc_bframe(ctx)) { + p->num_b_frame = 0; + if (IS_H264_ENC(ctx)) + p->codec.h264.hier_qp_type = + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P; + mfc_ctx_info("forcely can't be use B frame for 8K or 4K %d fps\n", fps); + } + if (p->num_refs_for_p > 1) { + p->num_refs_for_p = 1; + mfc_ctx_info("forcely use 1-ref frame for 8K or 4K %d fps\n", fps); + } + } + + mfc_ctx_debug_leave(); +} + +static void __mfc_set_temporal_svc_h264(struct mfc_core *core, + struct mfc_ctx *ctx, + struct mfc_h264_enc_params *p_264) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0, reg2 = 0; + int i; + + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_OPTIONS_2); + /* pic_order_cnt_type = 0 for backward compatibilities */ + mfc_clear_bits(reg, 0x3, 0); + /* Enable LTR */ + mfc_clear_bits(reg, 0x1, 2); + if ((p_264->enable_ltr & 0x1) || p_264->num_of_ltr > 0) + mfc_set_bits(reg, 0x1, 2, 0x1); + /* Number of LTR */ + mfc_clear_bits(reg, 0x3, 7); + if (p_264->num_of_ltr > 2) + mfc_set_bits(reg, 0x3, 7, (p_264->num_of_ltr - 2)); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_OPTIONS_2); + + /* Temporal SVC - qp type, layer number */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_NUM_T_LAYER); + mfc_clear_set_bits(reg, 0x1, 3, p_264->hier_qp_type); + mfc_clear_set_bits(reg, 0x7, 0, p_264->num_hier_layer); + mfc_clear_bits(reg, 0x7, 4); + if (p_264->hier_ref_type) { + mfc_set_bits(reg, 0x1, 7, 0x1); + mfc_set_bits(reg, 0x7, 4, p->num_hier_max_layer); + } else { + mfc_clear_bits(reg, 0x1, 7); + mfc_set_bits(reg, 0x7, 4, p_264->num_hier_layer); + } + mfc_clear_set_bits(reg, 0x1, 8, p->hier_bitrate_ctrl); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); + mfc_ctx_debug(3, "[HIERARCHICAL] hier_qp_enable %d, enable_ltr %d", + p_264->hier_qp_enable, p_264->enable_ltr); + mfc_ctx_debug(3, "num_hier_layer %d, max_layer %d, hier_ref_type %d, NUM_T_LAYER 0x%x\n", + p_264->num_hier_layer, p->num_hier_max_layer, p_264->hier_ref_type, reg); + + /* QP & Bitrate for each layer */ + for (i = 0; i < 7; i++) { + MFC_CORE_RAW_WRITEL + (p_264->hier_qp_layer[i], + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); + /* If hier_bitrate_ctrl is set to 1, this is meaningless */ + MFC_CORE_RAW_WRITEL + (p_264->hier_bit_layer[i], + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + mfc_ctx_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %d(FW ctrl: %d)\n", + i, p_264->hier_qp_layer[i], + p_264->hier_bit_layer[i], p->hier_bitrate_ctrl); + } + if (p_264->set_priority) { + reg = 0; + reg2 = 0; + for (i = 0; i < (p_264->num_hier_layer & 0x7); i++) { + if (i <= 4) + mfc_set_bits(reg, 0x3F, (6 * i), (p_264->base_priority + i)); + else + mfc_set_bits(reg2, 0x3F, (6 * (i - 5)), (p_264->base_priority + i)); + } + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_CORE_RAW_WRITEL(reg2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); + mfc_ctx_debug(3, "[HIERARCHICAL] priority EXTENSION0: %#x, EXTENSION1: %#x\n", + reg, reg2); + } +} + +static void __mfc_set_fmo_slice_map_h264(struct mfc_core *core, + struct mfc_ctx *ctx, + struct mfc_h264_enc_params *p_264) +{ + int i; + + if (p_264->fmo_enable) { + switch (p_264->fmo_slice_map_type) { + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES: + if (p_264->fmo_slice_num_grp > 4) + p_264->fmo_slice_num_grp = 4; + for (i = 0; i < (p_264->fmo_slice_num_grp & 0xF); i++) + MFC_CORE_RAW_WRITEL + (p_264->fmo_run_length[i] - 1, + MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_0 + i * 4); + break; + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: + if (p_264->fmo_slice_num_grp > 4) + p_264->fmo_slice_num_grp = 4; + break; + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN: + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: + if (p_264->fmo_slice_num_grp > 2) + p_264->fmo_slice_num_grp = 2; + MFC_CORE_RAW_WRITEL + (p_264->fmo_sg_dir & 0x1, MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_DIR); + /* the valid range is 0 ~ number of macroblocks -1 */ + MFC_CORE_RAW_WRITEL(p_264->fmo_sg_rate, + MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1); + break; + default: + mfc_ctx_err("Unsupported map type for FMO: %d\n", + p_264->fmo_slice_map_type); + p_264->fmo_slice_map_type = 0; + p_264->fmo_slice_num_grp = 1; + break; + } + + MFC_CORE_RAW_WRITEL + (p_264->fmo_slice_map_type, MFC_REG_E_H264_FMO_SLICE_GRP_MAP_TYPE); + MFC_CORE_RAW_WRITEL + (p_264->fmo_slice_num_grp - 1, MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1); + } else { + MFC_CORE_RAW_WRITEL(0, MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1); + } +} + +static void __mfc_set_enc_params_h264(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_h264_enc_params *p_264 = &p->codec.h264; + unsigned int mb = 0; + unsigned int reg = 0; + + mfc_ctx_debug_enter(); + + p->rc_framerate_res = FRAME_RATE_RESOLUTION; + __mfc_set_enc_params(core, ctx); + + if (p_264->num_hier_layer & 0x7) { + /* set gop_size without i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 0); + } else { + /* set gop_size with i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 1); + } + + mb = WIDTH_MB((ctx)->crop_width) * HEIGHT_MB((ctx)->crop_height); + /* Level 6.0 case */ + if (IS_LV60_MB(mb)) { + if (p_264->level < 60) + mfc_ctx_info("This resolution(mb: %d) recommends level6.0\n", mb); + /* In case of profile is baseline or constrained baseline */ + if (p_264->profile == 0x0 || p_264->profile == 0x3) + mfc_ctx_info("This resolution(mb: %d) recommends high profile\n", mb); + if (!dev->pdata->support_8K_cavlc && p_264->entropy_mode != 0x1) { + mfc_ctx_info("Set Entropy mode CABAC\n"); + p_264->entropy_mode = 1; + } + } + + /* Level 5.1 case */ + if (IS_LV51_MB(mb)) { + if (p_264->level < 51) + mfc_ctx_info("This resolution(mb: %d) recommends level5.1\n", mb); + /* In case of profile is baseline or constrained baseline */ + if (p_264->profile == 0x0 || p_264->profile == 0x3) + mfc_ctx_info("This resolution(mb: %d) recommends high profile\n", mb); + } + + /* profile & level */ + reg = 0; + /** level */ + mfc_clear_set_bits(reg, 0xFF, 8, p_264->level); + /** profile - 0 ~ 3 */ + mfc_clear_set_bits(reg, 0x3F, 0, p_264->profile); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_OPTIONS); + /* entropy coding mode */ + mfc_clear_set_bits(reg, 0x1, 0, p_264->entropy_mode); + /* loop filter ctrl */ + mfc_clear_set_bits(reg, 0x3, 1, p_264->loop_filter_mode); + /* interlace */ + mfc_clear_set_bits(reg, 0x1, 3, p_264->interlace); + /* intra picture period for H.264 open GOP */ + mfc_clear_set_bits(reg, 0x1, 4, p_264->open_gop); + /* extended encoder ctrl */ + mfc_clear_set_bits(reg, 0x1, 5, p_264->ar_vui); + /* ASO enable */ + mfc_clear_set_bits(reg, 0x1, 6, p_264->aso_enable); + /* if num_refs_for_p is 2, the performance falls by half */ + mfc_clear_set_bits(reg, 0x1, 7, (p->num_refs_for_p - 1)); + /* Temporal SVC - hier qp enable */ + mfc_clear_set_bits(reg, 0x1, 8, p_264->hier_qp_enable); + /* Weighted Prediction enable */ + mfc_clear_set_bits(reg, 0x3, 9, p->weighted_enable); + if (p->weighted_enable) + mfc_ctx_debug(2, "WP mode is %d\n", p->weighted_enable); + /* 8x8 transform enable [12]: INTER_8x8_TRANS_ENABLE */ + mfc_clear_set_bits(reg, 0x1, 12, p_264->_8x8_transform); + /* 8x8 transform enable [13]: INTRA_8x8_TRANS_ENABLE */ + mfc_clear_set_bits(reg, 0x1, 13, p_264->_8x8_transform); + /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ + mfc_clear_bits(reg, 0x1, 14); + /* sps pps control */ + mfc_clear_set_bits(reg, 0x1, 29, p_264->prepend_sps_pps_to_idr); + /* VUI parameter disable */ + mfc_clear_set_bits(reg, 0x1, 30, p_264->vui_enable); + /* Timing info */ + mfc_set_bits(reg, 0x1, 31, p->timing_info_enable); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_OPTIONS); + + /* cropped height */ + if (p_264->interlace) + MFC_CORE_RAW_WRITEL(ctx->crop_height >> 1, MFC_REG_E_CROPPED_FRAME_HEIGHT); + + /* loopfilter alpha offset */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_LF_ALPHA_OFFSET); + mfc_clear_set_bits(reg, 0x1F, 0, p_264->loop_filter_alpha); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_LF_ALPHA_OFFSET); + + /* loopfilter beta offset */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_LF_BETA_OFFSET); + mfc_clear_set_bits(reg, 0x1F, 0, p_264->loop_filter_beta); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_LF_BETA_OFFSET); + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_264->rc_frame_qp); + mfc_clear_bits(reg, 0x1, 11); + if (!p->rc_frame && !p->rc_mb && p->dynamic_qp) + mfc_set_bits(reg, 0x1, 11, 0x1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_264->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_264->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 24, p_264->rc_max_qp_b); + /** min B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 16, p_264->rc_min_qp_b); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_264->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_264->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 16, p_264->rc_b_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_264->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_264->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* chroma QP offset */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_CHROMA_QP_OFFSET); + mfc_clear_set_bits(reg, 0x1F, 5, p->chroma_qp_offset_cr); + mfc_clear_set_bits(reg, 0x1F, 0, p->chroma_qp_offset_cb); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_CHROMA_QP_OFFSET); + + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_ASPECT_RATIO); + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_EXTENDED_SAR); + if (p_264->ar_vui) { + /* aspect ration IDC */ + reg = 0; + mfc_set_bits(reg, 0xFF, 0, p_264->ar_vui_idc); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_ASPECT_RATIO); + if (p_264->ar_vui_idc == 0xFF) { + /* sample AR info. */ + reg = 0; + mfc_set_bits(reg, 0xFFFF, 16, p_264->ext_sar_width); + mfc_set_bits(reg, 0xFFFF, 0, p_264->ext_sar_height); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_EXTENDED_SAR); + } + } + /* intra picture period for H.264 open GOP, value */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_REFRESH_PERIOD); + mfc_clear_bits(reg, 0xFFFF, 0); + if (p_264->open_gop) + mfc_set_bits(reg, 0xFFFF, 0, p_264->open_gop_size); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_REFRESH_PERIOD); + + /* Temporal SVC */ + __mfc_set_temporal_svc_h264(core, ctx, p_264); + + /* set frame pack sei generation */ + if (p_264->sei_gen_enable) { + /* frame packing enable */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_H264_OPTIONS); + mfc_set_bits(reg, 0x1, 25, 0x1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_OPTIONS); + + /* set current frame0 flag & arrangement type */ + reg = 0; + /** current frame0 flag */ + mfc_set_bits(reg, 0x1, 2, p_264->sei_fp_curr_frame_0); + /** arrangement type */ + mfc_set_bits(reg, 0x3, 0, (p_264->sei_fp_arrangement_type - 3)); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_FRAME_PACKING_SEI_INFO); + } + + __mfc_set_fmo_slice_map_h264(core, ctx, p_264); + + mfc_ctx_debug_leave(); +} + +int mfc_core_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) +{ + if (IS_H264_ENC(ctx)) { + __mfc_set_enc_params_h264(core, ctx); + } else { + mfc_ctx_err("Unknown codec for encoding (%x)\n", ctx->codec_mode); + return -EINVAL; + } + + mfc_ctx_debug(5, "RC) Bitrate: %d / framerate: %#x / config %#x / mode %#x\n", + MFC_CORE_RAW_READL(MFC_REG_E_RC_BIT_RATE), + MFC_CORE_RAW_READL(MFC_REG_E_RC_FRAME_RATE), + MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG), + MFC_CORE_RAW_READL(MFC_REG_E_RC_MODE)); + + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h new file mode 100644 index 000000000000..ce15ae29abba --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * mfc_enc_param.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_ENC_PARAM_H +#define __MFC_ENC_PARAM_H __FILE__ + +#include "base/mfc_common.h" + +void mfc_core_set_slice_mode(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_set_aso_slice_order_h264(struct mfc_core *core, + struct mfc_ctx *ctx); +void mfc_core_set_enc_config_qp(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_set_enc_ts_delta(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx); +#endif /* __MFC_ENC_PARAM_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c index 8846230f1e20..4580aa3498cc 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c @@ -379,6 +379,768 @@ static struct mfc_ctrl_cfg mfc_dec_ctrl_list[] = { #define NUM_DEC_CTRL_CFGS ARRAY_SIZE(mfc_dec_ctrl_list) +static struct mfc_ctrl_cfg mfc_enc_ctrl_list[] = { + { /* set frame tag */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_PICTURE_TAG, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* get frame tag */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RET_PICTURE_TAG, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* encoded y physical addr */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* encoded c physical addr */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_ENCODED_SOURCE_SECOND_ADDR, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* I, not coded frame insertion */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_FRAME_INSERTION, + .mask = 0x3, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* I period change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_GOP_CONFIG, + .mask = 0xFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 0, + }, + { /* frame rate change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_FRAME_RATE, + .mask = 0x0000FFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 1, + }, + { /* bit rate change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_BIT_RATE, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 2, + }, + { /* frame status (in slice or not) */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS, + .is_volatile = 0, + .mode = MFC_CTRL_MODE_NONE, + .addr = 0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* H.264 I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.263 I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.263 I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP8 I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP8 I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP9 I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP9 I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC I frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC I frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.263 P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.263 P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP8 P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP8 P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP9 P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* VP9 P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC P frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC P frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 B frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 B frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 B frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* MPEG4 B frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC B frame QP Max change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* HEVC B frame QP Min change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_QP_BOUND_PB, + .mask = 0xFF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 4, + }, + { /* H.264 Dynamic Temporal Layer & bitrate change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 10, + }, + { /* HEVC Dynamic Temporal Layer & bitrate change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 10, + }, + { /* VP8 Dynamic Temporal Layer change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 10, + }, + { /* VP9 Dynamic Temporal Layer change */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 10, + }, + { /* set level */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_PICTURE_PROFILE, + .mask = 0x000000FF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 5, + }, + { /* set profile */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_PICTURE_PROFILE, + .mask = 0x0000000F, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 5, + }, + { /* set store LTR */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC_H264_MARK_LTR, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_H264_NAL_CONTROL, + .mask = 0x00000003, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* set use LTR */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC_H264_USE_LTR, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_H264_NAL_CONTROL, + .mask = 0x00000003, + .shft = 2, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* set base layer priority */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_H264_HD_SVC_EXTENSION_0, + .mask = 0x0000003F, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 12, + }, + { /* set QP per each frame */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_MFC_CONFIG_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_FIXED_PICTURE_QP, + .mask = 0x000000FF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* Region-Of-Interest control */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_ROI_CONTROL, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_ROI_CTRL, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* set YSUM for weighted prediction */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_YSUM, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_WEIGHT_FOR_WEIGHTED_PREDICTION, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_shft = 0, + }, + { /* set base layer priority */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_MODE, + .mask = 0x000000FF, + .shft = 8, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 13, + }, + { /* sync the timestamp for drop control */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_DROP_CONTROL, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_FRAME_RATE, + .mask = 0x0000FFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* average QP of current frame */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_AVERAGE_QP, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_NAL_DONE_INFO, + .mask = 0x000000FF, + .shft = 12, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* HOR range position of current frame */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L0, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_MV_HOR_RANGE, + .mask = 0x000000FF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* HOR range position of current frame */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L1, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_MV_HOR_RANGE, + .mask = 0x000000FF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* VER range position of current frame */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L0, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_MV_VER_RANGE, + .mask = 0x000000FF, + .shft = 16, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* VER range position of current frame */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L1, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_MV_VER_RANGE, + .mask = 0x000000FF, + .shft = 24, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* Max I frame size */ + .type = MFC_CTRL_TYPE_SET_SRC, + .id = V4L2_CID_MPEG_VIDEO_MAX_IFRAME_SIZE, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_RC_OPTIONS, + .mask = 0xFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_SFR, + .flag_addr = MFC_REG_E_PARAM_CHANGE, + .flag_shft = 20, + }, + { /* The number of skip MB */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SUM_SKIP_MB, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_SUM_SKIP_MB, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* The number of intra MB */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SUM_INTRA_MB, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_SUM_INTRA_MB, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* The number of intra MB */ + .type = MFC_CTRL_TYPE_GET_DST, + .id = V4L2_CID_MPEG_VIDEO_SUM_ZERO_MV_MB, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_SFR, + .addr = MFC_REG_E_SUM_ZERO_MV_MB, + .mask = 0xFFFFFFFF, + .shft = 0, + .flag_mode = MFC_CTRL_MODE_NONE, + .flag_addr = 0, + .flag_shft = 0, + }, + { /* buffer additional information */ + .type = MFC_CTRL_TYPE_SRC, + .id = V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_NONE, + .flag_mode = MFC_CTRL_MODE_NONE, + }, + { /* buffer additional information */ + .type = MFC_CTRL_TYPE_DST, + .id = V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, + .is_volatile = 1, + .mode = MFC_CTRL_MODE_NONE, + .flag_mode = MFC_CTRL_MODE_NONE, + } +}; + +#define NUM_ENC_CTRL_CFGS ARRAY_SIZE(mfc_enc_ctrl_list) + static void mfc_ctrl_cleanup_ctx(struct mfc_ctx *ctx) { struct mfc_ctx_ctrl *ctx_ctrl; @@ -426,6 +1188,8 @@ static int mfc_ctrl_init_ctx(struct mfc_ctx *ctx) { if (ctx->type == MFCINST_DECODER) return __mfc_ctrl_init_ctx(ctx, mfc_dec_ctrl_list, NUM_DEC_CTRL_CFGS); + else if (ctx->type == MFCINST_ENCODER) + return __mfc_ctrl_init_ctx(ctx, mfc_enc_ctrl_list, NUM_ENC_CTRL_CFGS); mfc_ctx_err("[CTRLS] invalid type %d\n", ctx->type); return -EINVAL; @@ -560,11 +1324,47 @@ static int mfc_ctrl_init_buf(struct mfc_ctx *ctx, enum mfc_ctrl_type type, unsig { if (ctx->type == MFCINST_DECODER) return __mfc_ctrl_init_buf(ctx, mfc_dec_ctrl_list, type, index, NUM_DEC_CTRL_CFGS); + else if (ctx->type == MFCINST_ENCODER) + return __mfc_ctrl_init_buf(ctx, mfc_enc_ctrl_list, type, index, NUM_ENC_CTRL_CFGS); mfc_ctx_err("[CTRLS] invalid type %d\n", ctx->type); return -EINVAL; } +static void __mfc_enc_set_roi(struct mfc_ctx *ctx, struct mfc_buf_ctrl *buf_ctrl) +{ + struct mfc_enc *enc = ctx->enc_priv; + int index = 0; + unsigned int reg = 0; + + index = enc->roi_index; + if (enc->roi_info[index].enable) { + enc->roi_index = (index + 1) % MFC_MAX_EXTRA_BUF; + reg |= enc->roi_info[index].enable; + reg &= ~(0xFF << 8); + reg |= (enc->roi_info[index].lower_qp << 8); + reg &= ~(0xFFFF << 16); + reg |= (enc->roi_info[index].upper_qp << 16); + /* + * 2bit ROI + * - All codec type: upper_qp and lower_qp is valid + * 8bit ROI + * - H.264/HEVC/MPEG4: upper_qp and lower_qp is invalid + * - VP8/VP9: upper_qp and lower_qp is valid + */ + mfc_ctx_debug(3, "[ROI] buffer[%d] en %d QP lower %d upper %d reg %#x\n", + index, enc->roi_info[index].enable, + enc->roi_info[index].lower_qp, + enc->roi_info[index].upper_qp, + reg); + } else { + mfc_ctx_debug(3, "[ROI] buffer[%d] is not enabled\n", index); + } + + buf_ctrl->val = reg; + buf_ctrl->old_val2 = index; +} + static void mfc_ctrl_to_buf(struct mfc_ctx *ctx, struct list_head *head) { struct mfc_ctx_ctrl *ctx_ctrl; @@ -588,6 +1388,9 @@ static void mfc_ctrl_to_buf(struct mfc_ctx *ctx, struct list_head *head) ctx_ctrl->set.has_new = 0; + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_ROI_CONTROL) + __mfc_enc_set_roi(ctx, buf_ctrl); + break; } } diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c index a7db47e58589..4083d76640fd 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.c @@ -685,12 +685,22 @@ static void __mfc_rm_migrate_all_to_one_core(struct mfc_dev *dev) spin_unlock_irqrestore(&dev->ctx_list_lock, flags); return; } - - if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_0) - op_core_fixed0++; - else if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_1) - op_core_fixed1++; - + /* op core type */ + if (tmp_ctx->type == MFCINST_ENCODER) { + /* + * instance of encoder cannot be moved to another core. + * So, treat main core as the fixed core. + */ + if (tmp_ctx->op_core_num[MFC_CORE_MAIN] == MFC_DEC_DEFAULT_CORE) + op_core_fixed0++; + else if (tmp_ctx->op_core_num[MFC_CORE_MAIN] == MFC_SURPLUS_CORE) + op_core_fixed1++; + } else { + if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_0) + op_core_fixed0++; + else if (tmp_ctx->op_core_type == MFC_OP_CORE_FIXED_1) + op_core_fixed1++; + } /* op main core */ if (tmp_ctx->op_core_num[MFC_CORE_MAIN] == MFC_DEC_DEFAULT_CORE) op_core0++; @@ -1344,6 +1354,14 @@ void mfc_rm_load_balancing(struct mfc_ctx *ctx, int load_add) __mfc_rm_update_core_load(tmp_ctx, 0, 1); continue; } + + if (tmp_ctx->type == MFCINST_ENCODER) { + mfc_ctx_debug(3, "[RMLB] encoder ctx[%d] can't be moved\n", + tmp_ctx->num); + __mfc_rm_update_core_load(tmp_ctx, 0, IS_MULTI_MODE(tmp_ctx)); + continue; + } + core_num = __mfc_rm_get_core_num_by_load(dev, tmp_ctx, MFC_DEC_DEFAULT_CORE); if (IS_SWITCH_SINGLE_MODE(tmp_ctx) || core_num == tmp_ctx->op_core_num[MFC_CORE_MAIN]) { @@ -1440,8 +1458,10 @@ int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx) * QoS portion data should be allocated * only once per instance after maincore is determined. */ - num_qos_steps = core->core_pdata->num_default_qos_steps; - + if (ctx->type == MFCINST_ENCODER) + num_qos_steps = core->core_pdata->num_encoder_qos_steps; + else + num_qos_steps = core->core_pdata->num_default_qos_steps; ctx->mfc_qos_portion = vmalloc(sizeof(unsigned int) * num_qos_steps); if (!ctx->mfc_qos_portion) ret = -ENOMEM; @@ -1916,6 +1936,46 @@ void mfc_rm_instance_dec_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, mfc_ctx_debug_leave(); } +void mfc_rm_instance_enc_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, + unsigned int type) +{ + struct mfc_core *core; + struct mfc_core *subcore; + + mfc_ctx_debug_enter(); + + mfc_get_corelock_ctx(ctx); + + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] There is no main core\n"); + mfc_release_corelock_ctx(ctx); + return; + } + + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + core->core_ops->instance_q_flush(core, ctx); + } else if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + if (IS_SWITCH_SINGLE_MODE(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (!subcore) { + mfc_ctx_err("[RM] There is no sub core for switch single\n"); + goto err_subcore_stop; + } + + core->core_ops->instance_finishing(core, ctx); + subcore->core_ops->instance_finishing(subcore, ctx); + } else { + core->core_ops->instance_finishing(core, ctx); + } + } + +err_subcore_stop: + mfc_release_corelock_ctx(ctx); + + mfc_ctx_debug_leave(); +} + int mfc_rm_subcore_seq_start(struct mfc_dev *dev, struct mfc_ctx *ctx) { struct mfc_core *core; @@ -2284,6 +2344,8 @@ void mfc_rm_qos_control(struct mfc_ctx *ctx, enum mfc_qos_control qos_control) mfc_rm_load_balancing(ctx, MFC_RM_LOAD_ADD); ctx->update_bitrate = false; + if (ctx->type == MFCINST_ENCODER) + ctx->update_framerate = false; break; default: mfc_ctx_err("[RM] not supported QoS control type: %#x\n", @@ -2528,9 +2590,14 @@ void mfc_rm_update_real_time(struct mfc_ctx *ctx) } } else { if (new_prio == 0) { - /* In case of google photo app, user sets priority 0 */ - new_prio = 1; - new_rt = MFC_RT_LOW; + if (ctx->type == MFCINST_ENCODER && + ctx->enc_priv->params.rc_framerate) { + new_rt = MFC_RT; + } else { + /* In case of google photo app, user sets priority 0 */ + new_prio = 1; + new_rt = MFC_RT_LOW; + } } else if (new_prio >= 1) { new_rt = MFC_NON_RT; } else { diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h index b73ef905718a..39ec63392db3 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_rm.h @@ -94,6 +94,8 @@ int mfc_rm_instance_deinit(struct mfc_dev *dev, struct mfc_ctx *ctx); int mfc_rm_instance_open(struct mfc_dev *dev, struct mfc_ctx *ctx); void mfc_rm_instance_dec_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, unsigned int type); +void mfc_rm_instance_enc_stop(struct mfc_dev *dev, struct mfc_ctx *ctx, + unsigned int type); int mfc_rm_subcore_seq_start(struct mfc_dev *dev, struct mfc_ctx *ctx); int mfc_rm_instance_setup(struct mfc_dev *dev, struct mfc_ctx *ctx); void mfc_rm_request_work(struct mfc_dev *dev, enum mfc_request_work work, -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035657epcas5p17d3e94c7c1ba5eeace97b0ff81053653@epcas5p1.samsung.com>]
* [PATCH 24/29] media: mfc: Add encoder VB2 support to driver [not found] ` <CGME20250930035657epcas5p17d3e94c7c1ba5eeace97b0ff81053653@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> Introduce encoder VB2 support. This enables proper V4L2 output for the Exynos MFC encoder, handling queue setup, buffers, and streaming control. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../platform/samsung/exynos-mfc/mfc_enc_vb2.c | 443 ++++++++++++++++++ .../platform/samsung/exynos-mfc/mfc_enc_vb2.h | 19 + 3 files changed, 463 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index a257d5b0a576..dad94a7c468c 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_VIDEO_EXYNOS_MFC) := exynos_mfc.o ccflags-y += -I$(srctree)/$(src) #Dev interface layer -exynos_mfc-y += mfc.o mfc_dec_v4l2.o mfc_dec_vb2.o +exynos_mfc-y += mfc.o mfc_dec_v4l2.o mfc_dec_vb2.o mfc_enc_vb2.o #Dev control layer exynos_mfc-y += mfc_rm.o mfc_ctx_ctrl.o mfc_debugfs.o #Core interface layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c new file mode 100644 index 000000000000..7164c334585b --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_enc_vb2.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_rm.h" + +#include "base/mfc_queue.h" +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" +#include "mfc_enc_vb2.h" + +static int mfc_enc_queue_setup(struct vb2_queue *vq, + unsigned int *buf_count, unsigned int *plane_count, + unsigned int psize[], struct device *alloc_devs[]) +{ + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int i; + + mfc_ctx_debug_enter(); + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (core_ctx->state != MFCINST_GOT_INST && + vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_err("invalid state: %d\n", core_ctx->state); + return -EINVAL; + } + if (core_ctx->state >= MFCINST_FINISHING && + vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_err("invalid state: %d\n", core_ctx->state); + return -EINVAL; + } + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_debug(4, "enc dst\n"); + if (ctx->dst_fmt) + *plane_count = ctx->dst_fmt->mem_planes; + else + *plane_count = MFC_ENC_CAP_PLANE_COUNT; + + if (*buf_count < 1) + *buf_count = 1; + if (*buf_count > MFC_MAX_BUFFERS) + *buf_count = MFC_MAX_BUFFERS; + + psize[0] = enc->dst_buf_size; + alloc_devs[0] = dev->device; + /* In case of VP8/VP9 encoder, part of stream buffer should be read */ + vq->dma_dir = DMA_BIDIRECTIONAL; + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "enc src\n"); + + if (ctx->src_fmt) + *plane_count = ctx->num_fd_frame; + else + *plane_count = MFC_ENC_OUT_PLANE_COUNT; + + if (*buf_count < 1) + *buf_count = 1; + if (*buf_count > MFC_MAX_BUFFERS) + *buf_count = MFC_MAX_BUFFERS; + + /* need to use minimum size to prevent qbuf fail */ + if (*plane_count == 1) { + psize[0] = 1; + alloc_devs[0] = dev->device; + } else { + for (i = 0; i < *plane_count; i++) { + psize[i] = 1; + alloc_devs[i] = dev->device; + } + } + } else { + mfc_err("invalid queue type: %d\n", vq->type); + return -EINVAL; + } + + mfc_debug(2, "buf_count: %d, plane_count: %d, type: %#x\n", + *buf_count, *plane_count, vq->type); + for (i = 0; i < *plane_count; i++) + mfc_debug(2, "plane[%d] size: %d\n", i, psize[i]); + + mfc_ctx_debug_leave(); + + return 0; +} + +static void mfc_enc_unlock(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mutex_unlock(&dev->mfc_mutex); +} + +static void mfc_enc_lock(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mutex_lock(&dev->mfc_mutex); +} + +static int mfc_enc_buf_init(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + int ret; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + ret = mfc_check_vb_with_fmt(ctx->dst_fmt, vb); + if (ret < 0) + return ret; + + if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_DST, + vb->index) < 0) + mfc_ctx_err("failed in init_buf_ctrls\n"); + + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + ret = mfc_check_vb_with_fmt(ctx->src_fmt, vb); + if (ret < 0) + return ret; + + if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, + vb->index) < 0) + mfc_ctx_err("failed in init_buf_ctrls\n"); + } else { + mfc_ctx_err("invalid queue type: %d\n", vq->type); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_enc_buf_prepare(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_raw_info *raw; + unsigned int index = vb->index; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + struct dma_buf *bufcon_dmabuf[MFC_MAX_PLANES]; + int i, mem_get_count = 0; + size_t buf_size; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + buf_size = vb2_plane_size(vb, 0); + mfc_ctx_debug(2, "[STREAM] vb size: %lu, calc size: %u\n", + buf_size, enc->dst_buf_size); + + if (buf_size < enc->dst_buf_size) { + mfc_ctx_err("[STREAM] size(%lu) is smaller than (%d)\n", + buf_size, enc->dst_buf_size); + return -EINVAL; + } + + buf->addr[0][0] = mfc_mem_get_daddr_vb(vb, 0); + + /* Copy dst buffer flag to buf_ctrl */ + buf->flag = call_cop(ctx, get_buf_ctrl_val, ctx, + &ctx->dst_ctrls[index], + V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + raw = &ctx->raw_buf; + if (ctx->src_fmt->mem_planes == 1) { + buf_size = vb2_plane_size(vb, 0); + mfc_ctx_debug(2, "[FRAME] single plane vb size: %lu, calc size: %d\n", + buf_size, raw->total_plane_size); + if (buf_size < raw->total_plane_size) { + mfc_ctx_err("[FRAME] single plane size(%lu) is smaller than (%d)\n", + buf_size, raw->total_plane_size); + return -EINVAL; + } + } else { + for (i = 0; i < ctx->src_fmt->mem_planes; i++) { + buf_size = vb2_plane_size(vb, i); + mfc_ctx_debug(2, "[FRAME] plane[%d] vb size: %lu, calc size: %d\n", + i, buf_size, raw->plane_size[i]); + if (buf_size < raw->plane_size[i]) { + mfc_ctx_err("[FRAME] plane[%d] size(%lu) is smaller than (%d)\n", + i, buf_size, raw->plane_size[i]); + return -EINVAL; + } + } + } + + for (i = 0; i < ctx->src_fmt->mem_planes; i++) { + bufcon_dmabuf[i] = dma_buf_get(vb->planes[i].m.fd); + if (IS_ERR(bufcon_dmabuf[i])) { + mfc_ctx_err("failed to get bufcon dmabuf\n"); + goto err_mem_put; + } + mem_get_count++; + + dma_buf_put(bufcon_dmabuf[i]); + mfc_calc_base_addr(ctx, vb, ctx->src_fmt); + } + + call_cop(ctx, to_buf_ctrls, ctx, &ctx->src_ctrls[index]); + + /* Copy src buffer flag to buf_ctrl */ + buf->flag = call_cop(ctx, get_buf_ctrl_val, ctx, + &ctx->src_ctrls[index], + V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG); + } else { + mfc_ctx_err("invalid queue type: %d\n", vq->type); + return -EINVAL; + } + + mfc_mem_buf_prepare(vb, 0); + + mfc_ctx_debug_leave(); + return 0; + +err_mem_put: + for (i = 0; i < mem_get_count; i++) + dma_buf_put(bufcon_dmabuf[i]); + + return -ENOMEM; +} + +static void mfc_enc_buf_finish(struct vb2_buffer *vb) +{ + struct mfc_buf *buf = vb_to_mfc_buf(vb); + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + unsigned int index = vb->index; + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + /* Copy to dst buffer flag */ + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, buf->flag); + mfc_ctx_debug(4, "[FLAG] dst update buf[%d] flag = %#x\n", + index, buf->flag); + + call_cop(ctx, to_ctx_ctrls, ctx, &ctx->dst_ctrls[index]); + + mfc_mem_buf_finish(vb, 1); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + /* Copy to src buffer flag */ + call_cop(ctx, update_buf_val, ctx, &ctx->src_ctrls[index], + V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, buf->flag); + mfc_ctx_debug(4, "[FLAG] src update buf[%d] flag = %#x\n", + index, buf->flag); + + call_cop(ctx, to_ctx_ctrls, ctx, &ctx->src_ctrls[index]); + } +} + +static void mfc_enc_buf_cleanup(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_ctx *ctx = vq->drv_priv; + unsigned int index = vb->index; + + mfc_ctx_debug_enter(); + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + if (call_cop(ctx, cleanup_buf_ctrls, ctx, + MFC_CTRL_TYPE_DST, index) < 0) + mfc_ctx_err("failed in cleanup_buf_ctrls\n"); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + if (call_cop(ctx, cleanup_buf_ctrls, ctx, + MFC_CTRL_TYPE_SRC, index) < 0) + mfc_ctx_err("failed in cleanup_buf_ctrls\n"); + } else { + mfc_ctx_err("unknown queue type\n"); + } + + mfc_ctx_debug_leave(); +} + +static int mfc_enc_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && + core_ctx->state == MFCINST_FINISHED) { + mfc_change_state(core_ctx, MFCINST_GOT_INST); + mfc_info("enc start_streaming changes state %d\n", + core_ctx->state); + MFC_TRACE_CTX("** ENC streamon, state: %d\n", + core_ctx->state); + } + + mfc_rm_update_real_time(ctx); + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + + return 0; +} + +static void mfc_enc_stop_streaming(struct vb2_queue *q) +{ + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; + + mfc_ctx_info("enc stop_streaming is called, type : %d\n", q->type); + MFC_TRACE_CTX("** ENC streamoff(type:%d)\n", q->type); + + mfc_rm_instance_enc_stop(dev, ctx, q->type); +} + +static void mfc_enc_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *buf = vb_to_mfc_buf(vb); + int i; + int is_dst_buf_ready; + + mfc_ctx_debug_enter(); + + buf->next_index = 0; + buf->done_index = 0; + + if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(2, "[BUFINFO] ctx[%d] add dst index: %d, addr: 0x%08llx\n", + ctx->num, vb->index, buf->addr[0][0]); + + /* Mark destination as available for use by MFC */ + mfc_add_tail_buf(ctx, &ctx->dst_buf_queue, buf); + mfc_rm_qos_control(ctx, MFC_QOS_TRIGGER); + } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + buf->src_index = ctx->serial_src_index++; + if (ctx->multi_view_enable) { + for (i = 0; i < ctx->raw_buf.num_planes; i++) + mfc_ctx_debug(2, "%s[%d] %s: %d(%d), addr[0][%d]: 0x%08llx\n", + "[BUFINFO-view0] ctx", ctx->num, + "add src index", vb->index, + buf->src_index, i, + buf->addr[0][i]); + for (i = 0; i < ctx->raw_buf.num_planes; i++) + mfc_ctx_debug(2, "%s[%d] %s: %d(%d), addr[2][%d]: 0x%08llx\n", + "[BUFINFO-view1] ctx", ctx->num, + "add src index", vb->index, + buf->src_index, i, + buf->addr[2][i]); + } else { + if (ctx->num_fd_frame > 3) { + mfc_ctx_err("if not multi_view_enable, num_fd_frame must be <= 3\n"); + } else { + for (i = 0; i < ctx->num_fd_frame; i++) { + mfc_ctx_debug(2, "%s[%d] %s: %d(%d), addr[%d]: 0x%08llx\n", + "[BUFINFO] ctx", ctx->num, + "add src index", vb->index, + buf->src_index, i, buf->addr[0][i]); + } + } + } + mfc_add_tail_buf(ctx, &ctx->src_buf_ready_queue, buf); + + if (dev->debugfs.debug_ts == 1) + mfc_ctx_info("[TS] framerate: %ld, timestamp: %lld\n", + ctx->framerate, buf->vb.vb2_buf.timestamp); + + mfc_rate_update_last_framerate(ctx, buf->vb.vb2_buf.timestamp); + mfc_rm_qos_control(ctx, MFC_QOS_TRIGGER); + } else { + mfc_ctx_err("unsupported buffer type (%d)\n", vq->type); + } + + if (ctx->stream_op_mode == MFC_OP_TWO_MODE1) + is_dst_buf_ready = + mfc_is_queue_count_greater(&ctx->buf_queue_lock, + &ctx->dst_buf_queue, 0); + + mfc_rm_request_work(dev, MFC_WORK_TRY, ctx); + + if (!mfc_rm_query_state(ctx, EQUAL_BIGGER, MFCINST_HEAD_PARSED) && + ctx->stream_op_mode == MFC_OP_TWO_MODE1 && is_dst_buf_ready) { + core = mfc_get_main_core(dev, ctx); + if (!core) { + mfc_ctx_err("[RM] main core is NULL\n"); + return; + } + core_ctx = core->core_ctx[ctx->num]; + + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + mfc_ctx_err("[RM] sub core header parsing failed\n"); + return; + } + + mfc_ctx_info("[2CORE] start the sub core\n"); + if (ctx->op_core_num[MFC_CORE_SUB] == MFC_CORE_INVALID) { + if (mfc_rm_instance_setup(dev, ctx)) + mfc_ctx_err("[2CORE] failed to setup sub core\n"); + } else { + if (mfc_rm_subcore_seq_start(dev, ctx)) + mfc_ctx_err("[2CORE] failed to seq_start sub core\n"); + } + } + + mfc_ctx_debug_leave(); +} + +static const struct vb2_ops mfc_enc_qops = { + .queue_setup = mfc_enc_queue_setup, + .wait_prepare = mfc_enc_unlock, + .wait_finish = mfc_enc_lock, + .buf_init = mfc_enc_buf_init, + .buf_prepare = mfc_enc_buf_prepare, + .buf_finish = mfc_enc_buf_finish, + .buf_cleanup = mfc_enc_buf_cleanup, + .start_streaming = mfc_enc_start_streaming, + .stop_streaming = mfc_enc_stop_streaming, + .buf_queue = mfc_enc_buf_queue, +}; + +const struct vb2_ops *mfc_get_enc_vb2_ops(void) +{ + return &mfc_enc_qops; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h new file mode 100644 index 000000000000..d3cb99f0bf84 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_enc_vb2.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_ENC_VB2_H +#define __MFC_ENC_VB2_H __FILE__ + +#include "base/mfc_common.h" + +const struct vb2_ops *mfc_get_enc_vb2_ops(void); + +#endif /* __MFC_ENC_VB2_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035700epcas5p1860af28e8a9e99d32b94fa1e97ab5456@epcas5p1.samsung.com>]
* [PATCH 25/29] media: mfc: Add encoder v4l2 driver interface [not found] ` <CGME20250930035700epcas5p1860af28e8a9e99d32b94fa1e97ab5456@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Add encoder V4L2 ioctls, format handling, control operations, buffer management, and driver initialization. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../platform/samsung/exynos-mfc/Makefile | 2 +- .../samsung/exynos-mfc/mfc_enc_v4l2.c | 4179 +++++++++++++++++ .../samsung/exynos-mfc/mfc_enc_v4l2.h | 20 + 3 files changed, 4200 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h diff --git a/drivers/media/platform/samsung/exynos-mfc/Makefile b/drivers/media/platform/samsung/exynos-mfc/Makefile index dad94a7c468c..96d70f9b790d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/Makefile +++ b/drivers/media/platform/samsung/exynos-mfc/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_VIDEO_EXYNOS_MFC) := exynos_mfc.o ccflags-y += -I$(srctree)/$(src) #Dev interface layer -exynos_mfc-y += mfc.o mfc_dec_v4l2.o mfc_dec_vb2.o mfc_enc_vb2.o +exynos_mfc-y += mfc.o mfc_dec_v4l2.o mfc_dec_vb2.o mfc_enc_v4l2.o mfc_enc_vb2.o #Dev control layer exynos_mfc-y += mfc_rm.o mfc_ctx_ctrl.o mfc_debugfs.o #Core interface layer diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c new file mode 100644 index 000000000000..84edebac82b2 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c @@ -0,0 +1,4179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_enc_v4l2.c file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#include "mfc_enc_v4l2.h" +#include "mfc_enc_vb2.h" +#include "mfc_rm.h" + +#include "base/mfc_queue.h" +#include "base/mfc_utils.h" +#include "base/mfc_buf.h" +#include "base/mfc_mem.h" +static struct v4l2_queryctrl enc_controls[] = { + { + .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The period of intra frame", + .minimum = 0, + .maximum = BIT(30) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The slice partitioning method", + .minimum = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + .maximum = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of MB in a slice", + .minimum = 1, + .maximum = INT_MAX, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The maximum bits per slices", + .minimum = 350, + .maximum = INT_MAX / 8, + .step = 1, + .default_value = 350, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB_ROW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of MB row in a slice", + .minimum = 1, + .maximum = INT_MAX / SZ_256, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of intra refresh MBs", + .minimum = 0, + .maximum = BIT(18) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Padding control enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Padding Color YUV Value", + .minimum = 0, + .maximum = BIT(24) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Frame level rate control enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_BITRATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Target bit rate rate-control", + .minimum = 1, + .maximum = INT_MAX, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Rate control reaction coeff.", + .minimum = 1, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_STREAM_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Encoded stream size", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_COUNT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Encoded frame count", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Encoded frame type", + .minimum = 0, + .maximum = 5, + .step = 1, + .default_value = 0, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Force frame type", + .minimum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED, + .maximum = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED, + .step = 1, + .default_value = V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VBV_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VBV buffer size (1Kbits)", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEADER_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Sequence header mode", + .minimum = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .maximum = V4L2_MPEG_VIDEO_HEADER_MODE_AT_THE_READY, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame skip enable", + .minimum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED, + .maximum = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step = 1, + .default_value = V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Fixed target bit enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of B frames", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 profile", + .minimum = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .maximum = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 level", + .minimum = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .maximum = V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 interlace mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 loop filter mode", + .minimum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + .maximum = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_S_B, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 loop filter alpha offset", + .minimum = -12, + .maximum = 12, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 loop filter beta offset", + .minimum = -12, + .maximum = 12, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 entorpy mode", + .minimum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .maximum = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of ref. picture of P", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 8x8 transform enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "MB level rate control", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Frame rate", + .minimum = 1, + .maximum = FRAME_RATE_RESOLUTION, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Frame QP value", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 dark region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 smooth region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 static region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "H264 MB activity adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 P frame QP value", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 B frame QP value", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Aspect ratio VUI enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VUI aspect ratio IDC", + .minimum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED, + .maximum = V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Horizontal size of SAR", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Vertical size of SAR", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "GOP closure", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 I period", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Hierarchical Coding", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Type", + .minimum = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B, + .maximum = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer QP", + .minimum = 0, + .maximum = ((6 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "frame pack sei generation flag", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Current frame is frame 0 flag", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame packing arrangement type", + .minimum = V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE, + .maximum = V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flexible Macroblock Order", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Map type for FMO", + .minimum = V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES, + .maximum = V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Number of slice groups for FMO", + .minimum = 1, + .maximum = 4, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "FMO Run Length", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Direction of the slice group", + .minimum = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT, + .maximum = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Size of the first slice group", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_ASO, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Arbitrary Slice Order", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "ASO Slice order", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_PREPEND_SPSPPS_TO_IDR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Prepend SPS/PPS to every IDR", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 profile", + .minimum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE, + .maximum = V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 level", + .minimum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0, + .maximum = V4L2_MPEG_VIDEO_MPEG4_LEVEL_6, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_MPEG4_LEVEL_0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Frame QP value", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_QPEL, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Quarter pixel search enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 P frame QP value", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 B frame QP value", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_TIME_RES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 vop time resolution", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_FRM_DELTA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 frame delta", + .minimum = 1, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_H263_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Frame rate", + .minimum = 1, + .maximum = BIT(8) - 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Frame QP value", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 P frame QP value", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame Tag", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frame Status", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_QOS_RATIO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "QoS ratio value", + .minimum = 20, + .maximum = INT_MAX, + .step = 1, + .default_value = 100, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_VERSION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 version", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Frame QP value", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Frame QP value", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Frame rate", + .minimum = 1, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_OF_PARTITIONS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 number of partitions", + .minimum = 0, + .maximum = 8, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_LEVEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 loop filter level", + .minimum = 0, + .maximum = 63, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_SHARPNESS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 loop filter sharpness", + .minimum = 0, + .maximum = 7, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_GOLDEN_FRAMESEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 indication of golden frame", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_GF_REFRESH_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 indication of golden frame", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP8 hierarchy QP enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 layer0 QP value", + .minimum = 0, + .maximum = ((2 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 layer1 QP value", + .minimum = 0, + .maximum = ((2 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 layer2 QP value", + .minimum = 0, + .maximum = ((2 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_REF_NUMBER_FOR_PFRAMES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Number of reference picture", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_DISABLE_INTRA_MD4X4, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP8 intra 4x4 mode disable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_TEMPORAL_LAYER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP8 number of hierarchical layer", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_VERSION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 version", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 profile", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 level", + .minimum = 10, + .maximum = 62, + .step = 1, + .default_value = 10, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Frame QP value", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Frame QP value", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Frame rate", + .minimum = 1, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_GOLDEN_FRAMESEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 indication of golden frame", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_GF_REFRESH_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 indication of golden frame", + .minimum = 0, + .maximum = (BIT(16) - 1), + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHY_QP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP9 hierarchy QP enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 layer0 QP value", + .minimum = 0, + .maximum = ((2 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_REF_NUMBER_FOR_PFRAMES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Number of reference picture", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP9 number of hierarchical layer", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_PARTITION_DEPTH, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP9 Maximum coding unit depth", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_DISABLE_INTRA_PU_SPLIT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "VP9 disable intra pu split", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit0", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit1", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit2", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Change", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DISABLE_IVF_HEADER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "IVF header generation", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Frame QP value", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC P frame QP value", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC B frame QP value", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_DARK, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC dark region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC smooth region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_STATIC, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC static region adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC activity adaptive", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Profile", + .minimum = 0, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC level", + .minimum = 10, + .maximum = 62, + .step = 1, + .default_value = 10, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TIER_FLAG, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC tier_flag default is Main", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Frame rate", + .minimum = 1, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_PARTITION_DEPTH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Maximum coding unit depth", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 2, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Number of reference picture", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Number of reference picture", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC refresh type", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LOSSLESS_CU_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC lossless encoding select", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WAVEFRONT_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Wavefront enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_DISABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Filter disable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_SLICE_BOUNDARY, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "across or not slice boundary", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LTR_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "long term reference enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "QP values for temporal layer", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Hierarchical Coding Type", + .minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B, + .maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer", + .minimum = 0, + .maximum = 7, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer QP", + .minimum = 0, + .maximum = ((6 << 16) | 0xFFFF), /* (index << 16) | value */ + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT0", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT1", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT2", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT3", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT4", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT5", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer BIT6", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Change", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIGN_DATA_HIDING, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Sign data hiding", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_GENERAL_PB_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC General pb enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TEMPORAL_ID_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Temporal id enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STRONG_SMOTHING_FLAG, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC Strong intra smoothing flag", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC disable intra pu split", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_TMV_PREDICTION, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "HEVC disable tmv prediction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "max number of candidate MVs", + .minimum = 0, + .maximum = 4, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "ENC without startcode enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Number of reference picture", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC loop filter beta offset", + .minimum = -6, + .maximum = 6, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_TC_OFFSET_DIV2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC loop filter tc offset", + .minimum = -6, + .maximum = 6, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC size of length field", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_USER_REF, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "user long term reference frame", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STORE_REF, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "store long term reference frame", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, /* need to check default value */ + }, + { + .id = V4L2_CID_MPEG_MFC_GET_VERSION_INFO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Get MFC version information", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_GET_EXTRA_BUFFER_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Get extra buffer size", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_GET_EXT_INFO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Get extra information", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit0", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit1", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit2", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT3, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit3", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT4, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit4", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT5, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit5", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT6, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit6", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Change", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit0", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit1", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Bit2", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding Layer Change", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_ENABLE_LTR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Enable LTR", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_NUM_OF_LTR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Number of LTR", + .minimum = 0, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_MARK_LTR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Set the frame as a LTRP", + .minimum = 0, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_USE_LTR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Specify a LTRP for encoding", + .minimum = 0, + .maximum = 0xF, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Base Layer Priority", + .minimum = 0, + .maximum = 63, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_CONFIG_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "QP control per each frame", + .minimum = -12, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_H264_VUI_RESTRICTION_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 vui generation enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Prepend SPS/PPS to every IDR", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_CONFIG_QP_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "set dynamic qp controls", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_ROI_CONTROL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Region-Of-Interest control", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_ROI_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Region-Of-Interest enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Min QP value for I frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Max QP value for I frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Min QP value for I frame", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Max QP value for I frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Min QP value for I frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Max QP value for I frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Min QP value for I frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Max QP value for I frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Min QP value for I frame", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Max QP value for I frame", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Min QP value for I frame", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Max QP value for I frame", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Min QP value for P frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Max QP value for P frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Min QP value for P frame", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Max QP value for P frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Min QP value for P frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Max QP value for P frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Min QP value for P frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H263 Max QP value for P frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Min QP value for P frame", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP8 Max QP value for P frame", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Min QP value for P frame", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "VP9 Max QP value for P frame", + .minimum = 1, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Min QP value for B frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "H264 Max QP value for B frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Min QP value for B frame", + .minimum = -12, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "HEVC Max QP value for B frame", + .minimum = 0, + .maximum = 51, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Min QP value for B frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MPEG4 Max QP value for B frame", + .minimum = 1, + .maximum = 31, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_RC_PVC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Perceptual Video Coding enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_SHORTTERM_MAX_LAYER, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Hierarchical Coding max layer", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_WEIGHTED_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Weighted Prediction enable", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_YSUM, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "YSUM for weighted Prediction", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "ratio of intra encoded size", + .minimum = 15, + .maximum = 50, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Color range", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Colour primaries", + .minimum = 0, + .maximum = 22, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_TRANSFER_CHARACTERISTICS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Transfer characteristics", + .minimum = 0, + .maximum = 18, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MATRIX_COEFFICIENTS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Matrix coefficients", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_HIERARCHICAL_BITRATE_CTRL, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Hierarchical bitrate control", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_MPEG_VIDEO_STATIC_INFO_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Static info enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_PIC_AVERAGE_LIGHT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Max pic average light", + .minimum = 0, + .maximum = 0xFFFF, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_CONTENT_LIGHT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Max content light", + .minimum = 0, + .maximum = 0xFFFF, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_DISPLAY_LUMINANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Max display luminance", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_MIN_DISPLAY_LUMINANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Min display luminance", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_WHITE_POINT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "White point", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Display primaries 0", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Display primaries 1", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_2, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Display primaries 2", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_HDR_USER_SHARED_HANDLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Dynamic HDR10+ SEI metadata", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DROP_CONTROL, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Drop control", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Chroma QP index for Cb", + .minimum = -12, + .maximum = 12, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Chroma QP index for Cr", + .minimum = -12, + .maximum = 12, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Buffer flag", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Buffer flag", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_GDC_VOTF, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "GDC vOTF", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SKIP_LAZY_UNMAP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "skip lazy unmap", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frames per second in 1000x scale", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 60000, + }, + { + .id = V4L2_CID_MPEG_VIDEO_GOP_CTRL, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Meaning of GOP_SIZE", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_AVERAGE_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Frames average QP", + .minimum = 0, + .maximum = U8_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_SEARCH_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV search mode", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV HOR position L0", + .minimum = -128, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV HOR position L1", + .minimum = -128, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L0, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV VER position L0", + .minimum = -128, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L1, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV VER position L1", + .minimum = -128, + .maximum = 127, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_PRIORITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "priority", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MIN_QUALITY, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "MIN quality mode enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MAX_IFRAME_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "max I frame size", + .minimum = 0, + .maximum = BIT(16) - 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_WP_TWO_PASS_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "WP two pass encoding enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_TIMING_INFO_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Timing info enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_ADAPTIVE_GOP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Adaptive GOP enable", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SUM_SKIP_MB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of skip MB", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SUM_INTRA_MB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of intra MB", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_SUM_ZERO_MV_MB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "The number of zero MV MB", + .minimum = 0, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_HOR_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV HOR Range", + .minimum = 16, + .maximum = 128, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_VIDEO_MV_VER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "MV VER Range", + .minimum = 16, + .maximum = 128, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_MULTI_VIEW_ENABLE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Multi-View Enable", + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_MPEG_MFC_MULTI_VIEW_MAIN_TYPE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Main-View Type", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, +}; + +#define ENC_NUM_CTRLS ARRAY_SIZE(enc_controls) +/* Find selected format description */ +static struct mfc_fmt *__mfc_enc_find_format(struct mfc_ctx *ctx, + unsigned int pixelformat) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_fmt *fmt = NULL; + unsigned long i; + + for (i = 0; i < MFC_NUM_FORMATS; i++) { + if ((mfc_formats[i].type & MFC_FMT_STREAM) && + !(mfc_formats[i].type & MFC_FMT_ENC)) { + continue; + } + if (mfc_formats[i].fourcc == pixelformat) { + fmt = (struct mfc_fmt *)&mfc_formats[i]; + break; + } + } + + if (fmt && !dev->pdata->support_10bit && (fmt->type & MFC_FMT_10BIT)) { + mfc_ctx_err("[FRAME] 10bit is not supported\n"); + fmt = NULL; + } + if (fmt && !dev->pdata->support_422 && (fmt->type & MFC_FMT_422)) { + mfc_ctx_err("[FRAME] 422 is not supported\n"); + fmt = NULL; + } + if (fmt && !dev->pdata->support_rgb && (fmt->type & MFC_FMT_RGB)) { + mfc_ctx_err("[FRAME] RGB is not supported\n"); + fmt = NULL; + } + + if (fmt && (fmt->type & MFC_FMT_STREAM) && + dev->pdata->mfc_resource[fmt->codec_mode].op_core_type == MFC_OP_CORE_NOT_FIXED) { + mfc_ctx_err("[STREAM] %s is not supported\n", fmt->name); + fmt = NULL; + } + + return fmt; +} + +static struct v4l2_queryctrl *__mfc_enc_get_ctrl(int id) +{ + unsigned long i; + + for (i = 0; i < ENC_NUM_CTRLS; ++i) + if (id == enc_controls[i].id) + return &enc_controls[i]; + return NULL; +} + +static int __mfc_enc_check_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + struct v4l2_queryctrl *c; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + + c = __mfc_enc_get_ctrl(ctrl->id); + if (!c) { + mfc_ctx_err("[CTRLS] not supported control id (%#x)\n", ctrl->id); + return -EINVAL; + } + + if (ctrl->id == V4L2_CID_MPEG_VIDEO_GOP_SIZE && ctrl->value > c->maximum) { + mfc_ctx_info("GOP_SIZE is changed to max(%d -> %d)\n", + ctrl->value, c->maximum); + ctrl->value = c->maximum; + } + + if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER || + ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER) { + if ((ctrl->value & ~BIT(16)) < c->minimum || + (ctrl->value & ~BIT(16)) > c->maximum || + (c->step != 0 && (ctrl->value & ~BIT(16)) % c->step != 0)) { + mfc_ctx_err("[CTRLS][%s] Invalid control id: %#x, value: %d (%#x)\n", + c->name, ctrl->id, ctrl->value, ctrl->value); + return -ERANGE; + } else { + return 0; + } + } + + if (ctrl->id == V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY) { + if (ctrl->value < c->minimum || + (ctrl->value + p->num_hier_max_layer - 1) > c->maximum || + (c->step != 0 && (ctrl->value & ~BIT(16)) % c->step != 0)) { + mfc_ctx_err("[CTRLS][%s] Invalid control id: %#x, value: %d (%#x)\n", + c->name, ctrl->id, ctrl->value, ctrl->value); + return -ERANGE; + } else { + return 0; + } + } + + if (ctrl->value < c->minimum || ctrl->value > c->maximum || + (c->step != 0 && ctrl->value % c->step != 0)) { + mfc_ctx_err("[CTRLS][%s] id: %#x, invalid value (%d)\n", + c->name, ctrl->id, ctrl->value); + return -ERANGE; + } + + mfc_ctx_debug(5, "[CTRLS][%s] id: %#x, value: %d (%#x)\n", + c->name, ctrl->id, ctrl->value, ctrl->value); + + return 0; +} + +static inline int __mfc_enc_h264_profile(struct mfc_ctx *ctx, int profile) +{ + int ret = 0; + + switch (profile) { + case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: + ret = MFC_REG_E_PROFILE_H264_MAIN; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: + ret = MFC_REG_E_PROFILE_H264_HIGH; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: + ret = MFC_REG_E_PROFILE_H264_BASELINE; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: + ret = MFC_REG_E_PROFILE_H264_CONSTRAINED_BASELINE; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH: + ret = MFC_REG_E_PROFILE_H264_CONSTRAINED_HIGH; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/* Query capabilities of the device */ +static int mfc_enc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, "MFC", sizeof(cap->driver)); + strscpy(cap->card, "encoder", sizeof(cap->card)); + + return 0; +} + +static int __mfc_enc_enum_fmt(struct mfc_dev *dev, struct v4l2_fmtdesc *f, + unsigned int type) +{ + struct mfc_fmt *fmt; + unsigned long i, j = 0; + + for (i = 0; i < MFC_NUM_FORMATS; ++i) { + if (!(mfc_formats[i].type & type)) + continue; + if (!dev->pdata->support_10bit && (mfc_formats[i].type & MFC_FMT_10BIT)) + continue; + if (!dev->pdata->support_422 && (mfc_formats[i].type & MFC_FMT_422)) + continue; + if (!dev->pdata->support_rgb && (mfc_formats[i].type & MFC_FMT_RGB)) + continue; + + if (j == f->index) { + fmt = &mfc_formats[i]; + strscpy(f->description, fmt->name, + sizeof(f->description)); + f->pixelformat = fmt->fourcc; + + return 0; + } + + ++j; + } + + return -EINVAL; +} + +static int mfc_enc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, + struct v4l2_fmtdesc *f) +{ + struct mfc_dev *dev = video_drvdata(file); + + return __mfc_enc_enum_fmt(dev, f, MFC_FMT_STREAM); +} + +static int mfc_enc_enum_fmt_vid_out_mplane(struct file *file, void *prov, + struct v4l2_fmtdesc *f) +{ + struct mfc_dev *dev = video_drvdata(file); + + return __mfc_enc_enum_fmt(dev, f, MFC_FMT_FRAME); +} + +static int mfc_enc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_enc *enc = ctx->enc_priv; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_raw_info *raw; + int i; + + mfc_ctx_debug_enter(); + + if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "enc dst g_fmt\n"); + /* This is run on output (encoder dest) */ + pix_fmt_mp->width = 0; + pix_fmt_mp->height = 0; + pix_fmt_mp->field = V4L2_FIELD_NONE; + pix_fmt_mp->pixelformat = ctx->dst_fmt->fourcc; + pix_fmt_mp->num_planes = ctx->dst_fmt->mem_planes; + + pix_fmt_mp->plane_fmt[0].bytesperline = enc->dst_buf_size; + pix_fmt_mp->plane_fmt[0].sizeimage = enc->dst_buf_size; + } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "enc src g_fmt\n"); + /* This is run on capture (encoder src) */ + raw = &ctx->raw_buf; + + pix_fmt_mp->width = ctx->img_width; + pix_fmt_mp->height = ctx->img_height; + pix_fmt_mp->field = V4L2_FIELD_NONE; + pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc; + pix_fmt_mp->num_planes = ctx->src_fmt->mem_planes; + for (i = 0; i < ctx->src_fmt->mem_planes; i++) { + pix_fmt_mp->plane_fmt[i].bytesperline = raw->stride[i]; + pix_fmt_mp->plane_fmt[i].sizeimage = raw->plane_size[i]; + } + } else { + mfc_ctx_err("invalid buf type (%d)\n", f->type); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_enc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_fmt *fmt; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + + fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for %s\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "source" : "destination"); + return -EINVAL; + } + if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && + fmt->codec_mode == MFC_FORMATS_NO_CODEC) { + mfc_ctx_err("MFC_FORMATS_NO_CODEC is invalid to dst(fmt is %s)\n", + fmt->name); + return -EINVAL; + } + + /* For resource reservation */ + if ((!ctx->img_width && !ctx->img_height) && + pix_fmt_mp->width > 0 && pix_fmt_mp->height > 0) { + ctx->img_width = pix_fmt_mp->width; + ctx->img_height = pix_fmt_mp->height; + } + + if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + ctx->dst_fmt = fmt; + ctx->codec_mode = ctx->dst_fmt->codec_mode; + ctx->op_core_type = ctx->dev->pdata->mfc_resource[ctx->codec_mode].op_core_type; + } + + mfc_ctx_debug(2, "[%s] resolution %dx%d, %s : %s\n", + V4L2_TYPE_IS_OUTPUT(f->type) ? "FRAME" : "STREAM", + ctx->img_width, ctx->img_height, + V4L2_TYPE_IS_OUTPUT(f->type) ? "pixelformat" : "codectype", fmt->name); + + return 0; +} + +static void __mfc_enc_check_format(struct mfc_ctx *ctx) +{ + ctx->is_422 = 0; + ctx->rgb_bpp = 0; + + switch (ctx->src_fmt->fourcc) { + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + mfc_ctx_debug(2, "[FRAME] is 422 format\n"); + ctx->is_422 = 1; + break; + case V4L2_PIX_FMT_RGB24: + ctx->rgb_bpp = 24; + break; + case V4L2_PIX_FMT_RGB565: + ctx->rgb_bpp = 16; + break; + case V4L2_PIX_FMT_RGB32X: + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_ARGB32: + case V4L2_PIX_FMT_RGB32: + ctx->rgb_bpp = 32; + break; + default: + break; + } + mfc_ctx_debug(2, "[FRAME] 422: %d, rgb: %d\n", + ctx->is_422, ctx->rgb_bpp); +} + +static int __mfc_enc_check_resolution(struct mfc_ctx *ctx) +{ + int max_width = 0, max_height = 0, min_width = 0, min_height = 0, swap_check = 0; + + /* Check max resolution */ + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_ENC: + max_width = 8192; + max_height = 8192; + break; + default: + mfc_ctx_err("Not supported codec(%d)\n", ctx->codec_mode); + return -EINVAL; + } + + if (swap_check) { + if (!((ctx->crop_width < max_width && ctx->crop_height < max_height) || + (ctx->crop_width < max_height && ctx->crop_height < max_width))) { + mfc_ctx_err("Resolution is too big(%dx%d > %dxi%d or %dx%d\n", + ctx->crop_width, ctx->crop_height, max_width, max_height, + max_height, max_width); + return -EINVAL; + } + } else { + if (ctx->crop_width > max_width || ctx->crop_height > max_height) { + mfc_ctx_err("Resolution is too big(%dx%d > %dx%d)\n", + ctx->crop_width, ctx->crop_height, max_width, max_height); + return -EINVAL; + } + } + + /* Check min resolution */ + switch (ctx->codec_mode) { + case MFC_REG_CODEC_H264_ENC: + min_width = 32; + min_height = 32; + break; + default: + mfc_ctx_err("Not supported codec(%d)\n", ctx->codec_mode); + return -EINVAL; + } + + if (ctx->crop_width < min_width || ctx->crop_height < min_height) { + mfc_ctx_err("Resolution is too small(%dx%d < %dx%d)\n", + ctx->crop_width, ctx->crop_height, min_width, min_height); + return -EINVAL; + } + + return 0; +} + +static int mfc_enc_s_fmt_vid_cap_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_enc *enc = ctx->enc_priv; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_fmt *fmt = NULL; + int ret = 0; + + mfc_ctx_debug_enter(); + + if (ctx->vq_dst.streaming) { + mfc_ctx_err("dst queue busy\n"); + return -EBUSY; + } + + fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for destination\n"); + return -EINVAL; + } + ctx->dst_fmt = fmt; + + if ((!ctx->img_width && !ctx->img_height) && + pix_fmt_mp->width > 0 && pix_fmt_mp->height > 0) { + ctx->img_width = pix_fmt_mp->width; + ctx->img_height = pix_fmt_mp->height; + ctx->crop_width = ctx->img_width; + ctx->crop_height = ctx->img_height; + } + + ctx->codec_mode = ctx->dst_fmt->codec_mode; + mfc_ctx_info("[STREAM] codectype: %s(%d), %d x %d\n", + ctx->dst_fmt->name, ctx->codec_mode, + ctx->img_width, ctx->img_height); + + if (__mfc_enc_check_resolution(ctx)) { + mfc_ctx_err("Unsupported MFC resolution\n"); + return -EINVAL; + } + + if (mfc_check_resolution(ctx)) { + mfc_ctx_err("Unsupported product resolution\n"); + return -EINVAL; + } + + enc->dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage; + pix_fmt_mp->plane_fmt[0].bytesperline = 0; + + ret = mfc_rm_instance_open(dev, ctx); + if (ret) + mfc_ctx_err("Failed to instance open\n"); + + if (dev->pdata->support_enc_mode1 && + (dev->debugfs.feature_option & MFC_OPTION_SET_MULTI_CORE_FORCE)) { + if (dev->debugfs.feature_option & MFC_OPTION_MULTI_CORE_DISABLE) { + mfc_ctx_info("[2CORE] multi core mode disabled\n"); + } else { + if (dev->num_inst > 1) + mfc_ctx_debug(2, "[2CORE] multi core bits: %#lx, num inst: %d\n", + dev->multi_core_inst_bits, dev->num_inst); + ctx->stream_op_mode = MFC_OP_TWO_MODE1; + mfc_ctx_info("[2CORE] This stream need to multi core stream_op_mode(%d)\n", + ctx->stream_op_mode); + } + } + + mfc_ctx_debug_leave(); + return ret; +} + +static int __mfc_enc_set_num_fd_frame(struct mfc_ctx *ctx, + struct v4l2_pix_format_mplane *pix_fmt_mp) +{ + int calc_num_planes; + int num_fd_depth_map = 0; + int num_view = 1; + int num_fd_sub_view_meta = 0; + + if (ctx->multi_view_enable) { + if (pix_fmt_mp->flags & MFC_FMT_FLAG_MULTI_VIEW) { + num_view = MFC_NUM_MULTI_VIEW; + num_fd_sub_view_meta = MFC_NUM_FD_SUB_VIEW_META; + } + if (pix_fmt_mp->flags & MFC_FMT_FLAG_DEPTH_MAP) + num_fd_depth_map = MFC_NUM_FD_DEPTH_MAP; + + calc_num_planes = + (ctx->src_fmt->mem_planes + num_fd_depth_map) * num_view + + num_fd_sub_view_meta; + } else { + calc_num_planes = ctx->src_fmt->mem_planes; + } + + if (calc_num_planes != pix_fmt_mp->num_planes) + return -EINVAL; + + mfc_set_view_buf_info(ctx, ctx->src_fmt->mem_planes, + num_fd_depth_map, num_fd_sub_view_meta); + + ctx->num_fd_frame = calc_num_planes; + + return 0; +} + +static int mfc_enc_s_fmt_vid_out_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + struct mfc_fmt *prev_src_fmt = NULL; + struct mfc_fmt *fmt = NULL; + int i, shift; + + mfc_ctx_debug_enter(); + + if (ctx->vq_src.streaming) { + mfc_ctx_err("src queue busy\n"); + return -EBUSY; + } + + /* Backup previous format */ + prev_src_fmt = ctx->src_fmt; + fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + if (!fmt) { + mfc_ctx_err("Unsupported format for source\n"); + return -EINVAL; + } + ctx->src_fmt = fmt; + + if (__mfc_enc_set_num_fd_frame(ctx, pix_fmt_mp)) { + mfc_ctx_err("[FRAME] enc src plane number is different (%d != %d)\n", + ctx->num_fd_frame, pix_fmt_mp->num_planes); + return -EINVAL; + } + + ctx->raw_buf.num_planes = ctx->src_fmt->num_planes; + shift = ctx->src_fmt->num_planes - 2; + ctx->img_width = pix_fmt_mp->width; + ctx->img_height = pix_fmt_mp->height; + for (i = 0; i < ctx->src_fmt->mem_planes; i++) + ctx->bytesperline[i] = pix_fmt_mp->plane_fmt[i].bytesperline; + + __mfc_enc_check_format(ctx); + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + /* Dynamic Resolution & Format Changes */ + if (core_ctx->state == MFCINST_FINISHED) { + mfc_change_state(core_ctx, MFCINST_GOT_INST); + if (ctx->stream_op_mode == MFC_OP_TWO_MODE1) { + core = mfc_get_sub_core_lock(dev, ctx); + if (core) { + core_ctx = core->core_ctx[ctx->num]; + mfc_change_state(core_ctx, MFCINST_GOT_INST); + mfc_clean_core_ctx_int_flags(core_ctx); + } + } + if (ctx->src_fmt->fourcc != prev_src_fmt->fourcc) + mfc_info("[DFC] Enc Dynamic Format Changed %s -> %s\n", + prev_src_fmt->name, ctx->src_fmt->name); + else + mfc_info("[DRC] Enc Dynamic Resolution Changed\n"); + } + + /* When single fd format, use luma stride for chroma stride */ + if (IS_SINGLE_FD(ctx, ctx->src_fmt)) + for (i = 1; i < ctx->src_fmt->num_planes; i++) + ctx->bytesperline[i] = ctx->bytesperline[0] >> shift; + + mfc_info("[FRAME] enc src pixelformat : %s\n", ctx->src_fmt->name); + mfc_info("[FRAME] resolution w: %d, h: %d, Y stride: %d, C stride: %d\n", + pix_fmt_mp->width, pix_fmt_mp->height, + ctx->bytesperline[0], ctx->bytesperline[1]); + + /* + * It should be keep till buffer size and stride was calculated. + * And it can be changed to real encoding size, if user call the s_crop. + */ + ctx->crop_width = ctx->img_width; + ctx->crop_height = ctx->img_height; + mfc_enc_calc_src_size(ctx); + + ctx->output_state = QUEUE_FREE; + + mfc_ctx_debug_leave(); + return 0; +} + +static int mfc_enc_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + + mfc_ctx_debug_enter(); + + s->r.left = ctx->crop_left; + s->r.top = ctx->crop_top; + s->r.width = ctx->crop_width; + s->r.height = ctx->crop_height; + + mfc_ctx_debug(2, "[FRAME] enc crop w: %d, h: %d, offset l: %d t: %d\n", + ctx->crop_width, ctx->crop_height, ctx->crop_left, ctx->crop_top); + + mfc_ctx_debug_leave(); + + return 0; +} + +static int mfc_enc_s_selection(struct file *file, void *priv, + struct v4l2_selection *s) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + + mfc_ctx_debug_enter(); + + if (!V4L2_TYPE_IS_OUTPUT(s->type)) { + mfc_ctx_err("not supported type (It can only in the source)\n"); + return -EINVAL; + } + + if (s->r.left < 0 || s->r.top < 0) { + mfc_ctx_err("[FRAME] crop position is negative\n"); + return -EINVAL; + } + + if (s->r.height > ctx->img_height || s->r.top > ctx->img_height || + s->r.width > ctx->img_width || s->r.left > ctx->img_width || + (s->r.left > (ctx->img_width - s->r.width)) || + (s->r.top > (ctx->img_height - s->r.height))) { + mfc_ctx_err("[FRAME] Out of crop range: (%d,%d,%d,%d) from %dx%d\n", + s->r.left, s->r.top, s->r.width, s->r.height, + ctx->img_width, ctx->img_height); + return -EINVAL; + } + + ctx->crop_top = s->r.top; + ctx->crop_left = s->r.left; + ctx->crop_height = s->r.height; + ctx->crop_width = s->r.width; + + mfc_ctx_debug(3, "[FRAME] enc original: %dx%d, crop: %dx%d, offset l: %d t: %d\n", + ctx->img_width, ctx->img_height, + ctx->crop_width, ctx->crop_height, + ctx->crop_left, ctx->crop_top); + + return 0; +} + +static int mfc_enc_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *reqbufs) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret = 0; + + mfc_ctx_debug_enter(); + + if (reqbufs->memory == V4L2_MEMORY_MMAP) { + mfc_ctx_err("Not supported memory type (%d)\n", reqbufs->memory); + return -EINVAL; + } + + if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_ctx_debug(4, "enc dst reqbuf(%d)\n", reqbufs->count); + + if (reqbufs->count == 0) { + ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); + ctx->capture_state = QUEUE_FREE; + return ret; + } + + if (ctx->capture_state != QUEUE_FREE) { + mfc_ctx_err("invalid capture state: %d\n", ctx->capture_state); + return -EINVAL; + } + + ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); + if (ret) { + mfc_ctx_err("error in vb2_reqbufs() for E(D)\n"); + return ret; + } + + ctx->capture_state = QUEUE_BUFS_REQUESTED; + } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "enc src reqbuf(%d)\n", reqbufs->count); + if (reqbufs->count == 0) { + ret = vb2_reqbufs(&ctx->vq_src, reqbufs); + ctx->output_state = QUEUE_FREE; + return ret; + } + + if (ctx->output_state != QUEUE_FREE) { + mfc_ctx_err("invalid output state: %d\n", ctx->output_state); + return -EINVAL; + } + + ret = vb2_reqbufs(&ctx->vq_src, reqbufs); + if (ret) { + mfc_ctx_err("error in vb2_reqbufs() for E(S)\n"); + return ret; + } + + ctx->output_state = QUEUE_BUFS_REQUESTED; + } else { + mfc_ctx_err("invalid buf type (%d)\n", reqbufs->type); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return ret; +} + +static int mfc_enc_querybuf(struct file *file, void *priv, + struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int ret = 0; + + mfc_ctx_debug_enter(); + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + mfc_debug(4, "enc dst querybuf, state: %d\n", core_ctx->state); + ret = vb2_querybuf(&ctx->vq_dst, buf); + if (ret != 0) { + mfc_err("enc dst: error in vb2_querybuf()\n"); + return ret; + } + } else if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_debug(4, "enc src querybuf, state: %d\n", core_ctx->state); + ret = vb2_querybuf(&ctx->vq_src, buf); + if (ret != 0) { + mfc_err("enc src: error in vb2_querybuf()\n"); + return ret; + } + } else { + mfc_err("invalid buf type (%d)\n", buf->type); + return -EINVAL; + } + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Queue a buffer */ +static int mfc_enc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int i, ret = -EINVAL; + + mfc_ctx_debug_enter(); + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (core_ctx->state == MFCINST_ERROR) { + mfc_err("Call on QBUF after unrecoverable error\n"); + return -EIO; + } + + if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) { + mfc_err("Invalid V4L2 Buffer for driver: type(%d)\n", buf->type); + return -EINVAL; + } + + if (!buf->length) { + mfc_err("multiplanar but length is zero\n"); + return -EIO; + } + + if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_debug(4, "enc src buf[%d] Q\n", buf->index); + + if (ctx->num_fd_frame != buf->length) { + mfc_err("number of memory container miss-match between Src%s planes(%d) and buffer length(%d)\n", + ctx->multi_view_enable ? "(Multi-View)" : "", + ctx->num_fd_frame, buf->length); + return -EINVAL; + } + + mfc_idle_update_queued(dev, ctx); + mfc_rate_update_bufq_framerate(ctx, MFC_TS_SRC_Q); + mfc_rate_update_framerate(ctx); + + for (i = 0; i < ctx->num_fd_frame; i++) { + if (!buf->m.planes[i].bytesused) { + mfc_debug(2, "[FRAME] enc src[%d] %s %d\n", + i, + "size zero, changed to buf size", + buf->m.planes[i].length); + buf->m.planes[i].bytesused = buf->m.planes[i].length; + } else { + mfc_debug(2, "[FRAME] enc src[%d] size %d\n", + i, buf->m.planes[i].bytesused); + } + } + + ret = vb2_qbuf(&ctx->vq_src, NULL, buf); + } else { + mfc_idle_update_queued(dev, ctx); + mfc_rate_update_bufq_framerate(ctx, MFC_TS_DST_Q); + mfc_rate_update_framerate(ctx); + + mfc_debug(4, "enc dst buf[%d] Q\n", buf->index); + ret = vb2_qbuf(&ctx->vq_dst, NULL, buf); + } + + mfc_ctx_debug_leave(); + return ret; +} + +/* Dequeue a buffer */ +static int mfc_enc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = ctx->dev; + struct mfc_core *core; + struct mfc_core_ctx *core_ctx; + int ret; + + mfc_ctx_debug_enter(); + + /* Encoder works only single core */ + core = mfc_get_main_core_lock(dev, ctx); + core_ctx = core->core_ctx[ctx->num]; + + if (core_ctx->state == MFCINST_ERROR) { + mfc_err("Call on DQBUF after unrecoverable error\n"); + return -EIO; + } + + if (!V4L2_TYPE_IS_MULTIPLANAR(buf->type)) { + mfc_err("Invalid V4L2 Buffer for driver: type(%d)\n", buf->type); + return -EINVAL; + } + + if (buf->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + ret = vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK); + mfc_debug(4, "enc src buf[%d] DQ\n", buf->index); + } else { + ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK); + mfc_debug(4, "enc dst buf[%d] DQ\n", buf->index); + } + mfc_ctx_debug_leave(); + return ret; +} + +/* Stream on */ +static int mfc_enc_streamon(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret = -EINVAL; + + mfc_ctx_debug_enter(); + + if (!V4L2_TYPE_IS_MULTIPLANAR(type)) { + mfc_ctx_err("Invalid V4L2 Buffer for driver: type(%d)\n", type); + return -EINVAL; + } + + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "enc src streamon\n"); + ret = vb2_streamon(&ctx->vq_src, type); + if (!ret) + mfc_rm_qos_control(ctx, MFC_QOS_ON); + } else { + mfc_ctx_debug(4, "enc dst streamon\n"); + ret = vb2_streamon(&ctx->vq_dst, type); + } + + mfc_ctx_debug(2, "src: %d, dst: %d, dpb_count = %d\n", + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + ctx->dpb_count); + mfc_ctx_debug_leave(); + return ret; +} + +/* Stream off, which equals to a pause */ +static int mfc_enc_streamoff(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + int ret = -EINVAL; + + mfc_ctx_debug_enter(); + + if (!V4L2_TYPE_IS_MULTIPLANAR(type)) { + mfc_ctx_err("Invalid V4L2 Buffer for driver: type(%d)\n", type); + return -EINVAL; + } + + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mfc_ctx_debug(4, "enc src streamoff\n"); + mfc_rate_reset_last_framerate(ctx); + + ret = vb2_streamoff(&ctx->vq_src, type); + if (!ret) + mfc_rm_qos_control(ctx, MFC_QOS_OFF); + } else { + mfc_ctx_debug(4, "enc dst streamoff\n"); + ret = vb2_streamoff(&ctx->vq_dst, type); + } + + mfc_ctx_debug_leave(); + + return ret; +} + +static int __mfc_enc_ext_info(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + int val = 0; + + val |= ENC_SET_SPARE_SIZE; + val |= ENC_SET_TEMP_SVC_CH; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->skype)) + val |= ENC_SET_SKYPE_FLAG; + + val |= ENC_SET_ROI_CONTROL; + val |= ENC_SET_QP_BOUND_PB; + val |= ENC_SET_FIXED_SLICE; + val |= ENC_SET_PVC_MODE; + val |= ENC_SET_RATIO_OF_INTRA; + val |= ENC_SET_DROP_CONTROL; + val |= ENC_SET_CHROMA_QP_CONTROL; + val |= ENC_SET_BUF_FLAG_CTRL; + val |= ENC_SET_OPERATING_FPS; + val |= ENC_SET_GOP_CTRL; + val |= ENC_SET_PRIORITY; + val |= ENC_SET_TIMING_INFO_ENABLE; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc)) + val |= ENC_SET_COLOR_ASPECT; + + val |= ENC_SET_HP_BITRATE_CONTROL; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_enc)) + val |= ENC_SET_STATIC_INFO; + + if (dev->pdata->support_422) + val |= ENC_SET_VP9_PROFILE_LEVEL; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->average_qp)) + val |= ENC_SET_AVERAGE_QP; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->mv_search_mode)) + val |= ENC_SET_MV_SEARCH_MODE; + + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->max_i_frame_size)) + val |= ENC_SET_IFRAME_SIZE; + + /* + * This is the integrated meaning of all the function support below. + * V4L2_CID_MPEG_VIDEO_WP_TWO_PASS_ENABLE + * V4L2_CID_MPEG_VIDEO_ADAPTIVE_GOP_ENABLE + * V4L2_CID_MPEG_VIDEO_SUM_SKIP_MB + * V4L2_CID_MPEG_VIDEO_SUM_INTRA_MB + * V4L2_CID_MPEG_VIDEO_SUM_ZERO_MV_MB + * V4L2_CID_MPEG_VIDEO_MV_HOR_RANGE + * V4L2_CID_MPEG_VIDEO_MV_VER_RANGE + * V4L2_CID_MPEG_MFC_H264_SUB_GOP_ENABLE + * V4L2_CID_MPEG_MFC_H264_SUB_GOP_TYPE + * V4L2_CID_MPEG_MFC_HEVC_SUB_GOP_ENABLE + */ + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->enc_capability)) + val |= ENC_SET_CAPABILITY; + + mfc_ctx_debug(5, "[CTRLS] ext info val: %#x\n", val); + + return val; +} + +static int __mfc_enc_get_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_ctx_ctrl *ctx_ctrl; + int ret = 0; + int found = 0; + + switch (ctrl->id) { + case V4L2_CID_MPEG_MFC51_VIDEO_STREAM_SIZE: + ctrl->value = enc->dst_buf_size; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TYPE: + ctrl->value = enc->frame_type; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_CHECK_STATE: + ctrl->value = MFCSTATE_PROCESSING; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG: + case V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR: + case V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR: + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS: + case V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG: + case V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG: + case V4L2_CID_MPEG_VIDEO_AVERAGE_QP: + case V4L2_CID_MPEG_VIDEO_SUM_SKIP_MB: + case V4L2_CID_MPEG_VIDEO_SUM_INTRA_MB: + case V4L2_CID_MPEG_VIDEO_SUM_ZERO_MV_MB: + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_GET)) + continue; + + if (ctx_ctrl->id == ctrl->id) { + if (ctx_ctrl->get.has_new) { + ctx_ctrl->get.has_new = 0; + ctrl->value = ctx_ctrl->get.val; + } else { + mfc_ctx_debug(5, "[CTRLS] %s 0x%08x\n", + "Control value is not up to date:", + ctrl->id); + if (ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG) + ctrl->value = IGNORE_TAG; + else + return -EINVAL; + } + + found = 1; + break; + } + } + + if (!found) { + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + return -EINVAL; + } + break; + case V4L2_CID_MPEG_MFC_GET_VERSION_INFO: + ctrl->value = dev->pdata->ip_ver; + break; + case V4L2_CID_MPEG_MFC_GET_DRIVER_INFO: + ctrl->value = MFC_DRIVER_INFO; + break; + case V4L2_CID_MPEG_MFC_GET_EXTRA_BUFFER_SIZE: + ctrl->value = MFC_LINEAR_BUF_SIZE; + break; + case V4L2_CID_MPEG_VIDEO_QOS_RATIO: + ctrl->value = ctx->qos_ratio; + break; + case V4L2_CID_MPEG_MFC_GET_EXT_INFO: + ctrl->value = __mfc_enc_ext_info(ctx); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE: + ctrl->value = mfc_rate_get_framerate(ctx); + break; + case V4L2_CID_MPEG_VIDEO_PRIORITY: + ctrl->value = ctx->prio; + mfc_ctx_debug(2, "[PRIO] user get priority: %d(%d)\n", ctrl->value, ctx->user_prio); + break; + default: + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + ret = -EINVAL; + break; + } + + mfc_ctx_debug(5, "[CTRLS] get id: %#x, value: %d\n", ctrl->id, ctrl->value); + + return ret; +} + +static inline int __mfc_enc_h264_level(enum v4l2_mpeg_video_h264_level lvl) +{ + static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_6_0 + 1] = { + /* V4L2_MPEG_VIDEO_H264_LEVEL_1_0 */ 10, + /* V4L2_MPEG_VIDEO_H264_LEVEL_1B */ 9, + /* V4L2_MPEG_VIDEO_H264_LEVEL_1_1 */ 11, + /* V4L2_MPEG_VIDEO_H264_LEVEL_1_2 */ 12, + /* V4L2_MPEG_VIDEO_H264_LEVEL_1_3 */ 13, + /* V4L2_MPEG_VIDEO_H264_LEVEL_2_0 */ 20, + /* V4L2_MPEG_VIDEO_H264_LEVEL_2_1 */ 21, + /* V4L2_MPEG_VIDEO_H264_LEVEL_2_2 */ 22, + /* V4L2_MPEG_VIDEO_H264_LEVEL_3_0 */ 30, + /* V4L2_MPEG_VIDEO_H264_LEVEL_3_1 */ 31, + /* V4L2_MPEG_VIDEO_H264_LEVEL_3_2 */ 32, + /* V4L2_MPEG_VIDEO_H264_LEVEL_4_0 */ 40, + /* V4L2_MPEG_VIDEO_H264_LEVEL_4_1 */ 41, + /* V4L2_MPEG_VIDEO_H264_LEVEL_4_2 */ 42, + /* V4L2_MPEG_VIDEO_H264_LEVEL_5_0 */ 50, + /* V4L2_MPEG_VIDEO_H264_LEVEL_5_1 */ 51, + /* V4L2_MPEG_VIDEO_H264_LEVEL_5_2 */ 52, + /* V4L2_MPEG_VIDEO_H264_LEVEL_6_0 */ 60, + }; + return t[lvl]; +} + +static inline int __mfc_enc_mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl) +{ + static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_6 + 1] = { + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 */ 0, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B, Simple */ 9, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 */ 1, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 */ 2, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 */ 3, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B, Advanced */ 7, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 */ 4, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 */ 5, + /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_6, Simple */ 6, + }; + return t[lvl]; +} + +static inline int __mfc_enc_vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar) +{ + static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = { + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED */ 0, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 */ 1, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 */ 2, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 */ 3, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 */ 4, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 */ 5, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 */ 6, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 */ 7, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 */ 8, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 */ 9, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 */ 10, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 */ 11, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 */ 12, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 */ 13, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 */ 14, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 */ 15, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 */ 16, + /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED */ 255, + }; + return t[sar]; +} + +static int __mfc_enc_get_roi(struct mfc_ctx *ctx, int value) +{ + struct mfc_enc *enc = ctx->enc_priv; + int index = 0; + + if (enc->sh_handle_roi.fd == -1) { + enc->sh_handle_roi.fd = value; + if (mfc_mem_get_user_shared_handle(ctx, &enc->sh_handle_roi, "ROI")) + return -EINVAL; + } + index = enc->roi_index; + + /* Copy the ROI info from shared buf */ + memcpy(&enc->roi_info[index], enc->sh_handle_roi.vaddr, + sizeof(struct mfc_enc_roi_info)); + if (enc->roi_info[index].size > enc->roi_buf[index].size) { + mfc_ctx_err("[MEMINFO][ROI] roi info size %d is over\n", + enc->roi_info[index].size); + return -EINVAL; + } + + /* Copy the ROI map buffer from user's map buf */ + if (copy_from_user(enc->roi_buf[index].vaddr, + enc->roi_info[index].addr, + enc->roi_info[index].size)) + return -EFAULT; + + return 0; +} + +static int __mfc_enc_set_param(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_MPEG_VIDEO_QOS_RATIO: + ctx->qos_ratio = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_PRIORITY: + mfc_ctx_debug(2, "[PRIO] user set priority: %d\n", ctrl->value); + ctx->user_prio = ctrl->value; + mfc_rm_update_real_time(ctx); + break; + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + p->gop_size = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: + p->slice_mode = + (enum v4l2_mpeg_video_multi_slice_mode)ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: + p->slice_mb = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES: + p->slice_bit = ctrl->value * 8; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB_ROW: + p->slice_mb_row = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB: + p->intra_refresh_mb = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_PADDING: + p->pad = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV: + p->pad_luma = (ctrl->value >> 16) & 0xff; + p->pad_cb = (ctrl->value >> 8) & 0xff; + p->pad_cr = (ctrl->value >> 0) & 0xff; + break; + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: + p->rc_frame = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_BITRATE: + p->rc_bitrate = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF: + p->rc_reaction_coeff = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE: + enc->force_frame_type = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VBV_SIZE: + p->vbv_buf_size = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEADER_MODE: + p->seq_hdr_mode = + (enum v4l2_mpeg_video_header_mode)(ctrl->value); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE: + p->frame_skip_mode = + (enum v4l2_mpeg_mfc51_video_frame_skip_mode) + (ctrl->value); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT: + p->fixed_target_bit = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_B_FRAMES: + p->num_b_frame = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: + p->codec.h264.profile = + __mfc_enc_h264_profile(ctx, (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); + break; + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: + p->codec.h264.level = + __mfc_enc_h264_level((enum v4l2_mpeg_video_h264_level)(ctrl->value)); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE: + p->codec.h264.interlace = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: + p->codec.h264.loop_filter_mode = + (enum v4l2_mpeg_video_h264_loop_filter_mode)(ctrl->value); + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: + p->codec.h264.loop_filter_alpha = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: + p->codec.h264.loop_filter_beta = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: + p->codec.h264.entropy_mode = + (enum v4l2_mpeg_video_h264_entropy_mode)(ctrl->value); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P: + p->num_refs_for_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: + p->codec.h264._8x8_transform = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: + p->rc_mb = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_RC_FRAME_RATE: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: + p->codec.h264.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + p->codec.h264.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: + p->codec.h264.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P: + p->codec.h264.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P: + p->codec.h264.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B: + p->codec.h264.rc_min_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B: + p->codec.h264.rc_max_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK: + p->codec.h264.rc_mb_dark = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH: + p->codec.h264.rc_mb_smooth = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC: + p->codec.h264.rc_mb_static = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY: + p->codec.h264.rc_mb_activity = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: + p->codec.h264.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: + p->codec.h264.rc_b_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE: + p->codec.h264.ar_vui = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: + p->codec.h264.ar_vui_idc = + __mfc_enc_vui_sar_idc((enum v4l2_mpeg_video_h264_vui_sar_idc)(ctrl->value)); + break; + case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH: + p->codec.h264.ext_sar_width = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT: + p->codec.h264.ext_sar_height = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_GOP_CLOSURE: + p->codec.h264.open_gop = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: + p->codec.h264.open_gop_size = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING: + p->codec.h264.hier_qp_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE: + p->codec.h264.hier_qp_type = + (enum v4l2_mpeg_video_h264_hierarchical_coding_type)(ctrl->value); + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER: + p->codec.h264.num_hier_layer = ctrl->value & 0x7; + p->codec.h264.hier_ref_type = (ctrl->value >> 16) & 0x1; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP: + p->codec.h264.hier_qp_layer[(ctrl->value >> 16) & 0x7] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT0: + p->codec.h264.hier_bit_layer[0] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT1: + p->codec.h264.hier_bit_layer[1] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT2: + p->codec.h264.hier_bit_layer[2] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT3: + p->codec.h264.hier_bit_layer[3] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT4: + p->codec.h264.hier_bit_layer[4] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT5: + p->codec.h264.hier_bit_layer[5] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_BIT6: + p->codec.h264.hier_bit_layer[6] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING: + p->codec.h264.sei_gen_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0: + p->codec.h264.sei_fp_curr_frame_0 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: + p->codec.h264.sei_fp_arrangement_type = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO: + p->codec.h264.fmo_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: + switch ((enum v4l2_mpeg_video_h264_fmo_map_type)(ctrl->value)) { + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES: + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN: + case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: + p->codec.h264.fmo_slice_map_type = ctrl->value; + break; + default: + ret = -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP: + p->codec.h264.fmo_slice_num_grp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH: + p->codec.h264.fmo_run_length[(ctrl->value >> 30) & 0x3] = ctrl->value & 0x3FFFFFFF; + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION: + p->codec.h264.fmo_sg_dir = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE: + p->codec.h264.fmo_sg_rate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_ASO: + p->codec.h264.aso_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER: + p->codec.h264.aso_slice_order[(ctrl->value >> 18) & 0x7] &= + ~(0xFF << (((ctrl->value >> 16) & 0x3) << 3)); + p->codec.h264.aso_slice_order[(ctrl->value >> 18) & 0x7] |= + (ctrl->value & 0xFF) << (((ctrl->value >> 16) & 0x3) << 3); + break; + case V4L2_CID_MPEG_VIDEO_H264_PREPEND_SPSPPS_TO_IDR: + p->codec.h264.prepend_sps_pps_to_idr = ctrl->value ? 1 : 0; + break; + case V4L2_CID_MPEG_MFC_H264_ENABLE_LTR: + p->codec.h264.enable_ltr = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_H264_NUM_OF_LTR: + p->codec.h264.num_of_ltr = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY: + p->codec.h264.base_priority = ctrl->value; + p->codec.h264.set_priority = 1; + break; + case V4L2_CID_MPEG_VIDEO_ROI_ENABLE: + p->roi_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_H264_VUI_RESTRICTION_ENABLE: + p->codec.h264.vui_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_CONFIG_QP_ENABLE: + p->dynamic_qp = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_CONFIG_QP: + p->config_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_RC_PVC_ENABLE: + /* It is valid for H.264, HEVC, VP8, VP9 */ + p->rc_pvc = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_TEMPORAL_SHORTTERM_MAX_LAYER: + p->num_hier_max_layer = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIGN_DATA_HIDING: + break; + case V4L2_CID_MPEG_VIDEO_WEIGHTED_ENABLE: + p->weighted_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA: + p->ratio_intra = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG: + p->check_color_range = 1; + p->color_range = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES: + p->colour_primaries = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_TRANSFER_CHARACTERISTICS: + p->transfer_characteristics = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MATRIX_COEFFICIENTS: + p->matrix_coefficients = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HIERARCHICAL_BITRATE_CTRL: + p->hier_bitrate_ctrl = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_STATIC_INFO_ENABLE: + p->static_info_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_MAX_PIC_AVERAGE_LIGHT: + p->max_pic_average_light = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_MAX_CONTENT_LIGHT: + p->max_content_light = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_MAX_DISPLAY_LUMINANCE: + p->max_display_luminance = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_MIN_DISPLAY_LUMINANCE: + p->min_display_luminance = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_WHITE_POINT: + p->white_point = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_0: + p->display_primaries_0 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_1: + p->display_primaries_1 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_2: + p->display_primaries_2 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DROP_CONTROL: + p->drop_control = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CB: + p->chroma_qp_offset_cb = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_CHROMA_QP_OFFSET_CR: + p->chroma_qp_offset_cr = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_SKIP_LAZY_UNMAP: + ctx->skip_lazy_unmap = ctrl->value; + mfc_ctx_debug(2, "[LAZY_UNMAP] lazy unmap %s\n", + ctx->skip_lazy_unmap ? "disable" : "enable"); + break; + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE: + mfc_ctx_debug(2, "[QoS] user set the operating frame rate: %d\n", ctrl->value); + ctx->operating_framerate = ctrl->value; + mfc_rm_update_real_time(ctx); + break; + case V4L2_CID_MPEG_VIDEO_GOP_CTRL: + p->gop_ctrl = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_SEARCH_MODE: + p->mv_search_mode = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L0: + p->mv_hor_pos_l0 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L1: + p->mv_hor_pos_l1 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L0: + p->mv_ver_pos_l0 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L1: + p->mv_ver_pos_l1 = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MIN_QUALITY: + p->min_quality_mode = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MAX_IFRAME_SIZE: + p->max_i_frame_size = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_WP_TWO_PASS_ENABLE: + p->wp_two_pass_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_ADAPTIVE_GOP_ENABLE: + p->adaptive_gop_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_HOR_RANGE: + p->mv_hor_range = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MV_VER_RANGE: + p->mv_ver_range = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_TIMING_INFO_ENABLE: + p->timing_info_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_MULTI_VIEW_ENABLE: + ctx->multi_view_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC_MULTI_VIEW_MAIN_TYPE: + ctx->left_view_id = ((ctrl->value & 0x1) == 0) ? MFC_VIEW_ID_MAIN : MFC_VIEW_ID_SUB; + break; + /* These are stored in specific variables */ + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH: + /* These require control per buffer */ + case V4L2_CID_MPEG_VIDEO_YSUM: + case V4L2_CID_MPEG_VIDEO_ROI_CONTROL: + case V4L2_CID_MPEG_MFC_H264_USE_LTR: + case V4L2_CID_MPEG_MFC_H264_MARK_LTR: + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG: + case V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG: + case V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG: + break; + default: + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + ret = -EINVAL; + } + + return ret; +} + +static int __mfc_enc_set_ctrl_val_list(struct mfc_ctx *ctx, + struct v4l2_control *ctrl) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_ctx_ctrl *ctx_ctrl; + int ret = 0; + int found = 0; + + list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { + if (!(ctx_ctrl->type & MFC_CTRL_TYPE_SET)) + continue; + + if (ctx_ctrl->id == ctrl->id) { + ctx_ctrl->set.has_new = 1; + ctx_ctrl->set.val = ctrl->value; + if (ctx_ctrl->id == + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH) { + if (enc->sh_handle_svc.fd == -1) { + enc->sh_handle_svc.fd = ctrl->value; + if (mfc_mem_get_user_shared_handle + (ctx, &enc->sh_handle_svc, "SVC")) + return -EINVAL; + } + } + if (ctx_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH && + p->i_frm_ctrl_mode) { + if (!p->gop_ctrl) + ctx_ctrl->set.val = ctx_ctrl->set.val * + (p->num_b_frame + 1); + + if (ctx_ctrl->set.val >= 0x3FFFFFFF) { + mfc_ctx_info("I frame interval is bigger than max: %d\n", + ctx_ctrl->set.val); + ctx_ctrl->set.val = 0x3FFFFFFF; + } + } + if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) + ctx_ctrl->set.val = __mfc_enc_h264_level + ((enum v4l2_mpeg_video_h264_level)(ctrl->value)); + if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) + ctx_ctrl->set.val = + __mfc_enc_h264_profile + (ctx, + (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); + if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_ROI_CONTROL) { + ret = __mfc_enc_get_roi(ctx, ctrl->value); + if (ret) + return ret; + } + + found = 1; + break; + } + } + + if (!found) { + mfc_ctx_err("Invalid control: 0x%08x\n", ctrl->id); + return -EINVAL; + } + + return ret; +} + +static int __mfc_enc_set_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) +{ + int ret = 0; + + /* update parameter value */ + ret = __mfc_enc_set_param(ctx, ctrl); + if (ret) + return ret; + + switch (ctrl->id) { + case V4L2_CID_MPEG_VIDEO_QOS_RATIO: + break; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B: + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B: + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG: + case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE: + case V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH: + case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH: + case V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH: + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: + case V4L2_CID_MPEG_MFC_H264_MARK_LTR: + case V4L2_CID_MPEG_MFC_H264_USE_LTR: + case V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY: + case V4L2_CID_MPEG_MFC_CONFIG_QP: + case V4L2_CID_MPEG_VIDEO_ROI_CONTROL: + case V4L2_CID_MPEG_VIDEO_YSUM: + case V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA: + case V4L2_CID_MPEG_VIDEO_DROP_CONTROL: + case V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L0: + case V4L2_CID_MPEG_VIDEO_MV_HOR_POSITION_L1: + case V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L0: + case V4L2_CID_MPEG_VIDEO_MV_VER_POSITION_L1: + case V4L2_CID_MPEG_VIDEO_MAX_IFRAME_SIZE: + case V4L2_CID_MPEG_VIDEO_SRC_BUF_FLAG: + case V4L2_CID_MPEG_VIDEO_DST_BUF_FLAG: + ret = __mfc_enc_set_ctrl_val_list(ctx, ctrl); + break; + default: + break; + } + + return ret; +} + +static int mfc_enc_g_ext_ctrls(struct file *file, void *priv, + struct v4l2_ext_controls *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_ext_control *ext_ctrl; + struct v4l2_control ctrl; + int i; + int ret = 0; + + if (f->which != V4L2_CTRL_CLASS_CODEC && f->which != V4L2_CTRL_CLASS_USER) + return -EINVAL; + + for (i = 0; i < f->count; i++) { + ext_ctrl = (f->controls + i); + + ctrl.id = ext_ctrl->id; + + ret = __mfc_enc_get_ctrl_val(ctx, &ctrl); + if (ret == 0) { + ext_ctrl->value = ctrl.value; + } else { + f->error_idx = i; + break; + } + + mfc_ctx_debug(5, "[CTRLS][%d] id: %#x, value: %d\n", + i, ext_ctrl->id, ext_ctrl->value); + } + + return ret; +} + +static int mfc_enc_s_ext_ctrls(struct file *file, void *priv, + struct v4l2_ext_controls *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_ext_control *ext_ctrl; + struct v4l2_control ctrl; + int i; + int ret = 0; + + mfc_ctx_debug_enter(); + + if (f->which != V4L2_CTRL_CLASS_CODEC && f->which != V4L2_CTRL_CLASS_USER) + return -EINVAL; + + for (i = 0; i < f->count; i++) { + ext_ctrl = (f->controls + i); + + ctrl.id = ext_ctrl->id; + ctrl.value = ext_ctrl->value; + + ret = __mfc_enc_check_ctrl_val(ctx, &ctrl); + if (ret != 0) { + f->error_idx = i; + break; + } + + if (f->which == V4L2_CTRL_CLASS_USER) + ret = __mfc_enc_set_ctrl_val(ctx, &ctrl); + else + ret = __mfc_enc_set_param(ctx, &ctrl); + if (ret != 0) { + f->error_idx = i; + break; + } + } + + mfc_ctx_debug_leave(); + + return ret; +} + +static int mfc_enc_try_ext_ctrls(struct file *file, void *priv, + struct v4l2_ext_controls *f) +{ + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct v4l2_ext_control *ext_ctrl; + struct v4l2_control ctrl; + int i; + int ret = 0; + + mfc_ctx_debug_enter(); + + if (f->which != V4L2_CTRL_CLASS_CODEC) + return -EINVAL; + + for (i = 0; i < f->count; i++) { + ext_ctrl = (f->controls + i); + + ctrl.id = ext_ctrl->id; + ctrl.value = ext_ctrl->value; + + ret = __mfc_enc_check_ctrl_val(ctx, &ctrl); + if (ret != 0) { + f->error_idx = i; + break; + } + } + + mfc_ctx_debug_leave(); + + return ret; +} + +/* Initialize for default format */ +void mfc_enc_set_default_format(struct mfc_ctx *ctx) +{ + struct mfc_fmt *fmt = NULL; + + /* Set default format for source */ + fmt = __mfc_enc_find_format(ctx, V4L2_PIX_FMT_NV12M); + if (!fmt) { + /* NEVER come here */ + mfc_ctx_err("Wrong memory access. Set fmt by mfc_formats[0]\n"); + fmt = &mfc_formats[0]; + } + ctx->src_fmt = fmt; + + /* Set default format for destination */ + fmt = __mfc_enc_find_format(ctx, V4L2_PIX_FMT_H264); + if (!fmt) { + /* NEVER come here */ + mfc_ctx_err("Wrong memory access. Set fmt by mfc_formats[0]\n"); + fmt = &mfc_formats[0]; + } + ctx->dst_fmt = fmt; +} + +static const struct v4l2_ioctl_ops mfc_enc_ioctl_ops = { + .vidioc_querycap = mfc_enc_querycap, + .vidioc_enum_fmt_vid_cap = mfc_enc_enum_fmt_vid_cap_mplane, + .vidioc_enum_fmt_vid_out = mfc_enc_enum_fmt_vid_out_mplane, + .vidioc_g_fmt_vid_cap_mplane = mfc_enc_g_fmt, + .vidioc_g_fmt_vid_out_mplane = mfc_enc_g_fmt, + .vidioc_try_fmt_vid_cap_mplane = mfc_enc_try_fmt, + .vidioc_try_fmt_vid_out_mplane = mfc_enc_try_fmt, + .vidioc_s_fmt_vid_cap_mplane = mfc_enc_s_fmt_vid_cap_mplane, + .vidioc_s_fmt_vid_out_mplane = mfc_enc_s_fmt_vid_out_mplane, + .vidioc_g_selection = mfc_enc_g_selection, + .vidioc_s_selection = mfc_enc_s_selection, + .vidioc_reqbufs = mfc_enc_reqbufs, + .vidioc_querybuf = mfc_enc_querybuf, + .vidioc_qbuf = mfc_enc_qbuf, + .vidioc_dqbuf = mfc_enc_dqbuf, + .vidioc_streamon = mfc_enc_streamon, + .vidioc_streamoff = mfc_enc_streamoff, + .vidioc_g_ext_ctrls = mfc_enc_g_ext_ctrls, + .vidioc_s_ext_ctrls = mfc_enc_s_ext_ctrls, + .vidioc_try_ext_ctrls = mfc_enc_try_ext_ctrls, +}; + +const struct v4l2_ioctl_ops *mfc_get_enc_v4l2_ioctl_ops(void) +{ + return &mfc_enc_ioctl_ops; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h new file mode 100644 index 000000000000..93cca69ae385 --- /dev/null +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * mfc_enc_v4l2.h file + * + * Nagaraju Siddineni, <nagaraju.s@samsung.com> + * Himanshu Dewangan, <h.dewangan@samsung.com> + */ + +#ifndef __MFC_ENC_V4L2_H +#define __MFC_ENC_V4L2_H __FILE__ + +#include "base/mfc_common.h" + +const struct v4l2_ioctl_ops *mfc_get_enc_v4l2_ioctl_ops(void); +void mfc_enc_set_default_format(struct mfc_ctx *ctx); + +#endif /* __MFC_ENC_V4L2_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035703epcas5p18e09c3e9e07401f4b268ea77bc831987@epcas5p1.samsung.com>]
* [PATCH 26/29] media: mfc: Add full encoder support [not found] ` <CGME20250930035703epcas5p18e09c3e9e07401f4b268ea77bc831987@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Integrate encoder command API into core flow. - Extend hardware‑lock handling for encoder state. - Manage encoder resources on instance open/close. - Add APIs for buffers, codec parameters, and status. - Update core ops, macros, headers, and error handling. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/mfc_core_cmd.c | 119 ++++++++++++ .../samsung/exynos-mfc/mfc_core_cmd.h | 6 + .../samsung/exynos-mfc/mfc_core_hwlock.c | 61 +++++++ .../samsung/exynos-mfc/mfc_core_ops.c | 154 ++++++++++++++++ .../samsung/exynos-mfc/mfc_core_reg_api.c | 169 ++++++++++++++++++ .../samsung/exynos-mfc/mfc_core_reg_api.h | 55 ++++++ .../samsung/exynos-mfc/mfc_core_run.c | 127 +++++++++++++ .../samsung/exynos-mfc/mfc_core_run.h | 5 + 8 files changed, 696 insertions(+) diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c index aaf216741575..a1de7920786b 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c @@ -12,6 +12,7 @@ #include "mfc_core_cmd.h" #include "mfc_core_intlock.h" +#include "mfc_core_enc_param.h" #include "mfc_core_hw_reg_api.h" #include "base/mfc_utils.h" @@ -286,6 +287,28 @@ void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx) mfc_debug_leave(); } +int mfc_core_cmd_enc_seq_header(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int ret; + + mfc_debug_enter(); + + ret = mfc_core_set_enc_params(core, ctx); + if (ret) { + mfc_debug(2, "fail to set enc params\n"); + return ret; + } + + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_SEQ_HEADER); + + mfc_debug_leave(); + + return 0; +} + int mfc_core_cmd_dec_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx) { struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; @@ -326,6 +349,58 @@ int mfc_core_cmd_dec_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx) return ret; } +int mfc_core_cmd_enc_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + unsigned int reg = 0; + int ret; + + /* + * Header was generated now starting processing + * First set the reference frame buffers + */ + if (!core_ctx->codec_buffer_allocated) { + mfc_info("there isn't codec buffer, re-alloc!\n"); + ret = mfc_alloc_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to allocate encoding buffers\n"); + mfc_change_state(core_ctx, MFCINST_ERROR); + return ret; + } + } + + mfc_clean_core_ctx_int_flags(core_ctx); + ret = mfc_core_set_enc_codec_buffers(core_ctx); + if (ret) { + mfc_info("isn't enough codec buffer size, re-alloc!\n"); + + mfc_release_codec_buffers(core_ctx); + ret = mfc_alloc_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to allocate encoding buffers\n"); + return ret; + } + ret = mfc_core_set_enc_codec_buffers(core_ctx); + if (ret) { + mfc_err("Failed to set enc codec buffers\n"); + return ret; + } + } + + if (IS_MULTI_MODE(ctx)) { + reg |= ((ctx->subcore_inst_no & MFC_REG_RET_INSTANCE_ID_OF_MFC1_MASK) + << MFC_REG_RET_INSTANCE_ID_OF_MFC1_SHIFT); + reg |= (core_ctx->inst_no & MFC_REG_RET_INSTANCE_ID_MASK); + MFC_CORE_WRITEL(reg, MFC_REG_INSTANCE_ID); + } else { + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + } + + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_INIT_BUFFERS); + + return ret; +} + static int __mfc_set_scratch_dpb_buffer(struct mfc_core *core, struct mfc_ctx *ctx) { struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; @@ -455,3 +530,47 @@ int mfc_core_cmd_dec_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, mfc_debug(2, "Decoding a usual frame\n"); return 0; } + +/* Encode a single frame */ +void mfc_core_cmd_enc_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, + int last_frame) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + u32 timeout_value = MFC_TIMEOUT_VALUE; + unsigned int reg = 0; + + mfc_debug_enter(); + + if (core->dev->pdata->support_enc_mode1) { + reg = MFC_CORE_READL(MFC_REG_E_HEVC_NAL_CONTROL); + mfc_clear_set_bits(reg, 0x1, 11, IS_MULTI_MODE(ctx)); + MFC_CORE_WRITEL(reg, MFC_REG_E_HEVC_NAL_CONTROL); + } + + reg = MFC_CORE_READL(MFC_REG_E_HEVC_NAL_CONTROL); + mfc_clear_set_bits(reg, 0x3, 12, ctx->select_view ? 0x3 : 0x0); + MFC_CORE_WRITEL(reg, MFC_REG_E_HEVC_NAL_CONTROL); + + if (core->last_mfc_freq) + timeout_value = (core->last_mfc_freq * MFC_TIMEOUT_VALUE_IN_MSEC); + mfc_debug(2, "Last MFC Freq: %d, Timeout Value: %d\n", + core->last_mfc_freq, timeout_value); + + MFC_CORE_WRITEL(timeout_value, MFC_REG_TIMEOUT_VALUE); + MFC_CORE_WRITEL(core_ctx->inst_no, MFC_REG_INSTANCE_ID); + + /* + * Issue different commands to instance basing on whether it + * is the last frame or not. + */ + switch (last_frame) { + case 0: + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_NAL_START); + break; + case 1: + mfc_core_cmd_host2risc(core, MFC_REG_H2R_CMD_LAST_FRAME); + break; + } + + mfc_debug_leave(); +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h index 216d07c564ae..91da9eeff904 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h @@ -28,8 +28,14 @@ void mfc_core_cmd_dpb_flush(struct mfc_core *core, struct mfc_ctx *ctx); void mfc_core_cmd_cache_flush(struct mfc_core *core); void mfc_core_cmd_dec_seq_header(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_cmd_enc_seq_header(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_cmd_dec_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_cmd_enc_init_buffers(struct mfc_core *core, struct mfc_ctx *ctx); + int mfc_core_cmd_dec_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, int last_frame, int src_index); +void mfc_core_cmd_enc_one_frame(struct mfc_core *core, struct mfc_ctx *ctx, + int last_frame); + #endif /* __MFC_CORE_CMD_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c index 0b594429fd59..5456368f5410 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c @@ -508,6 +508,65 @@ static int __mfc_just_run_dec(struct mfc_core *core, struct mfc_ctx *ctx) return ret; } +static int __mfc_just_run_enc(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_core *subcore; + struct mfc_core_ctx *subcore_ctx; + int ret = 0; + + switch (core_ctx->state) { + case MFCINST_FINISHING: + ret = mfc_core_run_enc_last_frames(core, ctx); + break; + case MFCINST_RUNNING: + ret = mfc_core_run_enc_frame(core, ctx); + break; + case MFCINST_INIT: + mfc_core_cmd_open_inst(core, ctx); + break; + case MFCINST_RETURN_INST: + ret = mfc_core_cmd_close_inst(core, ctx); + break; + case MFCINST_GOT_INST: + ret = mfc_core_run_enc_init(core, ctx); + break; + case MFCINST_HEAD_PARSED: + if (ctx->stream_op_mode == MFC_OP_TWO_MODE1) { + if (core->id == MFC_CORE_SUB) { + mfc_ctx_err("init buffer should be called to main core, so try again\n"); + return -EAGAIN; + } + + subcore = mfc_get_sub_core(ctx->dev, ctx); + if (!subcore) { + mfc_ctx_err("Failed to get subcore before calling INIT_BUF\n"); + return -EAGAIN; + } + subcore_ctx = subcore->core_ctx[ctx->num]; + if (mfc_wait_for_done_core_ctx(subcore_ctx, + MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + mfc_ctx_err("sub core header parsing should be done before init buffer\n"); + return -EAGAIN; + } + } + ret = mfc_core_cmd_enc_init_buffers(core, ctx); + break; + case MFCINST_ABORT_INST: + mfc_core_cmd_abort_inst(core, ctx); + break; + case MFCINST_MOVE_INST: + mfc_core_cmd_move_inst(core, ctx); + break; + default: + mfc_info("can't try command(encoder just_run), state : %d\n", + core_ctx->state); + ret = -EAGAIN; + } + + return ret; +} + /* Run an operation on hardware */ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) { @@ -557,6 +616,8 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) if (ctx->type == MFCINST_DECODER) { ret = __mfc_just_run_dec(core, ctx); + } else if (ctx->type == MFCINST_ENCODER) { + ret = __mfc_just_run_enc(core, ctx); } else { mfc_err("invalid context type: %d\n", ctx->type); ret = -EAGAIN; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c index f8a27548b218..fc90650c228c 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c @@ -322,6 +322,9 @@ static int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx) mfc_core_release_hwlock_ctx(core_ctx); mfc_core_destroy_listable_wq_ctx(core_ctx); + if (ctx->type == MFCINST_ENCODER) + mfc_release_enc_roi_buffer(core_ctx); + mfc_delete_queue(&core_ctx->src_buf_queue); core->core_ctx[core_ctx->num] = 0; @@ -361,6 +364,32 @@ static int __mfc_core_instance_open_dec(struct mfc_ctx *ctx, return 0; } +static int __mfc_core_instance_open_enc(struct mfc_ctx *ctx, + struct mfc_core_ctx *core_ctx) +{ + int ret = 0; + + ret = mfc_alloc_instance_context(core_ctx); + if (ret) { + mfc_err("Failed to allocate enc instance[%d] buffers\n", + core_ctx->num); + mfc_core_release_hwlock_ctx(core_ctx); + return -ENOMEM; + } + + ctx->capture_state = QUEUE_FREE; + + ret = mfc_alloc_enc_roi_buffer(core_ctx); + if (ret) { + mfc_err("[ROI] Failed to allocate ROI buffers\n"); + mfc_release_instance_context(core_ctx); + mfc_core_release_hwlock_ctx(core_ctx); + return -ENOMEM; + } + + return 0; +} + static int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx) { struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; @@ -380,6 +409,9 @@ static int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx) if (ctx->type == MFCINST_DECODER) { if (__mfc_core_instance_open_dec(ctx, core_ctx)) return -EAGAIN; + } else if (ctx->type == MFCINST_ENCODER) { + if (__mfc_core_instance_open_enc(ctx, core_ctx)) + return -EAGAIN; } else { mfc_err("invalid codec type: %d\n", ctx->type); return -EINVAL; @@ -414,6 +446,8 @@ static int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx) mfc_core_release_hwlock_ctx(core_ctx); core->sched->yield_work(core, core_ctx); mfc_release_instance_context(core_ctx); + if (ctx->type == MFCINST_ENCODER) + mfc_release_enc_roi_buffer(core_ctx); return ret; } @@ -619,6 +653,124 @@ static int mfc_core_instance_init_buf(struct mfc_core *core, struct mfc_ctx *ctx return 0; } +static void mfc_core_instance_q_flush(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int index = 0; + int ret = 0; + + /* If a H/W operation is in progress, wait for it complete */ + if (NEED_TO_WAIT_NAL_ABORT(core_ctx)) { + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_NAL_ABORT_RET)) { + mfc_err("time out during nal abort\n"); + core->sched->yield_work(core, core_ctx); + } + } + + ret = mfc_core_get_hwlock_ctx(core_ctx); + if (ret < 0) { + mfc_err("Failed to get hwlock\n"); + MFC_TRACE_CTX_LT("[ERR][Release] failed to get hwlock (shutdown: %d)\n", + core->shutdown); + return; + } + + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + + while (index < MFC_MAX_BUFFERS) { + index = find_next_bit(ctx->dst_ctrls_avail, MFC_MAX_BUFFERS, index); + if (index < MFC_MAX_BUFFERS) + call_cop(ctx, reset_buf_ctrls, &ctx->dst_ctrls[index]); + index++; + } + + if (core_ctx->state == MFCINST_FINISHING) + mfc_change_state(core_ctx, MFCINST_FINISHED); + + mfc_debug(2, "encoder destination stop sequence done\n"); + + core->sched->clear_work(core, core_ctx); + mfc_core_release_hwlock_ctx(core_ctx); + + core->sched->enqueue_work(core, core_ctx); + if (core->sched->is_work(core)) + core->sched->queue_work(core); +} + +static void mfc_core_instance_finishing(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int index = 0; + int ret = 0; + + /* If a H/W operation is in progress, wait for it complete */ + if (NEED_TO_WAIT_NAL_ABORT(core_ctx)) { + if (mfc_wait_for_done_core_ctx(core_ctx, MFC_REG_R2H_CMD_NAL_ABORT_RET)) { + mfc_err("time out during nal abort\n"); + core->sched->yield_work(core, core_ctx); + } + } + + ret = mfc_core_get_hwlock_ctx(core_ctx); + if (ret < 0) { + mfc_err("Failed to get hwlock\n"); + MFC_TRACE_CTX_LT("[ERR][Release] failed to get hwlock (shutdown: %d)\n", + core->shutdown); + return; + } + + if (core_ctx->state == MFCINST_RUNNING || core_ctx->state == MFCINST_FINISHING || + (IS_SWITCH_SINGLE_MODE(ctx) && core->id == ctx->op_core_num[MFC_CORE_SUB])) { + mfc_change_state(core_ctx, MFCINST_FINISHING); + core->sched->set_work(core, core_ctx); + + while (core_ctx->state != MFCINST_FINISHED) { + ret = mfc_core_just_run(core, ctx->num); + if (ret) { + mfc_err("Failed to run MFC\n"); + break; + } + if (mfc_wait_for_done_core_ctx(core_ctx, + MFC_REG_R2H_CMD_FRAME_DONE_RET)) { + mfc_err("Waiting for LAST_SEQ timed out\n"); + break; + } + } + } + + ctx->serial_src_index = 0; + mfc_move_buf_all(ctx, &core_ctx->src_buf_queue, + &ctx->ref_buf_queue, MFC_QUEUE_ADD_BOTTOM); + mfc_move_buf_all(ctx, &core_ctx->src_buf_queue, + &ctx->src_buf_ready_queue, MFC_QUEUE_ADD_BOTTOM); + mfc_cleanup_enc_src_queue(core_ctx); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->err_buf_queue); + + while (index < MFC_MAX_BUFFERS) { + index = find_next_bit(ctx->src_ctrls_avail, MFC_MAX_BUFFERS, index); + if (index < MFC_MAX_BUFFERS) + call_cop(ctx, reset_buf_ctrls, &ctx->src_ctrls[index]); + index++; + } + + if (core_ctx->state == MFCINST_FINISHING || + core_ctx->state == MFCINST_GOT_INST || + core_ctx->state == MFCINST_HEAD_PARSED) { + mfc_debug(2, "%d status can continue encoding without CLOSE_INSTANCE\n", + core_ctx->state); + mfc_change_state(core_ctx, MFCINST_FINISHED); + } + + mfc_debug(2, "encoder source stop sequence done\n"); + + core->sched->clear_work(core, core_ctx); + mfc_core_release_hwlock_ctx(core_ctx); + + core->sched->enqueue_work(core, core_ctx); + if (core->sched->is_work(core)) + core->sched->queue_work(core); +} + static int mfc_core_request_work(struct mfc_core *core, enum mfc_request_work work, struct mfc_ctx *ctx) @@ -650,6 +802,8 @@ static const struct mfc_core_ops mfc_core_ops = { .instance_move_from = mfc_core_instance_move_from, .instance_dpb_flush = mfc_core_instance_dpb_flush, .instance_init_buf = mfc_core_instance_init_buf, + .instance_q_flush = mfc_core_instance_q_flush, + .instance_finishing = mfc_core_instance_finishing, .request_work = mfc_core_request_work, }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c index 0cc5d1d9433e..d4e9cb4e4e79 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c @@ -225,6 +225,63 @@ int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx) return 0; } +/* Set encoding ref & codec buffer */ +int mfc_core_set_enc_codec_buffers(struct mfc_core_ctx *core_ctx) +{ + struct mfc_core *core = core_ctx->core; + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_enc *enc = ctx->enc_priv; + dma_addr_t buf_addr; + int buf_size; + int i; + + mfc_debug_enter(); + + buf_addr = core_ctx->codec_buf.daddr; + buf_size = core_ctx->codec_buf.size; + + mfc_debug(2, "[MEMINFO] codec buf 0x%llx, size: %d\n", buf_addr, buf_size); + mfc_debug(2, "DPB COUNT: %d\n", ctx->dpb_count); + + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_SCRATCH_BUFFER_ADDR); + MFC_CORE_WRITEL(ctx->scratch_buf_size, MFC_REG_E_SCRATCH_BUFFER_SIZE); + buf_addr += ctx->scratch_buf_size; + buf_size -= ctx->scratch_buf_size; + + /* start address of per buffer is aligned */ + for (i = 0; i < ctx->dpb_count; i++) { + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_LUMA_DPB + (4 * i)); + buf_addr += enc->luma_dpb_size; + buf_size -= enc->luma_dpb_size; + } + for (i = 0; i < ctx->dpb_count; i++) { + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_CHROMA_DPB + (4 * i)); + buf_addr += enc->chroma_dpb_size; + buf_size -= enc->chroma_dpb_size; + } + for (i = 0; i < ctx->dpb_count; i++) { + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_ME_BUFFER + (4 * i)); + buf_addr += enc->me_buffer_size; + buf_size -= enc->me_buffer_size; + } + + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_TMV_BUFFER0); + buf_addr += enc->tmv_buffer_size >> 1; + MFC_CORE_DMA_WRITEL(buf_addr, MFC_REG_E_TMV_BUFFER1); + buf_addr += enc->tmv_buffer_size >> 1; + buf_size -= enc->tmv_buffer_size; + + mfc_debug(2, "[MEMINFO] codec buf 0x%llx, remained size: %d\n", buf_addr, buf_size); + if (buf_size < 0) { + mfc_debug(2, "[MEMINFO] Not enough memory has been allocated\n"); + return -ENOMEM; + } + + mfc_debug_leave(); + + return 0; +} + /* Set registers for decoding stream buffer */ int mfc_core_set_dec_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, unsigned int start_num_byte, @@ -273,6 +330,118 @@ int mfc_core_set_dec_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, return 0; } +void mfc_core_set_enc_frame_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, int num_planes) +{ + dma_addr_t addr[3] = { 0, 0, 0 }; + int index, i; + int index_view; + + if (!mfc_buf) { + mfc_ctx_debug(3, "enc zero buffer set\n"); + goto buffer_set; + } + + index = mfc_buf->vb.vb2_buf.index; + if (mfc_buf->num_valid_bufs > 0) { + for (i = 0; i < num_planes; i++) { + addr[i] = mfc_buf->addr[mfc_buf->next_index][i]; + mfc_ctx_debug(2, "[BUFCON][BUFINFO] set src index: %d, batch[%d], addr[%d]: 0x%08llx\n", + index, mfc_buf->next_index, i, addr[i]); + } + mfc_buf->next_index++; + } else { + index_view = ctx->select_view == MFC_VIEW_ID_MAIN ? MFC_MV_BUF_IDX_VIEW0 + : MFC_MV_BUF_IDX_VIEW1; + for (i = 0; i < num_planes; i++) { + addr[i] = mfc_buf->addr[index_view][i]; + mfc_ctx_debug(2, "[BUFINFO] set src index: %d(%d), addr[%d]: 0x%08llx\n", + index, mfc_buf->src_index, i, addr[i]); + } + } + +buffer_set: + for (i = 0; i < num_planes; i++) + MFC_CORE_DMA_WRITEL(addr[i], MFC_REG_E_SOURCE_FIRST_ADDR + (i * 4)); +} + +/* Set registers for encoding stream buffer */ +int mfc_core_set_enc_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf) +{ + dma_addr_t addr = 0; + unsigned int size = 0, offset = 0, index = -1; + + if (mfc_buf) { + index = mfc_buf->vb.vb2_buf.index; + addr = mfc_buf->addr[0][0]; + offset = mfc_buf->vb.vb2_buf.planes[0].data_offset; + size = (unsigned int)vb2_plane_size(&mfc_buf->vb.vb2_buf, 0); + size = ALIGN(size, STREAM_BUF_ALIGN); + } else { + /* + * When LAST_SEQ of B frame encoding + * if there is no output buffer, set addr and size with 0xffffffff + * and then FW returns COMPLETE_SEQ. + */ + addr = 0xffffffff; + size = 0xffffffff; + } + + MFC_CORE_DMA_WRITEL(addr, MFC_REG_E_STREAM_BUFFER_ADDR); /* 16B align */ + MFC_CORE_WRITEL(size, MFC_REG_E_STREAM_BUFFER_SIZE); + MFC_CORE_WRITEL(offset, MFC_REG_E_STREAM_BUFFER_OFFSET); + + if (IS_MULTI_MODE(ctx) && + !(ctx->dev->debugfs.feature_option & MFC_OPTION_STREAM_COPY_DISABLE)) { + dma_addr_t tile1_addr = 0; + unsigned int tile0_size = 0; + unsigned int tile1_size = 0; + + tile0_size = ALIGN(size / 2, 16); + tile1_addr = addr + tile0_size; + tile1_size = (size > tile0_size) ? size - tile0_size : 0; + + MFC_CORE_DMA_WRITEL(tile1_addr, MFC_REG_E_TILE1_STREAM_BUFFER_ADDR); /* 16B align */ + MFC_CORE_WRITEL(tile1_size, MFC_REG_E_TILE1_STREAM_BUFFER_SIZE); + } + + mfc_ctx_debug(2, "[BUFINFO] set dst index: %d, addr: 0x%08llx\n", index, addr); + mfc_ctx_debug(2, "[STREAM] buf_size: %u, offset: %d\n", size, offset); + + return 0; +} + +void mfc_core_get_enc_frame_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + dma_addr_t addr[], int num_planes) +{ + dma_addr_t enc_recon_y_addr, enc_recon_c_addr; + int i, addr_offset; + + addr_offset = MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR; + + for (i = 0; i < num_planes; i++) + addr[i] = MFC_CORE_DMA_READL(addr_offset + (i * 4)); + + enc_recon_y_addr = MFC_CORE_DMA_READL(MFC_REG_E_RECON_LUMA_DPB_ADDR); + enc_recon_c_addr = MFC_CORE_DMA_READL(MFC_REG_E_RECON_CHROMA_DPB_ADDR); + + mfc_ctx_debug(2, "[MEMINFO] recon y: %#llx c: %#llx\n", + enc_recon_y_addr, enc_recon_c_addr); +} + +void mfc_core_set_enc_stride(struct mfc_core *core, struct mfc_ctx *ctx) +{ + int i; + + for (i = 0; i < ctx->raw_buf.num_planes; i++) { + MFC_CORE_WRITEL(ctx->raw_buf.stride[i], + MFC_REG_E_SOURCE_FIRST_STRIDE + (i * 4)); + mfc_ctx_debug(2, "[FRAME] enc src plane[%d] stride: %d\n", + i, ctx->raw_buf.stride[i]); + } +} + void mfc_core_set_dynamic_dpb(struct mfc_core *core, struct mfc_ctx *ctx, struct mfc_buf *dst_mb) { diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h index 08f74bd56f3f..6042f3a8a6ba 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h @@ -116,6 +116,14 @@ MFC_CORE_READL(MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE + ((x) * 4)) #define mfc_core_get_mv_count() MFC_CORE_READL(MFC_REG_D_MIN_NUM_MV) #define mfc_core_get_inst_no() MFC_CORE_READL(MFC_REG_RET_INSTANCE_ID) +#define mfc_core_get_enc_dpb_count() MFC_CORE_READL(MFC_REG_E_NUM_DPB) +#define mfc_core_get_enc_scratch_size() MFC_CORE_READL(MFC_REG_E_MIN_SCRATCH_BUFFER_SIZE) +#define mfc_core_get_enc_luma_size() MFC_CORE_READL(MFC_REG_E_MIN_LUMA_DPB_SIZE) +#define mfc_core_get_enc_chroma_size() MFC_CORE_READL(MFC_REG_E_MIN_CHROMA_DPB_SIZE) +#define mfc_core_get_enc_strm_size() MFC_CORE_READL(MFC_REG_E_STREAM_SIZE) +#define mfc_core_get_enc_slice_type() (MFC_CORE_READL(MFC_REG_E_SLICE_TYPE) \ + & MFC_REG_E_SLICE_TYPE_MASK) +#define mfc_core_get_enc_pic_count() MFC_CORE_READL(MFC_REG_E_PICTURE_COUNT) #define mfc_core_get_sei_avail() MFC_CORE_READL(MFC_REG_D_SEI_AVAIL) #define mfc_core_get_sei_content_light() \ MFC_CORE_READL(MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI) @@ -209,6 +217,14 @@ #define mfc_core_get_dec_used_flag() (((unsigned long)(MFC_CORE_READL \ (MFC_REG_D_USED_DPB_FLAG_UPPER)) << 32) | \ MFC_CORE_READL(MFC_REG_D_USED_DPB_FLAG_LOWER)) +#define mfc_core_get_enc_idr_flag() \ + ((MFC_CORE_READL(MFC_REG_E_NAL_DONE_INFO) \ + >> MFC_REG_E_NAL_DONE_INFO_IDR_SHIFT) \ + & MFC_REG_E_NAL_DONE_INFO_IDR_MASK) +#define mfc_core_get_enc_comp_err() \ + ((MFC_CORE_READL(MFC_REG_E_NAL_DONE_INFO) \ + >> MFC_REG_E_NAL_DONE_INFO_COMP_ERR_SHIFT) \ + & MFC_REG_E_NAL_DONE_INFO_COMP_ERR_MASK) #define mfc_core_get_chroma_format() (MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ & MFC_REG_D_CHROMA_FORMAT_MASK) #define mfc_core_get_color_range() ((MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ @@ -257,6 +273,15 @@ static inline void mfc_core_dec_get_crop_info(struct mfc_core *core, dec->cr_bot = bottom; } +static inline void mfc_core_clear_enc_res_change(struct mfc_core *core) +{ + unsigned int reg = 0; + + reg = MFC_CORE_READL(MFC_REG_E_PARAM_CHANGE); + reg &= ~(0x7 << 6); + MFC_CORE_WRITEL(reg, MFC_REG_E_PARAM_CHANGE); +} + static inline void mfc_core_clear_roi_enable(struct mfc_core *core) { unsigned int reg = 0; @@ -276,6 +301,25 @@ static inline void mfc_core_update_tag(struct mfc_core *core, struct mfc_ctx *ct } } +static inline void mfc_core_set_enc_src_votf(struct mfc_core *core, int onoff) +{ + unsigned int reg = 0; + + reg = MFC_CORE_READL(MFC_REG_E_PARAM_CHANGE); + reg &= ~(0x3 << 18); + reg |= (onoff << 18); + MFC_CORE_WRITEL(reg, MFC_REG_E_PARAM_CHANGE); +} + +static inline void mfc_core_clear_enc_src_votf(struct mfc_core *core) +{ + unsigned int reg = 0; + + reg = MFC_CORE_READL(MFC_REG_E_PARAM_CHANGE); + reg &= ~(0x3 << 18); + MFC_CORE_WRITEL(reg, MFC_REG_E_PARAM_CHANGE); +} + static inline void mfc_core_set_migration_addr(struct mfc_core *core, struct mfc_ctx *ctx, dma_addr_t fw_addr, dma_addr_t common_ctx_addr) { @@ -311,10 +355,21 @@ unsigned int mfc_get_frame_error_type(struct mfc_ctx *ctx, unsigned int err); void mfc_core_set_dec_dpb_and_scratch(struct mfc_core_ctx *core_ctx, dma_addr_t scratch_addr); int mfc_core_set_dec_codec_buffers(struct mfc_core_ctx *core_ctx); +int mfc_core_set_enc_codec_buffers(struct mfc_core_ctx *core_ctx); + int mfc_core_set_dec_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, unsigned int start_num_byte, unsigned int buf_size); +void mfc_core_set_enc_frame_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, int num_planes); +int mfc_core_set_enc_stream_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf); + +void mfc_core_get_enc_frame_buffer(struct mfc_core *core, struct mfc_ctx *ctx, + dma_addr_t addr[], int num_planes); +void mfc_core_set_enc_stride(struct mfc_core *core, struct mfc_ctx *ctx); + void mfc_core_set_dynamic_dpb(struct mfc_core *core, struct mfc_ctx *ctx, struct mfc_buf *dst_vb); diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c index 127d19c4d1cb..6270d22d3806 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c @@ -16,6 +16,7 @@ #include "mfc_core_cmd.h" #include "mfc_core_hw_reg_api.h" +#include "mfc_core_enc_param.h" #include "base/mfc_queue.h" #include "base/mfc_utils.h" @@ -412,3 +413,129 @@ int mfc_core_run_dec_last_frames(struct mfc_core *core, struct mfc_ctx *ctx) return 0; } + +int mfc_core_run_enc_init(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_buf *dst_mb; + int ret; + + if (!(ctx->stream_op_mode == MFC_OP_TWO_MODE1 && core->id == MFC_CORE_SUB)) { + dst_mb = mfc_get_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_SET_USED); + if (!dst_mb) { + mfc_ctx_debug(2, "no dst buffers\n"); + return -EAGAIN; + } + + mfc_core_set_enc_stream_buffer(core, ctx, dst_mb); + mfc_ctx_debug(2, "[BUFINFO] Header addr: 0x%08llx\n", dst_mb->addr[0][0]); + } + + mfc_core_set_enc_stride(core, ctx); + + mfc_clean_core_ctx_int_flags(core->core_ctx[ctx->num]); + + ret = mfc_core_cmd_enc_seq_header(core, ctx); + return ret; +} + +int mfc_core_run_enc_frame(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_buf *dst_mb; + struct mfc_buf *src_mb; + struct mfc_raw_info *raw; + unsigned int index; + int last_frame = 0; + + raw = &ctx->raw_buf; + + /* Get the next source buffer */ + src_mb = mfc_get_buf(ctx, &core_ctx->src_buf_queue, MFC_BUF_SET_USED); + if (!src_mb) { + mfc_debug(2, "no src buffers\n"); + return -EAGAIN; + } + + if (src_mb->num_valid_bufs > 0) { + /* last image in a buffer container */ + if (src_mb->next_index == (src_mb->num_valid_bufs - 1)) { + mfc_debug(4, "[BUFCON] last image in a container\n"); + last_frame = __mfc_check_last_frame(core_ctx, src_mb); + } + } else { + last_frame = __mfc_check_last_frame(core_ctx, src_mb); + } + + if (mfc_check_mb_flag(src_mb, MFC_FLAG_ENC_SRC_FAKE)) { + enc->fake_src = 1; + mfc_debug(2, "src is fake\n"); + } + + index = src_mb->vb.vb2_buf.index; + if (mfc_check_mb_flag(src_mb, MFC_FLAG_EMPTY_DATA)) { + enc->empty_data = 1; + mfc_debug(2, "[FRAME] src is empty data\n"); + mfc_core_set_enc_frame_buffer(core, ctx, 0, raw->num_planes); + } else { + mfc_core_set_enc_frame_buffer(core, ctx, src_mb, raw->num_planes); + } + + dst_mb = mfc_get_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_SET_USED); + if (!dst_mb) { + mfc_debug(2, "no dst buffers\n"); + return -EAGAIN; + } + + mfc_debug(2, "nal start : src index from src_buf_queue:%d\n", + src_mb->vb.vb2_buf.index); + mfc_debug(2, "nal start : dst index from dst_buf_queue:%d\n", + dst_mb->vb.vb2_buf.index); + + mfc_core_set_enc_stream_buffer(core, ctx, dst_mb); + + if (call_bop(ctx, core_set_buf_ctrls, core, ctx, &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_set_buf_ctrls\n"); + + mfc_clean_core_ctx_int_flags(core_ctx); + + if (IS_H264_ENC(ctx)) + mfc_core_set_aso_slice_order_h264(core, ctx); + + mfc_core_set_slice_mode(core, ctx); + mfc_core_set_enc_config_qp(core, ctx); + mfc_core_set_enc_ts_delta(core, ctx); + + mfc_core_cmd_enc_one_frame(core, ctx, last_frame); + + return 0; +} + +int mfc_core_run_enc_last_frames(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_buf *dst_mb = NULL; + struct mfc_raw_info *raw; + + raw = &ctx->raw_buf; + + if (IS_SWITCH_SINGLE_MODE(ctx) && core->id == ctx->op_core_num[MFC_CORE_SUB]) { + mfc_ctx_info("last-frame of subcore doesn't have dst buffer\n"); + } else { + dst_mb = mfc_get_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_SET_USED); + if (!dst_mb) { + mfc_ctx_debug(2, "no dst buffers set to zero\n"); + + if (mfc_is_enc_bframe(ctx)) + mfc_ctx_info("B frame encoding doesn't have dst buffer\n"); + } + } + + mfc_ctx_debug(2, "Set address zero for all planes\n"); + mfc_core_set_enc_frame_buffer(core, ctx, 0, raw->num_planes); + mfc_core_set_enc_stream_buffer(core, ctx, dst_mb); + + mfc_clean_core_ctx_int_flags(core->core_ctx[ctx->num]); + mfc_core_cmd_enc_one_frame(core, ctx, 1); + + return 0; +} diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h index 6b9c9ef91e47..410c2aadcf5d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h @@ -27,4 +27,9 @@ int mfc_core_run_wakeup(struct mfc_core *core); int mfc_core_run_dec_init(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_run_dec_frame(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_run_dec_last_frames(struct mfc_core *core, struct mfc_ctx *ctx); + +int mfc_core_run_enc_init(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_run_enc_frame(struct mfc_core *core, struct mfc_ctx *ctx); +int mfc_core_run_enc_last_frames(struct mfc_core *core, struct mfc_ctx *ctx); + #endif /* __MFC_CORE_RUN_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035706epcas5p4530de9edacfc86c0ae1ab9de2d2b0695@epcas5p4.samsung.com>]
* [PATCH 27/29] media: mfc: Add H.264 encoder support [not found] ` <CGME20250930035706epcas5p4530de9edacfc86c0ae1ab9de2d2b0695@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Register H.264 format and V4L2/VB2 headers. - Initialize encoder context, queues, and defaults. - Add buffer‑control handling (layers, ROI, frame‑rate, drop, profile/level) and parse DT properties. - Register encoder ioctl ops, set up QoS table, and extend debugfs. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_format.h | 8 + .../media/platform/samsung/exynos-mfc/mfc.c | 193 ++++++- .../platform/samsung/exynos-mfc/mfc_core.c | 26 + .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 321 +++++++++++ .../samsung/exynos-mfc/mfc_core_isr.c | 518 +++++++++++++++++- .../samsung/exynos-mfc/mfc_core_sync.c | 58 +- .../platform/samsung/exynos-mfc/mfc_debugfs.c | 17 +- 7 files changed, 1116 insertions(+), 25 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h index 0d48f2373e8d..e8573d6b6005 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h @@ -263,6 +263,14 @@ static struct mfc_fmt mfc_formats[] = { .num_planes = 1, .mem_planes = 1, }, + { + .name = "ENC H264", + .fourcc = V4L2_PIX_FMT_H264, + .codec_mode = MFC_REG_CODEC_H264_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, }; #endif /* __MFC_FORMAT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc.c b/drivers/media/platform/samsung/exynos-mfc/mfc.c index db17448eae13..68cba41b45da 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc.c @@ -23,6 +23,8 @@ #include "mfc_dec_v4l2.h" #include "mfc_dec_vb2.h" +#include "mfc_enc_v4l2.h" +#include "mfc_enc_vb2.h" #include "mfc_rm.h" #include "mfc_debugfs.h" @@ -228,6 +230,107 @@ static int __mfc_init_dec_ctx(struct mfc_ctx *ctx) return ret; } +static void __mfc_deinit_enc_ctx(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + + mfc_delete_queue(&ctx->src_buf_ready_queue); + mfc_delete_queue(&ctx->dst_buf_queue); + mfc_delete_queue(&ctx->ref_buf_queue); + mfc_delete_queue(&ctx->err_buf_queue); + mfc_delete_queue(&ctx->meminfo_inbuf_q); + mfc_delete_queue(&ctx->meminfo_outbuf_q); + + mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_svc); + mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_roi); + + kfree(enc); +} + +static int __mfc_init_enc_ctx(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc; + struct mfc_enc_params *p; + int ret = 0; + int i; + + enc = kzalloc(sizeof(*enc), GFP_KERNEL); + if (!enc) + return -ENOMEM; + + ctx->enc_priv = enc; + ctx->user_prio = -1; + + mfc_create_queue(&ctx->src_buf_ready_queue); + mfc_create_queue(&ctx->dst_buf_queue); + mfc_create_queue(&ctx->ref_buf_queue); + mfc_create_queue(&ctx->err_buf_queue); + mfc_create_queue(&ctx->meminfo_inbuf_q); + mfc_create_queue(&ctx->meminfo_outbuf_q); + + for (i = 0; i < MFC_MAX_BUFFERS; i++) { + INIT_LIST_HEAD(&ctx->src_ctrls[i]); + INIT_LIST_HEAD(&ctx->dst_ctrls[i]); + } + bitmap_zero(ctx->src_ctrls_avail, MFC_MAX_BUFFERS); + bitmap_zero(ctx->dst_ctrls_avail, MFC_MAX_BUFFERS); + + ctx->type = MFCINST_ENCODER; + ctx->c_ops = &mfc_ctrls_ops; + ctx->b_ops = &mfc_bufs_ops; + + mfc_enc_set_default_format(ctx); + mfc_rate_reset_framerate(ctx); + + ctx->qos_ratio = 100; + + /* disable IVF header by default (VP8, VP9) */ + p = &enc->params; + p->ivf_header_disable = 1; + + INIT_LIST_HEAD(&ctx->bitrate_list); + INIT_LIST_HEAD(&ctx->src_ts.ts_list); + + enc->sh_handle_svc.fd = -1; + enc->sh_handle_roi.fd = -1; + enc->sh_handle_svc.data_size = sizeof(struct temporal_layer_info); + enc->sh_handle_roi.data_size = sizeof(struct mfc_enc_roi_info); + + /* Init videobuf2 queue for OUTPUT */ + ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + ctx->vq_src.drv_priv = ctx; + ctx->vq_src.buf_struct_size = (unsigned int)sizeof(struct mfc_buf); + ctx->vq_src.io_modes = VB2_USERPTR | VB2_DMABUF; + ctx->vq_src.ops = mfc_get_enc_vb2_ops(); + ctx->vq_src.mem_ops = mfc_mem_ops(); + ctx->vq_src.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + ret = vb2_queue_init(&ctx->vq_src); + if (ret) { + mfc_ctx_err("Failed to initialize videobuf2 queue(output)\n"); + goto fail_enc_init; + } + + /* Init videobuf2 queue for CAPTURE */ + ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + ctx->vq_dst.drv_priv = ctx; + ctx->vq_dst.buf_struct_size = (unsigned int)sizeof(struct mfc_buf); + ctx->vq_dst.io_modes = VB2_USERPTR | VB2_DMABUF; + ctx->vq_dst.ops = mfc_get_enc_vb2_ops(); + ctx->vq_dst.mem_ops = mfc_mem_ops(); + ctx->vq_dst.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + ret = vb2_queue_init(&ctx->vq_dst); + if (ret) { + mfc_ctx_err("Failed to initialize videobuf2 queue(capture)\n"); + goto fail_enc_init; + } + + return 0; + +fail_enc_init: + __mfc_deinit_enc_ctx(ctx); + return 0; +} + /* Open an MFC node */ static int mfc_open(struct file *file) { @@ -339,6 +442,7 @@ static int mfc_open(struct file *file) ret = __mfc_init_dec_ctx(ctx); dev->num_dec_inst++; } else { + ret = __mfc_init_enc_ctx(ctx); dev->num_enc_inst++; } if (ret) @@ -351,8 +455,8 @@ static int mfc_open(struct file *file) /* idle mode */ spin_lock_init(&dev->idle_bits_lock); } - if (mfc_is_decoder_node(node)) - ret = call_cop(ctx, init_ctx_ctrls, ctx); + + ret = call_cop(ctx, init_ctx_ctrls, ctx); if (ret) { mfc_ctx_err("failed in init_ctx_ctrls\n"); goto err_ctx_init; @@ -449,12 +553,10 @@ static int mfc_release(struct file *file) * So, we need to performed stop_streaming * before instance de-init(CLOSE_INSTANCE). */ - if (ctx->type == MFCINST_DECODER) { - vb2_queue_release(&ctx->vq_src); - vb2_queue_release(&ctx->vq_dst); + vb2_queue_release(&ctx->vq_src); + vb2_queue_release(&ctx->vq_dst); - call_cop(ctx, cleanup_ctx_ctrls, ctx); - } + call_cop(ctx, cleanup_ctx_ctrls, ctx); ret = mfc_rm_instance_deinit(dev, ctx); if (ret) { @@ -471,6 +573,7 @@ static int mfc_release(struct file *file) __mfc_deinit_dec_ctx(ctx); dev->num_dec_inst--; } else if (ctx->type == MFCINST_ENCODER) { + __mfc_deinit_enc_ctx(ctx); dev->num_enc_inst--; } @@ -609,6 +712,12 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) of_property_read_u32_array (np, "static_info_dec", &pdata->static_info_dec.support, 2); + of_property_read_u32_array + (np, "color_aspect_enc", + &pdata->color_aspect_enc.support, 2); + of_property_read_u32_array + (np, "static_info_enc", + &pdata->static_info_enc.support, 2); of_property_read_u32_array (np, "vp9_stride_align", &pdata->vp9_stride_align.support, 2); @@ -618,6 +727,30 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) of_property_read_u32_array (np, "wait_fw_status", &pdata->wait_fw_status.support, 2); + of_property_read_u32_array + (np, "average_qp", + &pdata->average_qp.support, 2); + of_property_read_u32_array + (np, "mv_search_mode", + &pdata->mv_search_mode.support, 2); + of_property_read_u32_array + (np, "enc_idr_flag", + &pdata->enc_idr_flag.support, 2); + of_property_read_u32_array + (np, "min_quality_mode", + &pdata->min_quality_mode.support, 2); + of_property_read_u32_array + (np, "enc_capability", + &pdata->enc_capability.support, 2); + of_property_read_u32_array + (np, "enc_ts_delta", + &pdata->enc_ts_delta.support, 2); + of_property_read_u32_array + (np, "wfd_rc_mode", + &pdata->wfd_rc_mode.support, 2); + of_property_read_u32_array + (np, "max_i_frame_size", + &pdata->max_i_frame_size.support, 2); of_property_read_u32_array (np, "hevc_pic_output_flag", &pdata->hevc_pic_output_flag.support, 2); @@ -630,10 +763,14 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) /* Formats */ of_property_read_u32(np, "support_422", &pdata->support_422); + of_property_read_u32(np, "support_rgb", &pdata->support_rgb); /* Resolution */ of_property_read_u32(np, "support_check_res", &pdata->support_check_res); + /* HWAPG */ + of_property_read_u32(np, "support_hwapg", &pdata->support_hwapg); + /* HWACG */ of_property_read_u32(np, "support_hwacg", &pdata->support_hwacg); @@ -643,6 +780,39 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) /* output buffer Q framerate */ of_property_read_u32(np, "display_framerate", &pdata->display_framerate); + /* Encoder default parameter */ + of_property_read_u32(np, "enc_param_num", &pdata->enc_param_num); + if (pdata->enc_param_num) { + of_property_read_u32_array + (np, "enc_param_addr", + pdata->enc_param_addr, pdata->enc_param_num); + of_property_read_u32_array + (np, "enc_param_val", + pdata->enc_param_val, pdata->enc_param_num); + } + + /* MFC bandwidth information */ + of_property_read_u32_array + (np, "bw_enc_h264", + &pdata->mfc_bw_info.bw_enc_h264.peak, 3); + of_property_read_u32_array + (np, "bw_enc_hevc", + &pdata->mfc_bw_info.bw_enc_hevc.peak, 3); + of_property_read_u32_array + (np, "bw_enc_hevc_10bit", + &pdata->mfc_bw_info.bw_enc_hevc_10bit.peak, 3); + of_property_read_u32_array + (np, "bw_enc_vp8", + &pdata->mfc_bw_info.bw_enc_vp8.peak, 3); + of_property_read_u32_array + (np, "bw_enc_vp9", + &pdata->mfc_bw_info.bw_enc_vp9.peak, 3); + of_property_read_u32_array + (np, "bw_enc_vp9_10bit", + &pdata->mfc_bw_info.bw_enc_vp9_10bit.peak, 3); + of_property_read_u32_array + (np, "bw_enc_mpeg4", + &pdata->mfc_bw_info.bw_enc_mpeg4.peak, 3); of_property_read_u32_array (np, "bw_dec_h264", &pdata->mfc_bw_info.bw_dec_h264.peak, 3); @@ -745,6 +915,11 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) of_property_read_u32(np, "scheduler", &pdata->scheduler); of_property_read_u32(np, "pbs_num_prio", &pdata->pbs_num_prio); + /* Encoder RGB CSC formula by VUI from F/W */ + of_property_read_u32(np, "enc_rgb_csc_by_fw", &pdata->enc_rgb_csc_by_fw); + + of_property_read_u32(np, "support_enc_mode1", &pdata->support_enc_mode1); + of_property_read_u32(np, "support_mv_hevc", &pdata->support_mv_hevc); return 0; @@ -771,7 +946,7 @@ static struct video_device *__mfc_video_device_register if (IS_DEC_NODE(node_num)) vfd->ioctl_ops = mfc_get_dec_v4l2_ioctl_ops(); else if (IS_ENC_NODE(node_num)) - vfd->ioctl_ops = NULL; + vfd->ioctl_ops = mfc_get_enc_v4l2_ioctl_ops(); vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; @@ -1126,7 +1301,7 @@ static const struct dev_pm_ops mfc_pm_ops = { struct mfc_ctx_buf_size mfc_ctx_buf_size = { .dev_ctx = PAGE_ALIGN(0x7800), /* 30KB */ .h264_dec_ctx = PAGE_ALIGN(0x200000), /* 1.6MB */ - .av1_dec_ctx = PAGE_ALIGN(0x19000), /* 100KB */ + .av1_dec_ctx = PAGE_ALIGN(0x19000), /* 100KB */ .other_dec_ctx = PAGE_ALIGN(0xF000), /* 60KB */ .h264_enc_ctx = PAGE_ALIGN(0x19000), /* 100KB */ .hevc_enc_ctx = PAGE_ALIGN(0xC800), /* 50KB */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c index aad3273ce2ba..2d9c2ffef0d4 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core.c @@ -29,6 +29,7 @@ #include "mfc_core_ops.h" #include "mfc_core_isr.h" #include "mfc_dec_v4l2.h" +#include "mfc_enc_v4l2.h" #include "mfc_debugfs.h" #include "mfc_core_hwlock.h" @@ -79,6 +80,8 @@ static int __mfc_core_parse_mfc_qos_platdata(struct device_node *np, of_property_read_u32(np_qos, "mo_value", &qosdata->mo_value); of_property_read_u32(np_qos, "mo_10bit_value", &qosdata->mo_10bit_value); + of_property_read_u32(np_qos, "mo_uhd_enc60_value", + &qosdata->mo_uhd_enc60_value); of_property_read_u32(np_qos, "time_fw", &qosdata->time_fw); of_property_read_string(np_qos, "bts_scen", &qosdata->name); @@ -214,6 +217,8 @@ static int __mfc_core_parse_dt(struct device_node *np, struct mfc_core *core) /* QoS */ of_property_read_u32(np, "num_default_qos_steps", &pdata->num_default_qos_steps); + of_property_read_u32(np, "num_encoder_qos_steps", + &pdata->num_encoder_qos_steps); of_property_read_u32(np, "max_mb", &pdata->max_mb); of_property_read_u32(np, "max_hw_mb", &pdata->max_hw_mb); of_property_read_u32(np, "mfc_freq_control", &pdata->mfc_freq_control); @@ -233,6 +238,18 @@ static int __mfc_core_parse_dt(struct device_node *np, struct mfc_core *core) core); } + pdata->encoder_qos_table = devm_kzalloc(core->device, + sizeof(struct mfc_qos) * + pdata->num_encoder_qos_steps, + GFP_KERNEL); + for (i = 0; i < pdata->num_encoder_qos_steps; i++) { + snprintf(node_name, sizeof(node_name), "mfc_e_qos_variant_%d", + i); + __mfc_core_parse_mfc_qos_platdata(np, node_name, + &pdata->encoder_qos_table[i], + core); + } + /* performance boost mode */ pdata->qos_boost_table = devm_kzalloc(core->device, sizeof(struct mfc_qos_boost), @@ -466,6 +483,15 @@ static int mfc_core_probe(struct platform_device *pdev) core->core_pdata->default_qos_table[i].freq_mif, core->core_pdata->default_qos_table[i].name, core->core_pdata->default_qos_table[i].bts_scen_idx); + mfc_core_info("[QoS]-------------------Encoder only table\n"); + for (i = 0; i < core->core_pdata->num_encoder_qos_steps; i++) + mfc_core_info + ("[QoS] table[%d] mfc: %d, int: %d, mif: %d, bts_scen: %s(%d)\n", + i, core->core_pdata->encoder_qos_table[i].freq_mfc, + core->core_pdata->encoder_qos_table[i].freq_int, + core->core_pdata->encoder_qos_table[i].freq_mif, + core->core_pdata->encoder_qos_table[i].name, + core->core_pdata->encoder_qos_table[i].bts_scen_idx); #if IS_ENABLED(CONFIG_SAMSUNG_IOMMU) ret = samsung_iommu_register_fault_handler(core->device, mfc_core_sysmmu_fault_handler, diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c index 38f09d6ef2dd..cc0a20bea33a 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c @@ -11,6 +11,250 @@ #include "mfc_core_reg_api.h" +static void __mfc_enc_store_buf_ctrls_temporal_svc(int id, + struct mfc_enc_params *p, + struct temporal_layer_info + *temporal_LC) +{ + unsigned int num_layer = temporal_LC->temporal_layer_count; + int i; + + switch (id) { + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH: + p->codec.h264.num_hier_layer = num_layer & 0x7; + for (i = 0; i < (num_layer & 0x7); i++) + p->codec.h264.hier_bit_layer[i] = + temporal_LC->temporal_layer_bitrate[i]; + break; + default: + break; + } +} + +static void __mfc_core_enc_set_buf_ctrls_temporal_svc(struct mfc_core *core, + struct mfc_ctx *ctx, + struct mfc_buf_ctrl + *buf_ctrl) +{ + struct mfc_enc *enc = ctx->enc_priv; + unsigned int value = 0, value2 = 0; + struct temporal_layer_info temporal_LC; + unsigned int i; + struct mfc_enc_params *p = &enc->params; + + if (buf_ctrl->id + == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH) { + memcpy(&temporal_LC, + enc->sh_handle_svc.vaddr, + sizeof(struct temporal_layer_info)); + + if ((temporal_LC.temporal_layer_count & 0x7) < 1) { + /* clear NUM_T_LAYER_CHANGE */ + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value &= ~BIT(10); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + mfc_ctx_err + ("[HIERARCHICAL] layer count is invalid : %d\n", + temporal_LC.temporal_layer_count); + return; + } + + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value &= ~(0x3 << 21); + + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + + /* Store temporal layer information */ + __mfc_enc_store_buf_ctrls_temporal_svc(buf_ctrl->id, p, + &temporal_LC); + + /* enable RC_BIT_RATE_CHANGE */ + value = MFC_CORE_READL(buf_ctrl->flag_addr); + if (temporal_LC.temporal_layer_bitrate[0] > 0 || + p->hier_bitrate_ctrl) + /* set RC_BIT_RATE_CHANGE */ + value |= BIT(2); + else + /* clear RC_BIT_RATE_CHANGE */ + value &= ~BIT(2); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + + mfc_ctx_debug(3, + "[HIERARCHICAL] layer count %d, E_PARAM_CHANGE %#x\n", + temporal_LC.temporal_layer_count & 0x7, value); + + value = MFC_CORE_READL(MFC_REG_E_NUM_T_LAYER); + buf_ctrl->old_val2 = value; + value &= ~(0x7); + value |= (temporal_LC.temporal_layer_count & 0x7); + value &= ~BIT(8); + value |= (p->hier_bitrate_ctrl & 0x1) << 8; + MFC_CORE_WRITEL(value, MFC_REG_E_NUM_T_LAYER); + mfc_ctx_debug(3, "[HIERARCHICAL] E_NUM_T_LAYER %#x\n", value); + for (i = 0; i < (temporal_LC.temporal_layer_count & 0x7); i++) { + mfc_ctx_debug(3, + "[HIERARCHICAL] layer bitrate[%d] %d (FW ctrl: %d)\n", + i, temporal_LC.temporal_layer_bitrate[i], + p->hier_bitrate_ctrl); + MFC_CORE_WRITEL(temporal_LC.temporal_layer_bitrate[i], + buf_ctrl->addr + i * 4); + } + /* priority change */ + if (IS_H264_ENC(ctx)) { + value = 0; + value2 = 0; + for (i = 0; i < (p->codec.h264.num_hier_layer & 0x07); + i++) { + if (i <= 4) + value |= + ((p->codec.h264.base_priority & 0x3F) + i) + << (6 * i); + else + value2 |= + ((p->codec.h264.base_priority & 0x3F) + i) + << (6 * (i - 5)); + } + MFC_CORE_WRITEL(value, + MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_CORE_WRITEL(value2, + MFC_REG_E_H264_HD_SVC_EXTENSION_1); + mfc_ctx_debug(3, + "[HIERARCHICAL] EXTENSION0 %#x, EXTENSION1 %#x\n", + value, value2); + + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value |= BIT(12); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + mfc_ctx_debug(3, "[HIERARCHICAL] E_PARAM_CHANGE %#x\n", + value); + } + } + + /* temproral layer priority */ + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY) { + value = MFC_CORE_READL(MFC_REG_E_H264_HD_SVC_EXTENSION_0); + buf_ctrl->old_val |= value & 0x3FFFFFC0; + value &= ~(0x3FFFFFC0); + value2 = MFC_CORE_READL(MFC_REG_E_H264_HD_SVC_EXTENSION_1); + buf_ctrl->old_val2 = value2 & 0x0FFF; + value2 &= ~(0x0FFF); + for (i = 0; i < (p->codec.h264.num_hier_layer & 0x07); i++) { + if (i <= 4) + value |= + ((buf_ctrl->val & 0x3F) + i) << (6 * i); + else + value2 |= + ((buf_ctrl->val & 0x3F) + + i) << (6 * (i - 5)); + } + MFC_CORE_WRITEL(value, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_CORE_WRITEL(value2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); + mfc_ctx_debug(3, + "[HIERARCHICAL] EXTENSION0 %#x, EXTENSION1 %#x\n", + value, value2); + } +} + +static void __mfc_core_enc_set_buf_ctrls_exception(struct mfc_core *core, + struct mfc_ctx *ctx, + struct mfc_buf_ctrl + *buf_ctrl) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int value = 0; + + /* temporal layer setting */ + __mfc_core_enc_set_buf_ctrls_temporal_svc(core, ctx, buf_ctrl); + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_MARK_LTR) { + value = MFC_CORE_READL(MFC_REG_E_H264_NAL_CONTROL); + buf_ctrl->old_val2 = (value >> 8) & 0x7; + value &= ~(0x7 << 8); + value |= (buf_ctrl->val & 0x7) << 8; + MFC_CORE_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); + } + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_USE_LTR) { + value = MFC_CORE_READL(MFC_REG_E_H264_NAL_CONTROL); + buf_ctrl->old_val2 = (value >> 11) & 0xF; + value &= ~GENMASK(14, 11); + value |= (buf_ctrl->val & 0xF) << 11; + MFC_CORE_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH) { + value = MFC_CORE_READL(MFC_REG_E_GOP_CONFIG2); + buf_ctrl->old_val |= (value << 16) & 0x3FFF0000; + value &= ~(0x3FFF); + value |= (buf_ctrl->val >> 16) & 0x3FFF; + MFC_CORE_WRITEL(value, MFC_REG_E_GOP_CONFIG2); + } + + /* PROFILE & LEVEL have to be set up together */ + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { + value = MFC_CORE_READL(MFC_REG_E_PICTURE_PROFILE); + buf_ctrl->old_val |= (value & 0x000F) << 8; + value &= ~(0x000F); + value |= p->codec.h264.profile & 0x000F; + MFC_CORE_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); + p->codec.h264.level = buf_ctrl->val; + } + + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { + value = MFC_CORE_READL(MFC_REG_E_PICTURE_PROFILE); + buf_ctrl->old_val |= value & 0xFF00; + value &= ~(0x00FF << 8); + value |= (p->codec.h264.level << 8) & 0xFF00; + MFC_CORE_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); + p->codec.h264.profile = buf_ctrl->val; + } + + /* set the ROI buffer DVA */ + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_ROI_CONTROL) { + MFC_CORE_DMA_WRITEL(enc->roi_buf[buf_ctrl->old_val2].daddr, + MFC_REG_E_ROI_BUFFER_ADDR); + mfc_ctx_debug(3, "[ROI] buffer[%d] addr %#llx, QP val: %#x\n", + buf_ctrl->old_val2, + enc->roi_buf[buf_ctrl->old_val2].daddr, + buf_ctrl->val); + } + + /* set frame rate change with delta */ + if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH) { + p->rc_frame_delta = p->rc_framerate_res / buf_ctrl->val; + value = MFC_CORE_READL(buf_ctrl->addr); + value &= ~(buf_ctrl->mask << buf_ctrl->shft); + value |= + ((p->rc_frame_delta & buf_ctrl->mask) << buf_ctrl->shft); + MFC_CORE_WRITEL(value, buf_ctrl->addr); + } + + /* set drop control */ + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_DROP_CONTROL) { + p->rc_frame_delta = mfc_enc_get_ts_delta(ctx); + value = MFC_CORE_READL(MFC_REG_E_RC_FRAME_RATE); + value &= ~(0xFFFF); + value |= (p->rc_frame_delta & 0xFFFF); + MFC_CORE_WRITEL(value, MFC_REG_E_RC_FRAME_RATE); + if (ctx->src_ts.ts_last_interval) + mfc_ctx_debug(3, + "[DROPCTRL] fps %d -> %ld, delta: %d, reg: %#x\n", + p->rc_framerate, + USEC_PER_SEC / + ctx->src_ts.ts_last_interval, + p->rc_frame_delta, value); + else + mfc_ctx_debug(3, + "[DROPCTRL] fps %d -> 0, delta: %d, reg: %#x\n", + p->rc_framerate, p->rc_frame_delta, + value); + } + + /* store last config qp value in F/W */ + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_CONFIG_QP) + enc->config_qp = p->config_qp; +} + static int mfc_core_set_buf_ctrls(struct mfc_core *core, struct mfc_ctx *ctx, struct list_head *head) { @@ -51,6 +295,10 @@ static int mfc_core_set_buf_ctrls(struct mfc_core *core, if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG) ctx->stored_tag = buf_ctrl->val; + if (ctx->type == MFCINST_ENCODER) + __mfc_core_enc_set_buf_ctrls_exception(core, ctx, + buf_ctrl); + mfc_ctx_debug(6, "[CTRLS] Set buffer control id: 0x%08x, val: %d (%#x)\n", buf_ctrl->id, buf_ctrl->val, buf_ctrl->val); @@ -64,6 +312,7 @@ static int mfc_core_get_buf_ctrls(struct mfc_core *core, { struct mfc_buf_ctrl *buf_ctrl; struct mfc_dec *dec = ctx->dec_priv; + struct mfc_enc *enc = ctx->enc_priv; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -89,6 +338,10 @@ static int mfc_core_get_buf_ctrls(struct mfc_core *core, if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_FRAME_ERROR_TYPE) buf_ctrl->val = mfc_get_frame_error_type(ctx, value); + if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS) + if (enc) + buf_ctrl->val = !enc->in_slice; + mfc_ctx_debug(6, "[CTRLS] Get buffer control id: 0x%08x, val: %d (%#x)\n", buf_ctrl->id, buf_ctrl->val, buf_ctrl->val); @@ -97,6 +350,69 @@ static int mfc_core_get_buf_ctrls(struct mfc_core *core, return 0; } +static void __mfc_core_enc_recover_buf_ctrls_exception(struct mfc_core *core, + struct mfc_ctx *ctx, + struct mfc_buf_ctrl + *buf_ctrl) +{ + unsigned int value = 0; + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH) { + value = MFC_CORE_READL(MFC_REG_E_GOP_CONFIG2); + value &= ~(0x3FFF); + value |= (buf_ctrl->old_val >> 16) & 0x3FFF; + MFC_CORE_WRITEL(value, MFC_REG_E_GOP_CONFIG2); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { + value = MFC_CORE_READL(MFC_REG_E_PICTURE_PROFILE); + value &= ~(0x000F); + value |= (buf_ctrl->old_val >> 8) & 0x000F; + MFC_CORE_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { + value = MFC_CORE_READL(MFC_REG_E_PICTURE_PROFILE); + value &= ~(0xFF00); + value |= buf_ctrl->old_val & 0xFF00; + MFC_CORE_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY) { + MFC_CORE_WRITEL(buf_ctrl->old_val, + MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_CORE_WRITEL(buf_ctrl->old_val2, + MFC_REG_E_H264_HD_SVC_EXTENSION_1); + } + + if (buf_ctrl->id == + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH || + buf_ctrl->id == + V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH || + buf_ctrl->id == + V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH) { + MFC_CORE_WRITEL(buf_ctrl->old_val2, MFC_REG_E_NUM_T_LAYER); + /* clear RC_BIT_RATE_CHANGE */ + value = MFC_CORE_READL(buf_ctrl->flag_addr); + value &= ~BIT(2); + MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_MARK_LTR) { + value = MFC_CORE_READL(MFC_REG_E_H264_NAL_CONTROL); + value &= ~(0x7 << 8); + value |= (buf_ctrl->old_val2 & 0x7) << 8; + MFC_CORE_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); + } + + if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_USE_LTR) { + value = MFC_CORE_READL(MFC_REG_E_H264_NAL_CONTROL); + value &= ~GENMASK(14, 11); + value |= (buf_ctrl->old_val2 & 0xF) << 11; + MFC_CORE_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); + } +} + static int mfc_core_recover_buf_ctrls(struct mfc_core *core, struct mfc_ctx *ctx, struct list_head *head) @@ -125,6 +441,11 @@ static int mfc_core_recover_buf_ctrls(struct mfc_core *core, MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); } + /* Exception */ + if (ctx->type == MFCINST_ENCODER) + __mfc_core_enc_recover_buf_ctrls_exception(core, ctx, + buf_ctrl); + buf_ctrl->updated = 0; mfc_ctx_debug(6, "[CTRLS] Recover buffer control id: 0x%08x, old val: %d\n", diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c index aa2c0b618c19..1a3cf7e76e29 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c @@ -777,6 +777,9 @@ static void __mfc_handle_error_state(struct mfc_ctx *ctx, struct mfc_core_ctx *c /* Mark all src buffers as having an error */ mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_ready_queue); mfc_cleanup_queue(&ctx->buf_queue_lock, &core_ctx->src_buf_queue); + if (ctx->type == MFCINST_ENCODER) + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->ref_buf_queue); + /* Mark all NAL_Q buffers as having an error */ } void mfc_core_handle_error(struct mfc_core *core) @@ -885,6 +888,11 @@ static void __mfc_handle_frame_error(struct mfc_core *core, unsigned int index; enum vb2_buffer_state vb2_state; + if (ctx->type == MFCINST_ENCODER) { + mfc_info("Encoder Interrupt Error (err: %d)\n", mfc_get_err(err)); + return; + } + dec = ctx->dec_priv; if (!dec) { mfc_err("no mfc decoder to run\n"); @@ -1267,12 +1275,428 @@ static void __mfc_handle_frame(struct mfc_core *core, mfc_debug(2, "Assesing whether this context should be run again\n"); } -static inline void __mfc_handle_done_frame(struct mfc_core *core, - struct mfc_ctx *ctx, - unsigned int reason, - unsigned int err) +static void __mfc_handle_error_input(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_buf *mfc_buf = NULL; + int index; + + while (1) { + mfc_buf = mfc_get_del_buf(ctx, &ctx->err_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!mfc_buf) + break; + + index = mfc_buf->vb.vb2_buf.index; + + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_ctx_err("failed in core_recover_buf_ctrls\n"); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + mfc_ctx_info("find src buf(fd: %d) in err_queue\n", + mfc_buf->vb.vb2_buf.planes[0].m.fd); + mfc_clear_mb_flag(mfc_buf); + mfc_set_mb_flag(mfc_buf, MFC_FLAG_CONSUMED_ONLY); + vb2_buffer_done(&mfc_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } +} + +static void __mfc_handle_stream_copy_timestamp(struct mfc_ctx *ctx, struct mfc_buf *src_mb) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_buf *dst_mb; + u64 interval; + u64 start_timestamp; + u64 new_timestamp; + + start_timestamp = src_mb->vb.vb2_buf.timestamp; + interval = NSEC_PER_SEC / p->rc_framerate; + if (ctx->dev->debugfs.debug_ts == 1) + mfc_ctx_info("[BUFCON][TS] %dfps, start timestamp: %lld, base interval: %lld\n", + p->rc_framerate, start_timestamp, interval); + + new_timestamp = start_timestamp + (interval * src_mb->done_index); + if (ctx->dev->debugfs.debug_ts == 1) + mfc_ctx_info("[BUFCON][TS] new timestamp: %lld, interval: %lld\n", + new_timestamp, interval * src_mb->done_index); + + /* Get the destination buffer */ + dst_mb = mfc_get_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (dst_mb) + dst_mb->vb.vb2_buf.timestamp = new_timestamp; +} + +static void __mfc_handle_stream_input(struct mfc_core *core, struct mfc_ctx *ctx, + int consumed_only) { - __mfc_handle_frame(core, ctx, reason, err); + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_raw_info *raw; + struct mfc_buf *ref_mb, *src_mb; + dma_addr_t enc_addr[3] = { 0, 0, 0 }; + struct mfc_enc *enc = ctx->enc_priv; + int i, found_in_src_queue = 0; + unsigned int index; + + raw = &ctx->raw_buf; + + mfc_core_get_enc_frame_buffer(core, ctx, &enc_addr[0], raw->num_planes); + if (enc_addr[0] == 0) { + mfc_debug(3, "no encoded src\n"); + + if (enc->fake_src && enc->params.num_b_frame) { + mfc_change_state(core_ctx, MFCINST_FINISHING); + enc->fake_src = 0; + mfc_debug(2, "clear fake_src and change to FINISHING\n"); + } + + goto move_buf; + } + for (i = 0; i < raw->num_planes; i++) + mfc_debug(2, "[BUFINFO] ctx[%d] get src addr[%d]: 0x%08llx\n", + ctx->num, i, enc_addr[i]); + + if (ctx->multi_view_enable && + ctx->select_view == MFC_VIEW_ID_MAIN) { + mfc_debug(2, "not handling src_mb to reuse for VIEW_1\n"); + return; + } + + if (IS_BUFFER_BATCH_MODE(ctx)) { + src_mb = mfc_find_first_buf(ctx, &core_ctx->src_buf_queue, enc_addr[0]); + if (src_mb) { + found_in_src_queue = 1; + + __mfc_handle_stream_copy_timestamp(ctx, src_mb); + src_mb->done_index++; + mfc_debug(4, "[BUFCON] batch buf done_index: %d\n", src_mb->done_index); + + index = src_mb->vb.vb2_buf.index; + /* single buffer || last image in a buffer container */ + if (!src_mb->num_valid_bufs || + src_mb->done_index == src_mb->num_valid_bufs) { + if (consumed_only) { + mfc_clear_mb_flag(src_mb); + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + } + + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_recover_buf_ctrls\n"); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + src_mb = mfc_find_del_buf(ctx, + &core_ctx->src_buf_queue, + enc_addr[0]); + if (src_mb) { + for (i = 0; i < raw->num_planes; i++) + mfc_bufcon_put_daddr(ctx, src_mb, i); + vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + } + } + } else { + /* normal single buffer */ + src_mb = mfc_find_del_buf(ctx, &core_ctx->src_buf_queue, enc_addr[0]); + if (src_mb) { + found_in_src_queue = 1; + index = src_mb->vb.vb2_buf.index; + if (consumed_only) { + mfc_clear_mb_flag(src_mb); + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + } + + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_recover_buf_ctrls\n"); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + mfc_debug(3, "find src buf in src_queue\n"); + vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + } else { + mfc_debug(3, "no src buf in src_queue\n"); + ref_mb = mfc_find_del_buf(ctx, &ctx->ref_buf_queue, enc_addr[0]); + if (ref_mb) { + index = ref_mb->vb.vb2_buf.index; + if (consumed_only) { + mfc_clear_mb_flag(ref_mb); + mfc_set_mb_flag(ref_mb, MFC_FLAG_CONSUMED_ONLY); + } + + if (call_bop(ctx, core_recover_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_recover_buf_ctrls\n"); + + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, + &ctx->src_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + + mfc_debug(3, "find src buf in ref_queue\n"); + vb2_buffer_done(&ref_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + } else { + mfc_err("couldn't find src buffer\n"); + } + } + } + +move_buf: + /* move enqueued src buffer: src queue -> ref queue */ + if (!found_in_src_queue && core_ctx->state != MFCINST_FINISHING) { + mfc_get_move_buf_used(ctx, &ctx->ref_buf_queue, &core_ctx->src_buf_queue); + + mfc_debug(2, "enc src_buf_queue(%d) -> ref_buf_queue(%d)\n", + mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); + } +} + +static void __mfc_handle_stream_output(struct mfc_core *core, + struct mfc_ctx *ctx, + int slice_type, + unsigned int strm_size) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_buf *dst_mb; + unsigned int index, idr_flag = 1; + + if (strm_size == 0) { + mfc_ctx_debug(3, "no encoded dst (reuse)\n"); + return; + } + + if (ctx->select_view == MFC_VIEW_ID_MAIN && + MFC_FEATURE_SUPPORT(dev, dev->pdata->enc_idr_flag)) + enc->idr_flag = mfc_core_get_enc_idr_flag(); + idr_flag = enc->idr_flag; + + /* at least one more dest. buffers exist always */ + if (ctx->multi_view_enable && + ctx->select_view == MFC_VIEW_ID_MAIN) { + mfc_ctx_debug(2, "not handling dst_mb to reuse for VIEW_1\n"); + return; + } + + dst_mb = mfc_get_del_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) { + mfc_ctx_err("no dst buffers\n"); + return; + } + + mfc_ctx_debug(2, "[BUFINFO] ctx[%d] get dst addr: 0x%08llx\n", + ctx->num, dst_mb->addr[0][0]); + + mfc_clear_mb_flag(dst_mb); + dst_mb->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME); + switch (slice_type) { + case MFC_REG_E_SLICE_TYPE_I: + dst_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; + if (!(CODEC_HAS_IDR(ctx) && !idr_flag)) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_SYNC_FRAME); + mfc_ctx_debug(2, "[STREAM] syncframe IDR\n"); + } + break; + case MFC_REG_E_SLICE_TYPE_P: + dst_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; + break; + case MFC_REG_E_SLICE_TYPE_B: + dst_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; + break; + default: + dst_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; + break; + } + mfc_ctx_debug(2, "[STREAM] Slice type flag: %d\n", dst_mb->vb.flags); + + if (IS_MULTI_MODE(ctx) && + !(dev->debugfs.feature_option & MFC_OPTION_STREAM_COPY_DISABLE)) { + unsigned int tile0_size, tile1_size; + unsigned int size; + unsigned char *vaddr; + struct sg_table *sgt; + + tile0_size = MFC_CORE_READL(MFC_REG_E_TILE0_STREAM_SIZE); + tile1_size = MFC_CORE_READL(MFC_REG_E_TILE1_STREAM_SIZE); + + size = (unsigned int)vb2_plane_size(&dst_mb->vb.vb2_buf, 0); + size = ALIGN(size, STREAM_BUF_ALIGN); + + sgt = vb2_dma_sg_plane_desc(&dst_mb->vb.vb2_buf, 0); + dma_sync_sgtable_for_cpu(dev->device, sgt, DMA_BIDIRECTIONAL); + + vaddr = vb2_plane_vaddr(&dst_mb->vb.vb2_buf, 0); + if (!vaddr) + mfc_ctx_err("failed to get vaddr for copying stream\n"); + else + memmove(vaddr + tile0_size, vaddr + ALIGN(size / 2, 16), tile1_size); + + mfc_ctx_debug(3, "memmove done: %d + %d\n", tile0_size, tile1_size); + } + + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, strm_size); + mfc_rate_update_framerate(ctx); + + index = dst_mb->vb.vb2_buf.index; + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); +} + +static void __mfc_handle_stream_last_output(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_buf *dst_mb; + unsigned int index; + + /* at least one more dest. buffers exist always */ + dst_mb = mfc_get_del_buf(ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) { + mfc_ctx_err("no dst buffers\n"); + return; + } + + mfc_ctx_debug(2, "[BUFINFO] ctx[%d] get dst addr: 0x%08llx\n", + ctx->num, dst_mb->addr[0][0]); + + dst_mb->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | + V4L2_BUF_FLAG_PFRAME | + V4L2_BUF_FLAG_BFRAME); + + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, 0); + + index = dst_mb->vb.vb2_buf.index; + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, &ctx->dst_ctrls[index]) < 0) + mfc_ctx_err("failed in core_get_buf_ctrls\n"); + + mfc_ctx_debug(2, "[STREAM] update tag for last stream\n"); + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, ctx->stored_tag); + + vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); +} + +/* Handle frame encoding interrupt */ +static int __mfc_handle_stream(struct mfc_core *core, struct mfc_ctx *ctx, unsigned int reason) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_core *subcore; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + int slice_type, consumed_only = 0; + unsigned int strm_size; + unsigned int pic_count; + + slice_type = mfc_core_get_enc_slice_type(); + strm_size = mfc_core_get_enc_strm_size(); + pic_count = mfc_core_get_enc_pic_count(); + + mfc_debug(2, "[STREAM] encoded slice type: %d, size: %d, display order: %d\n", + slice_type, strm_size, pic_count); + + /* clear vOTF enable */ + mfc_core_clear_enc_src_votf(core); + + /* buffer full handling */ + if (enc->buf_full) { + core_ctx->prev_state = core_ctx->state; + mfc_change_state(core_ctx, MFCINST_ABORT_INST); + return 0; + } + if (core_ctx->state == MFCINST_RUNNING_BUF_FULL) + mfc_change_state(core_ctx, core_ctx->prev_state); + + /* set encoded frame type */ + if (ctx->select_view == MFC_VIEW_ID_MAIN) + enc->frame_type = slice_type; + ctx->sequence++; + + if (enc->in_slice) { + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) + core->sched->clear_work(core, core_ctx); + return 0; + } + + if (mfc_qos_mb_calculate(core, core_ctx, mfc_core_get_processing_cycle(), slice_type)) { + mfc_qos_on(core, ctx); + if (IS_TWO_MODE1(ctx)) { + subcore = mfc_get_sub_core(dev, ctx); + if (subcore) { + subcore->core_ctx[ctx->num]->dynamic_weight_level = + core_ctx->dynamic_weight_level; + mfc_qos_on(subcore, ctx); + } + } + } + + if (strm_size == 0 && !(enc->empty_data && reason == MFC_REG_R2H_CMD_COMPLETE_SEQ_RET)) { + mfc_debug(2, "[FRAME] dst buffer is not returned\n"); + consumed_only = 1; + } + + /* handle source buffer */ + __mfc_handle_stream_input(core, ctx, consumed_only); + + /* handle destination buffer */ + if (enc->empty_data && reason == MFC_REG_R2H_CMD_COMPLETE_SEQ_RET) { + enc->empty_data = 0; + mfc_debug(2, "[FRAME] handle EOS for empty data\n"); + __mfc_handle_stream_last_output(core, ctx); + } else { + __mfc_handle_stream_output(core, ctx, enc->frame_type, strm_size); + } + mfc_rate_update_bufq_framerate(ctx, MFC_TS_DST_DQ); + + /* handle error buffer */ + __mfc_handle_error_input(core, ctx); + + if (ctx->multi_view_enable) + ctx->select_view = (ctx->select_view + 1) % MFC_NUM_MULTI_VIEW; + + return 0; +} + +static inline int __mfc_handle_done_frame(struct mfc_core *core, + struct mfc_ctx *ctx, + unsigned int reason, + unsigned int err) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_enc *enc = NULL; + + if (ctx->type == MFCINST_DECODER) { + __mfc_handle_frame(core, ctx, reason, err); + } else if (ctx->type == MFCINST_ENCODER) { + enc = ctx->enc_priv; + if (reason == MFC_REG_R2H_CMD_SLICE_DONE_RET) { + core->preempt_core_ctx = ctx->num; + enc->buf_full = 0; + enc->in_slice = 1; + } else if (reason == MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET) { + mfc_err("stream buffer size(%d) isn't enough, (Bitrate: %d)\n", + mfc_core_get_enc_strm_size(), + MFC_CORE_RAW_READL(MFC_REG_E_RC_BIT_RATE)); + + core->preempt_core_ctx = ctx->num; + enc->buf_full = 1; + enc->in_slice = 0; + } else { + enc->buf_full = 0; + enc->in_slice = 0; + } + __mfc_handle_stream(core, ctx, reason); + } + + return 1; } /* Handle header decoder interrupt */ @@ -1387,13 +1811,82 @@ static int __mfc_handle_seq_dec(struct mfc_core *core, struct mfc_ctx *ctx) return 0; } +/* Handle header encoder interrupt */ +static int __mfc_handle_seq_enc(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_buf *dst_mb; + int ret, index; + + enc->header_size = mfc_core_get_enc_strm_size(); + mfc_debug(2, "[STREAM] encoded slice type: %d, header size: %d, display order: %d\n", + mfc_core_get_enc_slice_type(), enc->header_size, + mfc_core_get_enc_pic_count()); + + /* Initialize select_view */ + ctx->select_view = MFC_VIEW_ID_MAIN; + + if (!IS_NO_HEADER_GENERATE(ctx, p) && + !(ctx->stream_op_mode == MFC_OP_TWO_MODE1 && core->id == MFC_CORE_SUB)) { + dst_mb = mfc_get_del_buf + (ctx, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + if (!dst_mb) { + mfc_err("no dst buffers\n"); + return -EAGAIN; + } + + vb2_set_plane_payload + (&dst_mb->vb.vb2_buf, 0, mfc_core_get_enc_strm_size()); + + index = dst_mb->vb.vb2_buf.index; + if (call_bop(ctx, core_get_buf_ctrls, core, ctx, + &ctx->dst_ctrls[index]) < 0) + mfc_err("failed in core_get_buf_ctrls\n"); + call_cop(ctx, update_buf_val, ctx, &ctx->dst_ctrls[index], + V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, HEADER_TAG); + + vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); + } + + ctx->dpb_count = mfc_core_get_enc_dpb_count(); + ctx->scratch_buf_size = mfc_core_get_enc_scratch_size(); + ctx->min_dpb_size[0] = mfc_core_get_enc_luma_size(); + ctx->min_dpb_size[1] = mfc_core_get_enc_chroma_size(); + + /* If the ROI is enabled at SEQ_START, clear ROI_ENABLE bit */ + mfc_core_clear_roi_enable(core); + + if (core_ctx->codec_buffer_allocated) { + mfc_debug(2, "[DRC] previous codec buffer is exist\n"); + + mfc_release_codec_buffers(core_ctx); + } + + ret = mfc_alloc_codec_buffers(core_ctx); + if (ret) + mfc_err("Failed to allocate encoding buffers\n"); + + mfc_change_state(core_ctx, MFCINST_HEAD_PARSED); + + return 0; +} + static inline void __mfc_handle_nal_abort(struct mfc_core *core, struct mfc_ctx *ctx, unsigned int reason) { struct mfc_core_ctx *core_ctx = core->core_ctx[ctx->num]; + struct mfc_enc *enc = ctx->enc_priv; - mfc_change_state(core_ctx, MFCINST_ABORT); + if (ctx->type == MFCINST_ENCODER) { + mfc_change_state(core_ctx, MFCINST_RUNNING_BUF_FULL); + enc->buf_full = 0; + __mfc_handle_stream(core, ctx, reason); + } else { + mfc_change_state(core_ctx, MFCINST_ABORT); + } } irqreturn_t mfc_core_top_half_irq(int irq, void *priv) @@ -1479,11 +1972,20 @@ static int __mfc_irq_ctx(struct mfc_core *core, case MFC_REG_R2H_CMD_SLICE_DONE_RET: case MFC_REG_R2H_CMD_FIELD_DONE_RET: case MFC_REG_R2H_CMD_FRAME_DONE_RET: + case MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET: + return __mfc_handle_done_frame(core, ctx, reason, err); case MFC_REG_R2H_CMD_COMPLETE_SEQ_RET: - __mfc_handle_done_frame(core, ctx, reason, err); + if (ctx->type == MFCINST_ENCODER) { + __mfc_handle_stream(core, ctx, reason); + mfc_change_state(core_ctx, MFCINST_FINISHED); + } else if (ctx->type == MFCINST_DECODER) { + return __mfc_handle_done_frame(core, ctx, reason, err); + } break; case MFC_REG_R2H_CMD_SEQ_DONE_RET: - if (ctx->type == MFCINST_DECODER) + if (ctx->type == MFCINST_ENCODER) + __mfc_handle_seq_enc(core, ctx); + else if (ctx->type == MFCINST_DECODER) __mfc_handle_seq_dec(core, ctx); break; case MFC_REG_R2H_CMD_OPEN_INSTANCE_RET: diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c index e4b839eda2da..aedb3f56035e 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c @@ -30,7 +30,8 @@ static inline unsigned int __mfc_r2h_bit_mask(int cmd) R2H_BIT(MFC_REG_R2H_CMD_COMPLETE_SEQ_RET) | R2H_BIT(MFC_REG_R2H_CMD_SLICE_DONE_RET) | R2H_BIT(MFC_REG_R2H_CMD_INIT_BUFFERS_RET) | - R2H_BIT(MFC_REG_R2H_CMD_NAL_ABORT_RET)); + R2H_BIT(MFC_REG_R2H_CMD_NAL_ABORT_RET) | + R2H_BIT(MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET)); /* FIXME: Temporal mask for S3D SEI processing */ else if (cmd == MFC_REG_R2H_CMD_INIT_BUFFERS_RET) mask |= (R2H_BIT(MFC_REG_R2H_CMD_FIELD_DONE_RET) | @@ -311,6 +312,56 @@ static int __mfc_dec_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx) return is_ready; } +static int __mfc_enc_ctx_ready_set_bit(struct mfc_core_ctx *core_ctx) +{ + struct mfc_ctx *ctx = core_ctx->ctx; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + int is_ready = 0; + int src_buf_cnt, dst_buf_cnt; + + src_buf_cnt = mfc_get_queue_count(&ctx->buf_queue_lock, &core_ctx->src_buf_queue); + dst_buf_cnt = mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + + /* context is ready to make header */ + if (core_ctx->state == MFCINST_GOT_INST && dst_buf_cnt) { + if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_AT_THE_READY) { + if (src_buf_cnt) + is_ready = 1; + } else { + is_ready = 1; + } + } + + /* In mode1 encoding, MFC1 will run seq_start of dummy. */ + if (core_ctx->state == MFCINST_GOT_INST && + (ctx->stream_op_mode == MFC_OP_TWO_MODE1 && + core_ctx->core->id == MFC_CORE_SUB)) + is_ready = 1; + + /* context is ready to allocate DPB */ + else if (core_ctx->state == MFCINST_HEAD_PARSED && dst_buf_cnt && + !(ctx->stream_op_mode == MFC_OP_TWO_MODE1 && + core_ctx->core->id == MFC_CORE_SUB)) + is_ready = 1; + + /* context is ready to encode a frame */ + else if (core_ctx->state == MFCINST_RUNNING && + src_buf_cnt && dst_buf_cnt) + is_ready = 1; + + /* context is ready to encode a frame for NAL_ABORT command */ + else if (core_ctx->state == MFCINST_ABORT_INST && + src_buf_cnt && dst_buf_cnt) + is_ready = 1; + + /* context is ready to encode remain frames */ + else if (core_ctx->state == MFCINST_FINISHING && dst_buf_cnt) + is_ready = 1; + + return is_ready; +} + int mfc_ctx_ready_set_bit_raw(struct mfc_core_ctx *core_ctx, unsigned long *bits, bool set) { struct mfc_core *core = core_ctx->core; @@ -331,7 +382,10 @@ int mfc_ctx_ready_set_bit_raw(struct mfc_core_ctx *core_ctx, unsigned long *bits &ctx->dst_buf_queue), core_ctx->state, ctx->capture_state, ctx->wait_state); - is_ready = __mfc_dec_ctx_ready_set_bit(core_ctx); + if (ctx->type == MFCINST_DECODER) + is_ready = __mfc_dec_ctx_ready_set_bit(core_ctx); + else if (ctx->type == MFCINST_ENCODER) + is_ready = __mfc_enc_ctx_ready_set_bit(core_ctx); if (is_ready && set) { /* if the ctx is ready and request set_bit, set the work_bit */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c index 59cd6f3945ff..8967744b986b 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c @@ -33,15 +33,20 @@ static int __mfc_info_show(struct seq_file *s, void *unused) dev->pdata->skype.support, dev->pdata->skype.version, dev->pdata->black_bar.support, dev->pdata->black_bar.version); - seq_printf(s, " color_aspect_dec: %d(0x%x)\n", + seq_printf(s, " color_aspect_dec: %d(0x%x), enc: %d(0x%x)\n", dev->pdata->color_aspect_dec.support, - dev->pdata->color_aspect_dec.version); - seq_printf(s, " static_info_dec: %d(0x%x)\n", + dev->pdata->color_aspect_dec.version, + dev->pdata->color_aspect_enc.support, + dev->pdata->color_aspect_enc.version); + seq_printf(s, " static_info_dec: %d(0x%x), enc: %d(0x%x)\n", dev->pdata->static_info_dec.support, - dev->pdata->static_info_dec.version); - seq_printf(s, " [FORMATS] 10bit: %s, 422: %s\n", + dev->pdata->static_info_dec.version, + dev->pdata->static_info_enc.support, + dev->pdata->static_info_enc.version); + seq_printf(s, " [FORMATS] 10bit: %s, 422: %s, RGB: %s\n", dev->pdata->support_10bit ? "supported" : "not supported", - dev->pdata->support_422 ? "supported" : "not supported"); + dev->pdata->support_422 ? "supported" : "not supported", + dev->pdata->support_rgb ? "supported" : "not supported"); seq_printf(s, " [LOWMEM] is_low_mem: %d\n", IS_LOW_MEM); for (j = 0; j < dev->num_core; j++) { -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035711epcas5p437e54e8c277ee98149fccb2d984a0e55@epcas5p4.samsung.com>]
* [PATCH 28/29] media: mfc: Add AVC, VP8, VP9, and HEVC encoding support [not found] ` <CGME20250930035711epcas5p437e54e8c277ee98149fccb2d984a0e55@epcas5p4.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Introduce generic codec‑mode macros for MPEG‑4, VP8, VP9, HEVC - Extend 4:2:2 format handling and IDR‑frame processing - Suppress IVF headers for VP8/VP9 when disabled - Enable multi‑core processing for HEVC and refine instance opening flow - Expand mfc_enc_params with codec‑specific fields and raise resolution limits - Add new V4L2 controls (profiles, levels, QP, hierarchical coding, golden frames, etc.) - Implement VP9 HDR, colour‑space mapping, HEVC ROI, and extra debug logging Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_common.h | 18 +- .../samsung/exynos-mfc/base/mfc_data_struct.h | 127 ++++ .../samsung/exynos-mfc/mfc_core_enc_param.c | 649 +++++++++++++++++- .../samsung/exynos-mfc/mfc_enc_v4l2.c | 439 +++++++++++- 4 files changed, 1211 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h index bec6f88d5e44..30865588b69a 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h @@ -172,6 +172,11 @@ /* Encoder codec mode check */ #define IS_H264_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_ENC) +#define IS_MPEG4_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG4_ENC) +#define IS_H263_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H263_ENC) +#define IS_VP8_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP8_ENC) +#define IS_HEVC_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_ENC) +#define IS_VP9_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP9_ENC) #define CODEC_NOT_CODED(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ @@ -195,7 +200,8 @@ #define CODEC_422FORMAT(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ - (IS_HEVC_DEC(_ctx) || IS_VP9_DEC(_ctx)); \ + (IS_HEVC_DEC(_ctx) || IS_HEVC_ENC(_ctx) || IS_VP9_DEC(_ctx) || \ + IS_VP9_ENC(_ctx)); \ }) #define ON_RES_CHANGE(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ @@ -221,7 +227,7 @@ #define CODEC_HAS_IDR(ctx) ({ \ typeof(ctx) _ctx = (ctx); \ (IS_H264_DEC(_ctx) || IS_H264_MVC_DEC(_ctx) || IS_HEVC_DEC(_ctx) || \ - IS_H264_ENC(_ctx)); \ + IS_H264_ENC(_ctx) || IS_HEVC_ENC(_ctx)); \ }) // Buffer container @@ -229,7 +235,8 @@ #define IS_NO_HEADER_GENERATE(ctx, p) ({ \ typeof(ctx) _ctx = (ctx); \ typeof(p) _p = (p); \ - (_p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME); \ + ((_p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) || \ + ((IS_VP8_ENC(_ctx) || IS_VP9_ENC(_ctx)) && _p->ivf_header_disable)); \ }) /* @@ -332,6 +339,11 @@ (OVER_UHD_RES(_ctx) && mfc_is_enc_bframe(_ctx))); \ }) +#define IS_MULTI_MODE_ENC_CONDITION(ctx) ({ \ + typeof(ctx) _ctx = (ctx); \ + ((IS_HEVC_ENC(_ctx) && IS_MULTI_MODE_ENC_RES(_ctx))); \ +}) + #define IS_BLACKBAR_OFF(ctx) ((ctx)->crop_height > 2160) #define IS_SINGLE_FD(ctx, fmt) ((!(ctx)->rgb_bpp) && ((fmt)->mem_planes == 1)) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h index 6d34905a1cba..cb20b19b75cc 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h @@ -1246,6 +1246,129 @@ struct mfc_h264_enc_params { u32 vui_enable; }; +/** + * + */ +struct mfc_mpeg4_enc_params { + /* MPEG4 Only */ + enum v4l2_mpeg_video_mpeg4_profile profile; + u8 level; + u8 quarter_pixel; + u8 rc_b_frame_qp; + /* Common for MPEG4, H263 */ + u8 rc_frame_qp; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_min_qp_p; + u8 rc_max_qp_p; + u8 rc_min_qp_b; + u8 rc_max_qp_b; + u8 rc_p_frame_qp; + u16 vop_frm_delta; +}; + +/** + * + */ +struct mfc_vp9_enc_params { + /* VP9 Only */ + u8 profile; + u8 level; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_min_qp_p; + u8 rc_max_qp_p; + u8 rc_frame_qp; + u8 rc_p_frame_qp; + u16 vp9_gfrefreshperiod; + u8 vp9_goldenframesel; + u8 hier_qp_enable; + u8 num_hier_layer; + u8 hier_qp_layer[3]; + u32 hier_bit_layer[3]; + u8 max_partition_depth; + u8 intra_pu_split_disable; +}; + +/** + * + */ +struct mfc_vp8_enc_params { + /* VP8 Only */ + u8 vp8_version; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_min_qp_p; + u8 rc_max_qp_p; + u8 rc_frame_qp; + u8 rc_p_frame_qp; + u8 vp8_numberofpartitions; + u8 vp8_filterlevel; + u8 vp8_filtersharpness; + u16 vp8_gfrefreshperiod; + u8 vp8_goldenframesel; + u8 intra_4x4mode_disable; + u8 num_hier_layer; + u8 hier_qp_enable; + u8 hier_qp_layer[3]; + u32 hier_bit_layer[3]; +}; + +/** + * + */ +struct mfc_hevc_enc_params { + u8 profile; + u8 level; + u8 tier_flag; + /* HEVC Only */ + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_min_qp_p; + u8 rc_max_qp_p; + u8 rc_min_qp_b; + u8 rc_max_qp_b; + u8 rc_lcu_dark; + u8 rc_lcu_smooth; + u8 rc_lcu_static; + u8 rc_lcu_activity; + u8 rc_frame_qp; + u8 rc_p_frame_qp; + u8 rc_b_frame_qp; + u8 max_partition_depth; + u8 refreshtype; + u16 refreshperiod; + s32 lf_beta_offset_div2; + s32 lf_tc_offset_div2; + u8 loopfilter_disable; + u8 loopfilter_across; + u8 nal_control_length_filed; + u8 nal_control_user_ref; + u8 nal_control_store_ref; + u8 const_intra_period_enable; + u8 lossless_cu_enable; + u8 wavefront_enable; + enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type; + u8 enable_ltr; + u8 hier_qp_enable; + u8 hier_ref_type; + u8 num_hier_layer; + u32 hier_bit_layer[7]; + u8 hier_qp_layer[7]; + u8 general_pb_enable; + u8 temporal_id_enable; + u8 strong_intra_smooth; + u8 intra_pu_split_disable; + u8 tmv_prediction_disable; + u8 max_num_merge_mv; + u8 eco_mode_enable; + u8 encoding_nostartcode_enable; + u8 size_of_length_field; + u8 user_ref; + u8 store_ref; + u8 prepend_sps_pps_to_idr; +}; + /** * */ @@ -1327,6 +1450,10 @@ struct mfc_enc_params { union { struct mfc_h264_enc_params h264; + struct mfc_mpeg4_enc_params mpeg4; + struct mfc_vp8_enc_params vp8; + struct mfc_vp9_enc_params vp9; + struct mfc_hevc_enc_params hevc; } codec; }; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c index 9ff949df04ab..aea8d9c9b7ea 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c @@ -19,6 +19,20 @@ #define CBR_I_LIMIT_WFD 6 #define CBR_I_LIMIT_MAX 5 +static int mfc_colorspace_to_rgb_format_ctrl[][2] = { + { MFC_COLORSPACE_UNSPECIFICED, 1}, /* Unknown */ + { MFC_COLORSPACE_BT601, 0}, /* Rec. ITU-R BT.601-7 */ + { MFC_COLORSPACE_BT709, 1}, /* Rec. ITU-R BT.709-6 */ + { MFC_COLORSPACE_SMPTE_170, 0}, /* SMPTE-170 */ + { MFC_COLORSPACE_SMPTE_240, 0}, /* SMPTE-240 */ + { MFC_COLORSPACE_BT2020, 1}, /* Rec. ITU-R BT.2020-2 */ + { MFC_COLORSPACE_RESERVED, 1}, /* Reserved */ + { MFC_COLORSPACE_SRGB, 1}, /* sRGB (IEC 61966-2-1) */ + { MFC_COLORSPACE_UNSPECIFICED, 1}, /* Unknown */ + { MFC_COLORSPACE_UNSPECIFICED, 1}, /* Unknown */ + { MFC_COLORSPACE_UNSPECIFICED, 1}, /* Unknown */ +}; + static int mfc_transfer_to_rgb_format_ctrl[][2] = { { MFC_TRANSFER_RESERVED, 1}, { MFC_TRANSFER_BT709, 1}, @@ -226,6 +240,11 @@ static int __mfc_get_rgb_format_ctrl(struct mfc_ctx *ctx, struct mfc_enc_params if (ctx->dev->pdata->enc_rgb_csc_by_fw) { ret = 3; mfc_ctx_debug(2, "[RGB] coefficients of CSC formula using VUI by F/W\n"); + } else if (IS_VP9_ENC(ctx)) { + ret = mfc_colorspace_to_rgb_format_ctrl[p->colour_primaries][1]; + mfc_ctx_debug(2, "[RGB] VP9 color space %d converts to RGB format ctrl %s\n", + p->colour_primaries, ret ? "BT.709" : "BT.601"); + } else { ret = mfc_transfer_to_rgb_format_ctrl[p->transfer_characteristics][1]; mfc_ctx_debug(2, "[RGB] transfer %d converts to RGB format ctrl %s\n", @@ -246,7 +265,8 @@ static void __mfc_set_video_signal_type(struct mfc_core *core, struct mfc_ctx *c /* VIDEO_SIGNAL_TYPE_FLAG */ mfc_set_bits(reg, 0x1, 31, 0x1); /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); + if (!IS_VP9_ENC(ctx)) + mfc_set_bits(reg, 0x1, 24, 0x1); } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { /* VIDEO_SIGNAL_TYPE_FLAG */ @@ -254,23 +274,29 @@ static void __mfc_set_video_signal_type(struct mfc_core *core, struct mfc_ctx *c /* COLOR_RANGE */ if (!(ctx->src_fmt->type & MFC_FMT_RGB)) mfc_set_bits(reg, 0x1, 25, p->color_range); - - if (p->colour_primaries && - p->transfer_characteristics && - p->matrix_coefficients != 3) { - /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); - /* COLOUR_PRIMARIES */ - mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); - /* TRANSFER_CHARACTERISTICS */ - mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); - /* MATRIX_COEFFICIENTS */ - mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); + if (IS_VP9_ENC(ctx)) { + /* COLOR_SPACE: VP9 uses colour_primaries interface for color space */ + mfc_set_bits(reg, 0x1F, 26, p->colour_primaries); + mfc_ctx_debug(2, "[HDR] VP9 ENC Color aspect: range(%s), space(%d)\n", + p->color_range ? "Full" : "Limited", p->colour_primaries); + } else { + if (p->colour_primaries && + p->transfer_characteristics && + p->matrix_coefficients != 3) { + /* COLOUR_DESCRIPTION_PRESENT_FLAG */ + mfc_set_bits(reg, 0x1, 24, 0x1); + /* COLOUR_PRIMARIES */ + mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); + /* TRANSFER_CHARACTERISTICS */ + mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); + /* MATRIX_COEFFICIENTS */ + mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); + } + mfc_ctx_debug(2, "[HDR] %s ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", + IS_HEVC_ENC(ctx) ? "HEVC" : "H264", + p->color_range ? "Full" : "Limited", p->colour_primaries, + p->transfer_characteristics, p->matrix_coefficients); } - mfc_ctx_debug(2, "[HDR] %s ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", - "H264", - p->color_range ? "Full" : "Limited", p->colour_primaries, - p->transfer_characteristics, p->matrix_coefficients); } MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); } @@ -510,6 +536,9 @@ static void __mfc_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) if (IS_H264_ENC(ctx)) p->codec.h264.hier_qp_type = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P; + else if (IS_HEVC_ENC(ctx)) + p->codec.hevc.hier_qp_type = + V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P; mfc_ctx_info("forcely can't be use B frame for 8K or 4K %d fps\n", fps); } if (p->num_refs_for_p > 1) { @@ -829,10 +858,596 @@ static void __mfc_set_enc_params_h264(struct mfc_core *core, mfc_ctx_debug_leave(); } +static void __mfc_set_enc_params_mpeg4(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; + unsigned int reg = 0; + + mfc_ctx_debug_enter(); + + p->rc_framerate_res = FRAME_RATE_RESOLUTION; + __mfc_set_enc_params(core, ctx); + + /* set gop_size with I_FRM_CTRL mode */ + __mfc_set_gop_size(core, ctx, 1); + + /* profile & level */ + reg = 0; + /** level */ + mfc_set_bits(reg, 0xFF, 8, p_mpeg4->level); + /** profile - 0 ~ 1 */ + mfc_set_bits(reg, 0x3F, 0, p_mpeg4->profile); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); + + /* quarter_pixel */ + /* MFC_CORE_RAW_WRITEL(p_mpeg4->quarter_pixel, MFC_REG_ENC_MPEG4_QUART_PXL); */ + + /* qp */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 16, p_mpeg4->rc_b_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 24, p_mpeg4->rc_max_qp_b); + /** min B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 16, p_mpeg4->rc_min_qp_b); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + /* initialize for '0' only setting*/ + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_MPEG4_OPTIONS); /* SEQ_start only */ + MFC_CORE_RAW_WRITEL(0x0, MFC_REG_E_MPEG4_HEC_PERIOD); /* SEQ_start only */ + + mfc_ctx_debug_leave(); +} + +static void __mfc_set_enc_params_h263(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; + unsigned int reg = 0; + + mfc_ctx_debug_enter(); + + /* For H.263 only 8 bit is used and maximum value can be 0xFF */ + p->rc_framerate_res = U8_MAX; + __mfc_set_enc_params(core, ctx); + + /* set gop_size with I_FRM_CTRL mode */ + __mfc_set_gop_size(core, ctx, 1); + + /* profile & level: supports only baseline profile Level 70 */ + + /* qp */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_mpeg4->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_mpeg4->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + mfc_ctx_debug_leave(); +} + +static void __mfc_set_enc_params_vp8(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_vp8_enc_params *p_vp8 = &p->codec.vp8; + unsigned int reg = 0; + int i; + + mfc_ctx_debug_enter(); + + p->rc_framerate_res = FRAME_RATE_RESOLUTION; + __mfc_set_enc_params(core, ctx); + + if (p_vp8->num_hier_layer & 0x3) { + /* set gop_size without i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 0); + } else { + /* set gop_size with i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 1); + } + + /* profile*/ + reg = 0; + mfc_set_bits(reg, 0xF, 0, p_vp8->vp8_version); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_VP8_OPTION); + /* if num_refs_for_p is 2, the performance falls by half */ + mfc_clear_set_bits(reg, 0x1, 0, (p->num_refs_for_p - 1)); + /* vp8 partition is possible as below value: 1/2/4/8 */ + if (p_vp8->vp8_numberofpartitions & 0x1) { + if (p_vp8->vp8_numberofpartitions > 1) + mfc_ctx_err("partition should be even num (%d)\n", + p_vp8->vp8_numberofpartitions); + p_vp8->vp8_numberofpartitions = (p_vp8->vp8_numberofpartitions & ~0x1); + } + mfc_clear_set_bits(reg, 0xF, 3, p_vp8->vp8_numberofpartitions); + mfc_clear_set_bits(reg, 0x1, 10, p_vp8->intra_4x4mode_disable); + /* Temporal SVC - hier qp enable */ + mfc_clear_set_bits(reg, 0x1, 11, p_vp8->hier_qp_enable); + /* Disable IVF header */ + mfc_clear_set_bits(reg, 0x1, 12, p->ivf_header_disable); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VP8_OPTION); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_VP8_GOLDEN_FRAME_OPTION); + mfc_clear_set_bits(reg, 0x1, 0, p_vp8->vp8_goldenframesel); + mfc_clear_set_bits(reg, 0xFFFF, 1, p_vp8->vp8_gfrefreshperiod); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VP8_GOLDEN_FRAME_OPTION); + + /* Temporal SVC - layer number */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_NUM_T_LAYER); + mfc_clear_set_bits(reg, 0x7, 0, p_vp8->num_hier_layer); + mfc_clear_set_bits(reg, 0x7, 4, 0x3); + mfc_clear_set_bits(reg, 0x1, 8, p->hier_bitrate_ctrl); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); + mfc_ctx_debug(3, "[HIERARCHICAL] hier_qp_enable %d, num_hier_layer %d, NUM_T_LAYER 0x%x\n", + p_vp8->hier_qp_enable, p_vp8->num_hier_layer, reg); + + /* QP & Bitrate for each layer */ + for (i = 0; i < 3; i++) { + MFC_CORE_RAW_WRITEL(p_vp8->hier_qp_layer[i], + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); + /* If hier_bitrate_ctrl is set to 1, this is meaningless */ + MFC_CORE_RAW_WRITEL(p_vp8->hier_bit_layer[i], + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + mfc_ctx_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %#x(FW ctrl: %d)\n", + i, p_vp8->hier_qp_layer[i], + p_vp8->hier_bit_layer[i], p->hier_bitrate_ctrl); + } + + reg = 0; + mfc_set_bits(reg, 0x7, 0, p_vp8->vp8_filtersharpness); + mfc_set_bits(reg, 0x3F, 8, p_vp8->vp8_filterlevel); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VP8_FILTER_OPTION); + + /* qp */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_vp8->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_vp8->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp8->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_vp8->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp8->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_vp8->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp8->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + mfc_ctx_debug_leave(); +} + +static void __mfc_enc_check_vp9_profile(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; + + if (!ctx->is_422) { + /* YUV420 8bit format */ + if (p_vp9->profile != MFC_REG_E_PROFILE_VP9_PROFILE0) { + mfc_ctx_err("4:2:0 format is not matched with profile(%d)\n", + p_vp9->profile); + p_vp9->profile = MFC_REG_E_PROFILE_VP9_PROFILE0; + } + } else if (ctx->is_422) { + /* YUV422 8bit format */ + if (p_vp9->profile != MFC_REG_E_PROFILE_VP9_PROFILE1) { + mfc_ctx_err("4:2:2 format is not matched with profile(%d)\n", + p_vp9->profile); + p_vp9->profile = MFC_REG_E_PROFILE_VP9_PROFILE1; + } + } +} + +static void __mfc_set_enc_params_vp9(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; + unsigned int reg = 0; + int i; + + mfc_ctx_debug_enter(); + + p->rc_framerate_res = FRAME_RATE_RESOLUTION; + __mfc_set_enc_params(core, ctx); + __mfc_enc_check_vp9_profile(ctx); + + if (p_vp9->num_hier_layer & 0x3) { + /* set gop_size without i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 0); + } else { + /* set gop_size with i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 1); + } + + /* profile*/ + reg = 0; + mfc_set_bits(reg, 0xF, 0, p_vp9->profile); + /* level */ + mfc_set_bits(reg, 0xFF, 8, p_vp9->level); + + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_VP9_OPTION); + /* if num_refs_for_p is 2, the performance falls by half */ + mfc_clear_set_bits(reg, 0x1, 0, (p->num_refs_for_p - 1)); + mfc_clear_set_bits(reg, 0x1, 1, p_vp9->intra_pu_split_disable); + mfc_clear_set_bits(reg, 0x1, 3, p_vp9->max_partition_depth); + /* Temporal SVC - hier qp enable */ + mfc_clear_set_bits(reg, 0x1, 11, p_vp9->hier_qp_enable); + /* Disable IVF header */ + mfc_clear_set_bits(reg, 0x1, 12, p->ivf_header_disable); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VP9_OPTION); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_VP9_GOLDEN_FRAME_OPTION); + mfc_clear_set_bits(reg, 0x1, 0, p_vp9->vp9_goldenframesel); + mfc_clear_set_bits(reg, 0xFFFF, 1, p_vp9->vp9_gfrefreshperiod); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VP9_GOLDEN_FRAME_OPTION); + + /* Temporal SVC - layer number */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_NUM_T_LAYER); + mfc_clear_set_bits(reg, 0x7, 0, p_vp9->num_hier_layer); + mfc_clear_set_bits(reg, 0x7, 4, 0x3); + mfc_clear_set_bits(reg, 0x1, 8, p->hier_bitrate_ctrl); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); + mfc_ctx_debug(3, "[HIERARCHICAL] hier_qp_enable %d, num_hier_layer %d, NUM_T_LAYER 0x%x\n", + p_vp9->hier_qp_enable, p_vp9->num_hier_layer, reg); + + /* QP & Bitrate for each layer */ + for (i = 0; i < 3; i++) { + MFC_CORE_RAW_WRITEL(p_vp9->hier_qp_layer[i], + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); + /* If hier_bitrate_ctrl is set to 1, this is meaningless */ + MFC_CORE_RAW_WRITEL(p_vp9->hier_bit_layer[i], + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + mfc_ctx_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %#x (FW ctrl: %d)\n", + i, p_vp9->hier_qp_layer[i], + p_vp9->hier_bit_layer[i], p->hier_bitrate_ctrl); + } + + /* qp */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_vp9->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_vp9->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp9->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_vp9->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp9->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_vp9->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_vp9->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + mfc_ctx_debug_leave(); +} + +static void __mfc_enc_check_hevc_profile(struct mfc_ctx *ctx) +{ + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_hevc_enc_params *p_hevc = &p->codec.hevc; + + if (!ctx->is_422) { + /* YUV420 8bit format */ + if (p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN && + p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_10) { + mfc_ctx_err("4:2:0 format is not matched with profile(%d)\n", + p_hevc->profile); + p_hevc->profile = MFC_REG_E_PROFILE_HEVC_MAIN; + } + } else if (ctx->is_422) { + /* YUV422 8bit format */ + if (p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10_INTRA && + p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10) { + mfc_ctx_err("4:2:2 format is not matched with profile(%d)\n", + p_hevc->profile); + p_hevc->profile = MFC_REG_E_PROFILE_HEVC_MAIN_422_10; + } + } +} + +static void __mfc_set_enc_params_hevc(struct mfc_core *core, + struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_hevc_enc_params *p_hevc = &p->codec.hevc; + unsigned int mb = 0; + unsigned int reg = 0; + bool enable_stream_copy = false; + int i; + + mfc_ctx_debug_enter(); + + p->rc_framerate_res = FRAME_RATE_RESOLUTION; + __mfc_set_enc_params(core, ctx); + __mfc_enc_check_hevc_profile(ctx); + + if (p_hevc->num_hier_layer & 0x7) { + /* set gop_size without i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 0); + } else { + /* set gop_size with i_frm_ctrl mode */ + __mfc_set_gop_size(core, ctx, 1); + } + + mb = WIDTH_MB((ctx)->crop_width) * HEIGHT_MB((ctx)->crop_height); + /* Level 6.0 case */ + if (IS_LV60_MB(mb) && p_hevc->level < 60) + mfc_ctx_info("This resolution(mb: %d) recommends level6.0\n", mb); + + /* Level 5.1 case */ + if (IS_LV51_MB(mb) && p_hevc->level < 51) + mfc_ctx_info("This resolution(mb: %d) recommends level5.1\n", mb); + + /* tier_flag & level & profile */ + reg = 0; + + /* profile */ + if (ctx->multi_view_enable) + mfc_set_bits(reg, 0xF, 0, 0x6); + else + mfc_set_bits(reg, 0xF, 0, p_hevc->profile); + + /* level */ + mfc_set_bits(reg, 0xFF, 8, p_hevc->level); + /* tier_flag - 0 ~ 1 */ + mfc_set_bits(reg, 0x1, 16, p_hevc->tier_flag); + + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_OPTIONS); + /* max partition depth */ + mfc_clear_set_bits(reg, 0x3, 0, p_hevc->max_partition_depth); + /* if num_refs_for_p is 2, the performance falls by half */ + mfc_clear_set_bits(reg, 0x1, 2, (p->num_refs_for_p - 1)); + mfc_clear_set_bits(reg, 0x3, 3, p_hevc->refreshtype); + mfc_clear_set_bits(reg, 0x1, 5, p_hevc->const_intra_period_enable); + mfc_clear_set_bits(reg, 0x1, 6, p_hevc->lossless_cu_enable); + mfc_clear_set_bits(reg, 0x1, 7, p_hevc->wavefront_enable); + mfc_clear_set_bits(reg, 0x1, 8, p_hevc->loopfilter_disable); + mfc_clear_set_bits(reg, 0x1, 9, p_hevc->loopfilter_across); + mfc_clear_set_bits(reg, 0x1, 10, p_hevc->enable_ltr); + mfc_clear_set_bits(reg, 0x1, 11, p_hevc->hier_qp_enable); + mfc_clear_set_bits(reg, 0x1, 13, p_hevc->general_pb_enable); + mfc_clear_set_bits(reg, 0x1, 14, p_hevc->temporal_id_enable); + mfc_clear_set_bits(reg, 0x1, 15, p_hevc->strong_intra_smooth); + mfc_clear_set_bits(reg, 0x1, 16, p_hevc->intra_pu_split_disable); + mfc_clear_set_bits(reg, 0x1, 17, p_hevc->tmv_prediction_disable); + mfc_clear_set_bits(reg, 0x7, 18, p_hevc->max_num_merge_mv); + mfc_clear_set_bits(reg, 0x1, 23, p_hevc->encoding_nostartcode_enable); + mfc_clear_set_bits(reg, 0x1, 26, p_hevc->prepend_sps_pps_to_idr); + + /* Weighted Prediction enable */ + mfc_clear_set_bits(reg, 0x1, 28, p->weighted_enable); + /* 30bit is 32x32 transform. If it is enabled, the performance falls by half */ + mfc_clear_bits(reg, 0x1, 30); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_OPTIONS_2); + /* Timing info */ + mfc_set_bits(reg, 0x1, 2, p->timing_info_enable); + + // TODO : replace this magic number to define + mfc_clear_set_bits(reg, 0x1, 9, (ctx->stream_op_mode == MFC_OP_TWO_MODE1)); + enable_stream_copy = ((ctx->stream_op_mode == MFC_OP_TWO_MODE1) && + !(dev->debugfs.feature_option & MFC_OPTION_STREAM_COPY_DISABLE)); + mfc_clear_set_bits(reg, 0x1, 13, enable_stream_copy); + + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS_2); + + /* refresh period */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_REFRESH_PERIOD); + mfc_clear_set_bits(reg, 0xFFFF, 0, p_hevc->refreshperiod); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_REFRESH_PERIOD); + /* loop filter setting */ + MFC_CORE_RAW_WRITEL(0, MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2); + MFC_CORE_RAW_WRITEL(0, MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2); + if (!p_hevc->loopfilter_disable) { + MFC_CORE_RAW_WRITEL + (p_hevc->lf_beta_offset_div2, MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2); + MFC_CORE_RAW_WRITEL + (p_hevc->lf_tc_offset_div2, MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2); + } + /* long term reference */ + if (p_hevc->enable_ltr) { + reg = 0; + mfc_set_bits(reg, 0x3, 0, p_hevc->store_ref); + mfc_set_bits(reg, 0x3, 2, p_hevc->user_ref); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_NAL_CONTROL); + } + + /* Temporal SVC - qp type, layer number */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_NUM_T_LAYER); + mfc_clear_set_bits(reg, 0x1, 3, p_hevc->hier_qp_type); + mfc_clear_set_bits(reg, 0x7, 0, p_hevc->num_hier_layer); + mfc_clear_bits(reg, 0x7, 4); + if (p_hevc->hier_ref_type) { + mfc_set_bits(reg, 0x1, 7, 0x1); + mfc_set_bits(reg, 0x7, 4, p->num_hier_max_layer); + } else { + mfc_clear_bits(reg, 0x1, 7); + mfc_set_bits(reg, 0x7, 4, p_hevc->num_hier_layer); + } + mfc_clear_set_bits(reg, 0x1, 8, p->hier_bitrate_ctrl); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); + mfc_ctx_debug(3, "[HIERARCHICAL] hier_qp_enable %d, enable_ltr %d, ", + p_hevc->hier_qp_enable, p_hevc->enable_ltr); + mfc_ctx_debug(3, "num_hier_layer %d, max_layer %d, hier_ref_type %d, NUM_T_LAYER 0x%x\n", + p_hevc->num_hier_layer, p->num_hier_max_layer, p_hevc->hier_ref_type, reg); + + /* QP & Bitrate for each layer */ + for (i = 0; i < 7; i++) { + MFC_CORE_RAW_WRITEL(p_hevc->hier_qp_layer[i], + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); + MFC_CORE_RAW_WRITEL(p_hevc->hier_bit_layer[i], + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + mfc_ctx_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %d(FW ctrl: %d)\n", + i, p_hevc->hier_qp_layer[i], + p_hevc->hier_bit_layer[i], p->hier_bitrate_ctrl); + } + + /* rate control config. */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_CONFIG); + /** frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_hevc->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_CONFIG); + + /* max & min value of QP for I frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND); + /** max I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_hevc->rc_max_qp); + /** min I frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_hevc->rc_min_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); + + /* max & min value of QP for P/B frame */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_QP_BOUND_PB); + /** max B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 24, p_hevc->rc_max_qp_b); + /** min B frame QP */ + mfc_clear_set_bits(reg, 0xFF, 16, p_hevc->rc_min_qp_b); + /** max P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 8, p_hevc->rc_max_qp_p); + /** min P frame QP */ + mfc_clear_set_bits(reg, 0xFF, 0, p_hevc->rc_min_qp_p); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_FIXED_PICTURE_QP); + mfc_clear_set_bits(reg, 0xFF, 24, p->config_qp); + mfc_clear_set_bits(reg, 0xFF, 16, p_hevc->rc_b_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 8, p_hevc->rc_p_frame_qp); + mfc_clear_set_bits(reg, 0xFF, 0, p_hevc->rc_frame_qp); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); + + /* chroma QP offset */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_CHROMA_QP_OFFSET); + mfc_clear_set_bits(reg, 0x1F, 5, p->chroma_qp_offset_cr); + mfc_clear_set_bits(reg, 0x1F, 0, p->chroma_qp_offset_cb); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_CHROMA_QP_OFFSET); + + /* ROI enable: it must set on SEQ_START only for HEVC encoder */ + reg = MFC_CORE_RAW_READL(MFC_REG_E_RC_ROI_CTRL); + mfc_clear_set_bits(reg, 0x1, 0, p->roi_enable); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_ROI_CTRL); + mfc_ctx_debug(3, "[ROI] HEVC ROI %s\n", p->roi_enable ? "enable" : "disable"); + + reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_OPTIONS_2); + /* HDR_STATIC_INFO_ENABLE */ + mfc_clear_bits(reg, 0x1, 0); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS_2); + + reg = MFC_CORE_READL(MFC_REG_E_MVC_INTER_VIEW_PREDICTION_ON); + mfc_clear_set_bits(reg, 0x1, 0, ctx->multi_view_enable); + /* LEFT_VIEW_ID */ + mfc_clear_set_bits(reg, 0x3, 1, ctx->left_view_id); + /* RIGHT_VIEW_ID. Always opposite to left. */ + mfc_clear_set_bits(reg, 0x3, 3, ctx->left_view_id ? 0 : 1); + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_MVC_INTER_VIEW_PREDICTION_ON); + + mfc_ctx_debug_leave(); +} + int mfc_core_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) { if (IS_H264_ENC(ctx)) { __mfc_set_enc_params_h264(core, ctx); + } else if (IS_MPEG4_ENC(ctx)) { + __mfc_set_enc_params_mpeg4(core, ctx); + } else if (IS_H263_ENC(ctx)) { + __mfc_set_enc_params_h263(core, ctx); + } else if (IS_VP8_ENC(ctx)) { + __mfc_set_enc_params_vp8(core, ctx); + } else if (IS_VP9_ENC(ctx)) { + __mfc_set_enc_params_vp9(core, ctx); + } else if (IS_HEVC_ENC(ctx)) { + __mfc_set_enc_params_hevc(core, ctx); } else { mfc_ctx_err("Unknown codec for encoding (%x)\n", ctx->codec_mode); return -EINVAL; diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c index 84edebac82b2..386262623977 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c @@ -2667,10 +2667,33 @@ static int __mfc_enc_check_resolution(struct mfc_ctx *ctx) /* Check max resolution */ switch (ctx->codec_mode) { + case MFC_REG_CODEC_HEVC_ENC: + if (ctx->is_422) { + max_width = 65536; + max_height = 8192; + swap_check = 1; + } else { + max_width = 8192; + max_height = 8192; + } + break; case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_VP8_ENC: max_width = 8192; max_height = 8192; break; + case MFC_REG_CODEC_VP9_ENC: + max_width = 4096; + max_height = 8192; + break; + case MFC_REG_CODEC_MPEG4_ENC: + max_width = 2048; + max_height = 2048; + break; + case MFC_REG_CODEC_H263_ENC: + max_width = 2048; + max_height = 1152; + break; default: mfc_ctx_err("Not supported codec(%d)\n", ctx->codec_mode); return -EINVAL; @@ -2694,7 +2717,15 @@ static int __mfc_enc_check_resolution(struct mfc_ctx *ctx) /* Check min resolution */ switch (ctx->codec_mode) { + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_VP9_ENC: + min_width = 64; + min_height = 64; + break; case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_VP8_ENC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: min_width = 32; min_height = 32; break; @@ -2767,7 +2798,8 @@ static int mfc_enc_s_fmt_vid_cap_mplane(struct file *file, void *priv, mfc_ctx_err("Failed to instance open\n"); if (dev->pdata->support_enc_mode1 && - (dev->debugfs.feature_option & MFC_OPTION_SET_MULTI_CORE_FORCE)) { + (IS_MULTI_MODE_ENC_CONDITION(ctx) || + (dev->debugfs.feature_option & MFC_OPTION_SET_MULTI_CORE_FORCE))) { if (dev->debugfs.feature_option & MFC_OPTION_MULTI_CORE_DISABLE) { mfc_ctx_info("[2CORE] multi core mode disabled\n"); } else { @@ -3751,12 +3783,382 @@ static int __mfc_enc_set_param(struct mfc_ctx *ctx, struct v4l2_control *ctrl) p->codec.h264.base_priority = ctrl->value; p->codec.h264.set_priority = 1; break; + case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: + switch ((enum v4l2_mpeg_video_mpeg4_profile)(ctrl->value)) { + case V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE: + p->codec.mpeg4.profile = + MFC_REG_E_PROFILE_MPEG4_SIMPLE; + break; + case V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE: + p->codec.mpeg4.profile = + MFC_REG_E_PROFILE_MPEG4_ADVANCED_SIMPLE; + break; + default: + ret = -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: + p->codec.mpeg4.level = + __mfc_enc_mpeg4_level((enum v4l2_mpeg_video_mpeg4_level)(ctrl->value)); + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: + p->codec.mpeg4.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP: + p->codec.mpeg4.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP: + p->codec.mpeg4.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P: + p->codec.mpeg4.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P: + p->codec.mpeg4.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B: + p->codec.mpeg4.rc_min_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B: + p->codec.mpeg4.rc_max_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_QPEL: + p->codec.mpeg4.quarter_pixel = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: + p->codec.mpeg4.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: + p->codec.mpeg4.rc_b_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_TIME_RES: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_MPEG4_VOP_FRM_DELTA: + p->codec.mpeg4.vop_frm_delta = ctrl->value; + break; + case V4L2_CID_MPEG_MFC51_VIDEO_H263_RC_FRAME_RATE: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP: + p->codec.mpeg4.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_MIN_QP: + p->codec.mpeg4.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_MAX_QP: + p->codec.mpeg4.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P: + p->codec.mpeg4.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P: + p->codec.mpeg4.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP: + p->codec.mpeg4.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_VERSION: + p->codec.vp8.vp8_version = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_RC_FRAME_RATE: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_MIN_QP: + p->codec.vp8.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_MAX_QP: + p->codec.vp8.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P: + p->codec.vp8.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P: + p->codec.vp8.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_I_FRAME_QP: + p->codec.vp8.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_P_FRAME_QP: + p->codec.vp8.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_OF_PARTITIONS: + p->codec.vp8.vp8_numberofpartitions = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_LEVEL: + p->codec.vp8.vp8_filterlevel = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_FILTER_SHARPNESS: + p->codec.vp8.vp8_filtersharpness = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_GOLDEN_FRAMESEL: + p->codec.vp8.vp8_goldenframesel = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_GF_REFRESH_PERIOD: + p->codec.vp8.vp8_gfrefreshperiod = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_ENABLE: + p->codec.vp8.hier_qp_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER0: + p->codec.vp8.hier_qp_layer[(ctrl->value >> 16) & 0x3] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER1: + p->codec.vp8.hier_qp_layer[(ctrl->value >> 16) & 0x3] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_HIERARCHY_QP_LAYER2: + p->codec.vp8.hier_qp_layer[(ctrl->value >> 16) & 0x3] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT0: + p->codec.vp8.hier_bit_layer[0] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT1: + p->codec.vp8.hier_bit_layer[1] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_BIT2: + p->codec.vp8.hier_bit_layer[2] = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_REF_NUMBER_FOR_PFRAMES: + p->num_refs_for_p = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_DISABLE_INTRA_MD4X4: + p->codec.vp8.intra_4x4mode_disable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC70_VIDEO_VP8_NUM_TEMPORAL_LAYER: + p->codec.vp8.num_hier_layer = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_VERSION: + p->codec.vp9.profile = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_RC_FRAME_RATE: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_MIN_QP: + p->codec.vp9.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_MAX_QP: + p->codec.vp9.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P: + p->codec.vp9.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P: + p->codec.vp9.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_I_FRAME_QP: + p->codec.vp9.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_P_FRAME_QP: + p->codec.vp9.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_GOLDEN_FRAMESEL: + p->codec.vp9.vp9_goldenframesel = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_GF_REFRESH_PERIOD: + p->codec.vp9.vp9_gfrefreshperiod = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHY_QP_ENABLE: + p->codec.vp9.hier_qp_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_QP: + p->codec.vp9.hier_qp_layer[(ctrl->value >> 16) & 0x3] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT0: + p->codec.vp9.hier_bit_layer[0] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT1: + p->codec.vp9.hier_bit_layer[1] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_BIT2: + p->codec.vp9.hier_bit_layer[2] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_REF_NUMBER_FOR_PFRAMES: + p->num_refs_for_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER: + p->codec.vp9.num_hier_layer = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_MAX_PARTITION_DEPTH: + p->codec.vp9.max_partition_depth = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_DISABLE_INTRA_PU_SPLIT: + p->codec.vp9.intra_pu_split_disable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_DISABLE_IVF_HEADER: + p->ivf_header_disable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: + p->codec.vp9.profile = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: + p->codec.vp9.level = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: + p->codec.hevc.rc_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: + p->codec.hevc.rc_p_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: + p->codec.hevc.rc_b_frame_qp = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_RC_FRAME_RATE: + p->rc_framerate = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: + p->codec.hevc.rc_min_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: + p->codec.hevc.rc_max_qp = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P: + p->codec.hevc.rc_min_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P: + p->codec.hevc.rc_max_qp_p = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B: + p->codec.hevc.rc_min_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B: + p->codec.hevc.rc_max_qp_b = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: + p->codec.hevc.level = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: + p->codec.hevc.profile = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_DARK: + p->codec.hevc.rc_lcu_dark = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH: + p->codec.hevc.rc_lcu_smooth = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_STATIC: + p->codec.hevc.rc_lcu_static = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY: + p->codec.hevc.rc_lcu_activity = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TIER_FLAG: + p->codec.hevc.tier_flag = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_PARTITION_DEPTH: + p->codec.hevc.max_partition_depth = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES: + p->num_refs_for_p = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_TYPE: + p->codec.hevc.refreshtype = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE: + p->codec.hevc.const_intra_period_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LOSSLESS_CU_ENABLE: + p->codec.hevc.lossless_cu_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WAVEFRONT_ENABLE: + p->codec.hevc.wavefront_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_DISABLE: + p->codec.hevc.loopfilter_disable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_SLICE_BOUNDARY: + p->codec.hevc.loopfilter_across = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LTR_ENABLE: + p->codec.hevc.enable_ltr = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE: + p->codec.hevc.hier_qp_enable = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE: + p->codec.hevc.hier_qp_type = + (enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->value); + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER: + p->codec.hevc.num_hier_layer = ctrl->value & 0x7; + p->codec.hevc.hier_ref_type = (ctrl->value >> 16) & 0x1; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP: + p->codec.hevc.hier_qp_layer[(ctrl->value >> 16) & 0x7] = + ctrl->value & 0xFF; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0: + p->codec.hevc.hier_bit_layer[0] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1: + p->codec.hevc.hier_bit_layer[1] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2: + p->codec.hevc.hier_bit_layer[2] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3: + p->codec.hevc.hier_bit_layer[3] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4: + p->codec.hevc.hier_bit_layer[4] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5: + p->codec.hevc.hier_bit_layer[5] = ctrl->value; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6: + p->codec.hevc.hier_bit_layer[6] = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_GENERAL_PB_ENABLE: + p->codec.hevc.general_pb_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_TEMPORAL_ID_ENABLE: + p->codec.hevc.temporal_id_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STRONG_SMOTHING_FLAG: + p->codec.hevc.strong_intra_smooth = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT: + p->codec.hevc.intra_pu_split_disable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_DISABLE_TMV_PREDICTION: + p->codec.hevc.tmv_prediction_disable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: + p->codec.hevc.max_num_merge_mv = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE: + p->codec.hevc.encoding_nostartcode_enable = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_REFRESH_PERIOD: + p->codec.hevc.refreshperiod = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: + p->codec.hevc.lf_beta_offset_div2 = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_LF_TC_OFFSET_DIV2: + p->codec.hevc.lf_tc_offset_div2 = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: + p->codec.hevc.size_of_length_field = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_USER_REF: + p->codec.hevc.user_ref = ctrl->value; + break; + case V4L2_CID_MPEG_MFC90_VIDEO_HEVC_STORE_REF: + p->codec.hevc.store_ref = ctrl->value; + break; case V4L2_CID_MPEG_VIDEO_ROI_ENABLE: p->roi_enable = ctrl->value; break; case V4L2_CID_MPEG_MFC_H264_VUI_RESTRICTION_ENABLE: p->codec.h264.vui_enable = ctrl->value; break; + case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR: + p->codec.hevc.prepend_sps_pps_to_idr = ctrl->value; + break; case V4L2_CID_MPEG_MFC_CONFIG_QP_ENABLE: p->dynamic_qp = ctrl->value; break; @@ -3924,7 +4326,13 @@ static int __mfc_enc_set_ctrl_val_list(struct mfc_ctx *ctx, ctx_ctrl->set.has_new = 1; ctx_ctrl->set.val = ctrl->value; if (ctx_ctrl->id == - V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH) { + V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH || + ctx_ctrl->id == + V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH || + ctx_ctrl->id == + V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH || + ctx_ctrl->id == + V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH) { if (enc->sh_handle_svc.fd == -1) { enc->sh_handle_svc.fd = ctrl->value; if (mfc_mem_get_user_shared_handle @@ -3984,17 +4392,44 @@ static int __mfc_enc_set_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl case V4L2_CID_MPEG_VIDEO_QOS_RATIO: break; case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: + case V4L2_CID_MPEG_VIDEO_H263_MAX_QP: + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP: + case V4L2_CID_MPEG_VIDEO_VP8_MAX_QP: + case V4L2_CID_MPEG_VIDEO_VP9_MAX_QP: + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + case V4L2_CID_MPEG_VIDEO_H263_MIN_QP: + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP: + case V4L2_CID_MPEG_VIDEO_VP8_MIN_QP: + case V4L2_CID_MPEG_VIDEO_VP9_MIN_QP: + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P: + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P: case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P: + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P: case V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B: + case V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B: + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B: case V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B: + case V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B: + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B: case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG: case V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE: case V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH: case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH: case V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH: case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH: + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH: case V4L2_CID_MPEG_VIDEO_H264_PROFILE: case V4L2_CID_MPEG_VIDEO_H264_LEVEL: case V4L2_CID_MPEG_MFC_H264_MARK_LTR: -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20250930035717epcas5p1dd561ae382ab7cbab428c528a046e989@epcas5p1.samsung.com>]
* [PATCH 29/29] media: mfc: Hardware‑accelerated encoding support [not found] ` <CGME20250930035717epcas5p1dd561ae382ab7cbab428c528a046e989@epcas5p1.samsung.com> @ 2025-09-30 4:03 ` Himanshu Dewangan 0 siblings, 0 replies; 38+ messages in thread From: Himanshu Dewangan @ 2025-09-30 4:03 UTC (permalink / raw) To: mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig, Himanshu Dewangan From: Nagaraju Siddineni <nagaraju.s@samsung.com> - Add for MPEG‑4, H.263, VP8/VP9, HEVC codec support with extended contexts and buffer allocation. - Implement LCU sizing, motion‑estimation buffers, and align scratch buffers. - Unify ROI buffer handling across all encoders. - Register additional pixel formats (`mfc_format.h`). - Enhance QoS weighting and B‑frame/reference‑count logic. - Introduce hierarchical‑coding controls (layer count, per‑layer bitrate) and SVC for HEVC, VP8, VP9. - Update timestamp handling for H.263 and improved VP8 buffer‑exhaustion error reporting. Signed-off-by: Nagaraju Siddineni <nagaraju.s@samsung.com> Signed-off-by: Himanshu Dewangan <h.dewangan@samsung.com> --- .../samsung/exynos-mfc/base/mfc_buf.c | 71 ++++++++++++++++++- .../samsung/exynos-mfc/base/mfc_format.h | 40 +++++++++++ .../samsung/exynos-mfc/base/mfc_qos.c | 23 +++++- .../samsung/exynos-mfc/base/mfc_utils.h | 10 ++- .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 59 ++++++++++++++- .../samsung/exynos-mfc/mfc_core_isr.c | 2 + 6 files changed, 198 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c index 0186fe3327f1..164852e83e7d 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c @@ -133,10 +133,17 @@ int mfc_alloc_instance_context(struct mfc_core_ctx *core_ctx) core_ctx->instance_ctx_buf.size = buf_size->other_dec_ctx; break; case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_AV1_DEC: core_ctx->instance_ctx_buf.size = buf_size->h264_enc_ctx; break; - case MFC_REG_CODEC_AV1_DEC: - core_ctx->instance_ctx_buf.size = buf_size->av1_dec_ctx; + case MFC_REG_CODEC_HEVC_ENC: + core_ctx->instance_ctx_buf.size = buf_size->hevc_enc_ctx; + break; + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: + case MFC_REG_CODEC_VP8_ENC: + case MFC_REG_CODEC_VP9_ENC: + core_ctx->instance_ctx_buf.size = buf_size->other_enc_ctx; break; default: core_ctx->instance_ctx_buf.size = 0; @@ -256,6 +263,7 @@ static void __mfc_enc_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) struct mfc_ctx *ctx = core_ctx->ctx; struct mfc_enc *enc; unsigned int mb_width, mb_height; + unsigned int lcu_width = 0, lcu_height = 0; enc = ctx->enc_priv; enc->tmv_buffer_size = 0; @@ -263,6 +271,9 @@ static void __mfc_enc_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) mb_width = WIDTH_MB(ctx->crop_width); mb_height = HEIGHT_MB(ctx->crop_height); + lcu_width = ENC_LCU_WIDTH(ctx->crop_width); + lcu_height = ENC_LCU_HEIGHT(ctx->crop_height); + /* default recon buffer size, it can be changed in case of 422, 10bit */ enc->luma_dpb_size = ALIGN(ENC_LUMA_DPB_SIZE(ctx->crop_width, ctx->crop_height), SZ_64); @@ -293,6 +304,47 @@ static void __mfc_enc_calc_codec_buffer_size(struct mfc_core_ctx *core_ctx) (ctx->dpb_count * (enc->luma_dpb_size + enc->chroma_dpb_size + enc->me_buffer_size)); break; + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: + enc->me_buffer_size = + ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, mb_height), SZ_256); + + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + enc->tmv_buffer_size + + (ctx->dpb_count * (enc->luma_dpb_size + + enc->chroma_dpb_size + enc->me_buffer_size)); + break; + case MFC_REG_CODEC_VP8_ENC: + enc->me_buffer_size = + ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), SZ_256); + + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + enc->tmv_buffer_size + + (ctx->dpb_count * (enc->luma_dpb_size + + enc->chroma_dpb_size + enc->me_buffer_size)); + break; + case MFC_REG_CODEC_VP9_ENC: + enc->me_buffer_size = + ALIGN(ENC_V100_VP9_ME_SIZE(lcu_width, lcu_height), SZ_256); + + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + enc->tmv_buffer_size + + (ctx->dpb_count * (enc->luma_dpb_size + + enc->chroma_dpb_size + enc->me_buffer_size)); + break; + case MFC_REG_CODEC_HEVC_ENC: + enc->me_buffer_size = + ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), SZ_256); + + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, SZ_256); + core_ctx->codec_buf.size = + ctx->scratch_buf_size + enc->tmv_buffer_size + + (ctx->dpb_count * (enc->luma_dpb_size + + enc->chroma_dpb_size + enc->me_buffer_size)); + break; default: core_ctx->codec_buf.size = 0; mfc_err("invalid codec type: %d\n", ctx->codec_mode); @@ -493,6 +545,7 @@ int mfc_alloc_enc_roi_buffer(struct mfc_core_ctx *core_ctx) struct mfc_ctx *ctx = core_ctx->ctx; struct mfc_enc *enc = ctx->enc_priv; unsigned int mb_width, mb_height; + unsigned int lcu_width = 0, lcu_height = 0; size_t size; int i; @@ -503,6 +556,20 @@ int mfc_alloc_enc_roi_buffer(struct mfc_core_ctx *core_ctx) case MFC_REG_CODEC_H264_ENC: size = ((((mb_width * (mb_height + 1) / 2) + 15) / 16) * 16) * 2; break; + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_VP8_ENC: + size = mb_width * mb_height; + break; + case MFC_REG_CODEC_VP9_ENC: + lcu_width = (ctx->crop_width + 63) / 64; + lcu_height = (ctx->crop_height + 63) / 64; + size = lcu_width * lcu_height * 4; + break; + case MFC_REG_CODEC_HEVC_ENC: + lcu_width = (ctx->crop_width + 31) / 32; + lcu_height = (ctx->crop_height + 31) / 32; + size = lcu_width * lcu_height; + break; default: mfc_debug(2, "ROI not supported codec type(%d). Allocate with default size\n", diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h index e8573d6b6005..070c669e1d82 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h @@ -271,6 +271,46 @@ static struct mfc_fmt mfc_formats[] = { .num_planes = 1, .mem_planes = 1, }, + { + .name = "ENC MPEG4", + .fourcc = V4L2_PIX_FMT_MPEG4, + .codec_mode = MFC_REG_CODEC_MPEG4_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "ENC H263", + .fourcc = V4L2_PIX_FMT_H263, + .codec_mode = MFC_REG_CODEC_H263_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "ENC VP8", + .fourcc = V4L2_PIX_FMT_VP8, + .codec_mode = MFC_REG_CODEC_VP8_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "ENC VP9", + .fourcc = V4L2_PIX_FMT_VP9, + .codec_mode = MFC_REG_CODEC_VP9_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, + { + .name = "ENC HEVC", + .fourcc = V4L2_PIX_FMT_HEVC, + .codec_mode = MFC_REG_CODEC_HEVC_ENC, + .type = MFC_FMT_STREAM | MFC_FMT_ENC, + .num_planes = 1, + .mem_planes = 1, + }, }; #endif /* __MFC_FORMAT_H */ diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c index 40541e2d626f..73058ace1fd6 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c @@ -58,6 +58,7 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l break; case MFC_REG_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP8_ENC: weight = (weight * 100) / qos_weight->weight_vp8_vp9; mfc_ctx_debug(3, "[QoS] vp8, vp9 codec, weight: %d\n", weight / 10); if (num_planes == 3) { @@ -80,12 +81,26 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l } break; + case MFC_REG_CODEC_HEVC_ENC: + weight = (weight * 100) / qos_weight->weight_h264_hevc; + mfc_ctx_debug(3, "[QoS] h264, hevc codec, weight: %d\n", weight / 10); + if (num_planes == 3) { + weight = (weight * 100) / qos_weight->weight_3plane; + mfc_ctx_debug(3, "[QoS] 3 plane, weight: %d\n", weight / 10); + } + if (ctx->is_422) { + weight = (weight * 100) / qos_weight->weight_422; + mfc_ctx_debug(3, "[QoS] 422foramt, weight: %d\n", weight / 10); + } + break; + case MFC_REG_CODEC_AV1_DEC: weight = (weight * 100) / qos_weight->weight_av1; mfc_ctx_debug(3, "[QoS] av1 codec, weight: %d\n", weight / 10); break; case MFC_REG_CODEC_VP9_DEC: + case MFC_REG_CODEC_VP9_ENC: weight = (weight * 100) / qos_weight->weight_vp8_vp9; mfc_ctx_debug(3, "[QoS] vp8, vp9 codec, weight: %d\n", weight / 10); @@ -109,6 +124,8 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l case MFC_REG_CODEC_VC1_RCV_DEC: case MFC_REG_CODEC_VC1_DEC: case MFC_REG_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: weight = (weight * 100) / qos_weight->weight_other_codec; mfc_ctx_debug(3, "[QoS] other codec, weight: %d\n", weight / 10); break; @@ -122,9 +139,13 @@ static inline unsigned long __mfc_qos_add_weight(struct mfc_ctx *ctx, unsigned l if (mfc_is_enc_bframe(ctx)) { weight = (weight * 100) / qos_weight->weight_bframe; mfc_ctx_debug(3, "[QoS] B frame encoding, weight: %d\n", weight / 10); - } else if (IS_H264_ENC(ctx) && (p->num_refs_for_p >= 2)) { + } else if ((IS_H264_ENC(ctx) || IS_HEVC_ENC(ctx) || IS_VP8_ENC(ctx) || + IS_VP9_ENC(ctx)) && (p->num_refs_for_p >= 2)) { weight = (weight * 100) / qos_weight->weight_num_of_ref; mfc_ctx_debug(3, "[QoS] num of ref >= 2, weight: %d\n", weight / 10); + } else if (IS_HEVC_ENC(ctx) && p->codec.hevc.general_pb_enable) { + weight = (weight * 100) / qos_weight->weight_gpb; + mfc_ctx_debug(3, "[QoS] Genaral PB, weight: %d\n", weight / 10); } } if (dec) { diff --git a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h index a127f330fe16..8526f5676761 100644 --- a/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h +++ b/drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h @@ -229,7 +229,11 @@ static inline int mfc_is_enc_bframe(struct mfc_ctx *ctx) if (IS_H264_ENC(ctx)) { num_hier_layer = p->codec.h264.num_hier_layer; hier_qp_type = (int)p->codec.h264.hier_qp_type; + } else if (IS_HEVC_ENC(ctx)) { + num_hier_layer = p->codec.hevc.num_hier_layer; + hier_qp_type = (int)p->codec.hevc.hier_qp_type; } + if (enc->params.num_b_frame || (num_hier_layer >= 2 && hier_qp_type == V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B)) @@ -402,7 +406,11 @@ static inline int mfc_enc_get_ts_delta(struct mfc_ctx *ctx) * so thie is also divided into pre-calculated 100. * (Preventing both overflow and calculation duplication) */ - ts_delta = ctx->src_ts.ts_last_interval / 100; + if (IS_H263_ENC(ctx)) + ts_delta = ctx->src_ts.ts_last_interval * + p->rc_framerate_res / USEC_PER_SEC; + else + ts_delta = ctx->src_ts.ts_last_interval / 100; } return ts_delta; } diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c index cc0a20bea33a..11e9c2622242 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c @@ -11,6 +11,25 @@ #include "mfc_core_reg_api.h" +static int __mfc_enc_check_adaptive_temporal_svc(int id, + struct mfc_enc_params *p, + struct temporal_layer_info + *temporal_LC) +{ + unsigned int new_num_layer = temporal_LC->temporal_layer_count; + unsigned int old_num_layer, ref_type; + + if (id == V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH) { + old_num_layer = p->codec.hevc.num_hier_layer; + ref_type = p->codec.hevc.hier_ref_type; + if (ref_type == 0 && old_num_layer != new_num_layer) + if (new_num_layer == 1 || old_num_layer == 1) + return 1; + } + + return 0; +} + static void __mfc_enc_store_buf_ctrls_temporal_svc(int id, struct mfc_enc_params *p, struct temporal_layer_info @@ -26,6 +45,24 @@ static void __mfc_enc_store_buf_ctrls_temporal_svc(int id, p->codec.h264.hier_bit_layer[i] = temporal_LC->temporal_layer_bitrate[i]; break; + case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH: + p->codec.hevc.num_hier_layer = num_layer & 0x7; + for (i = 0; i < (num_layer & 0x7); i++) + p->codec.hevc.hier_bit_layer[i] = + temporal_LC->temporal_layer_bitrate[i]; + break; + case V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH: + p->codec.vp8.num_hier_layer = num_layer & 0x7; + for (i = 0; i < (num_layer & 0x7); i++) + p->codec.vp8.hier_bit_layer[i] = + temporal_LC->temporal_layer_bitrate[i]; + break; + case V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH: + p->codec.vp9.num_hier_layer = num_layer & 0x7; + for (i = 0; i < (num_layer & 0x7); i++) + p->codec.vp9.hier_bit_layer[i] = + temporal_LC->temporal_layer_bitrate[i]; + break; default: break; } @@ -43,12 +80,21 @@ static void __mfc_core_enc_set_buf_ctrls_temporal_svc(struct mfc_core *core, struct mfc_enc_params *p = &enc->params; if (buf_ctrl->id - == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH) { + == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH || + buf_ctrl->id + == V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH || + buf_ctrl->id + == V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH || + buf_ctrl->id + == V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH) { memcpy(&temporal_LC, enc->sh_handle_svc.vaddr, sizeof(struct temporal_layer_info)); - if ((temporal_LC.temporal_layer_count & 0x7) < 1) { + if (((temporal_LC.temporal_layer_count & 0x7) < 1) || + (temporal_LC.temporal_layer_count > 3 && IS_VP8_ENC(ctx)) || + (temporal_LC.temporal_layer_count > 3 && + IS_VP9_ENC(ctx))) { /* clear NUM_T_LAYER_CHANGE */ value = MFC_CORE_READL(buf_ctrl->flag_addr); value &= ~BIT(10); @@ -61,7 +107,14 @@ static void __mfc_core_enc_set_buf_ctrls_temporal_svc(struct mfc_core *core, value = MFC_CORE_READL(buf_ctrl->flag_addr); value &= ~(0x3 << 21); - + /* Adaptive temporal SVC(layer count 1: IPPP, others: H-B) */ + if (__mfc_enc_check_adaptive_temporal_svc + (buf_ctrl->id, p, &temporal_LC)) { + if (temporal_LC.temporal_layer_count > 1) + value |= BIT(21); + else + value |= (0x2 << 21); + } MFC_CORE_WRITEL(value, buf_ctrl->flag_addr); /* Store temporal layer information */ diff --git a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c index 1a3cf7e76e29..9c5be84fcbc6 100644 --- a/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c +++ b/drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c @@ -1883,6 +1883,8 @@ static inline void __mfc_handle_nal_abort(struct mfc_core *core, if (ctx->type == MFCINST_ENCODER) { mfc_change_state(core_ctx, MFCINST_RUNNING_BUF_FULL); enc->buf_full = 0; + if (IS_VP8_ENC(ctx)) + mfc_err("stream buffer size isn't enough\n"); __mfc_handle_stream(core, ctx, reason); } else { mfc_change_state(core_ctx, MFCINST_ABORT); -- 2.34.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver 2025-09-30 4:03 ` [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver Himanshu Dewangan ` (28 preceding siblings ...) [not found] ` <CGME20250930035717epcas5p1dd561ae382ab7cbab428c528a046e989@epcas5p1.samsung.com> @ 2025-09-30 18:00 ` Nicolas Dufresne 2025-10-01 8:30 ` Hans Verkuil 30 siblings, 0 replies; 38+ messages in thread From: Nicolas Dufresne @ 2025-09-30 18:00 UTC (permalink / raw) To: Himanshu Dewangan, mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig [-- Attachment #1: Type: text/plain, Size: 21565 bytes --] Hi Himanshu, Le mardi 30 septembre 2025 à 09:33 +0530, Himanshu Dewangan a écrit : > Exynos MFC new driver upstream proposal > +++++++++++++++++++++++++++++++++++++++ > > The s5p-mfc driver in the kernel is quite outdated and has not kept up with the hardware advances of the MFC IP. > Going forward, we want to provide support for all the later versions of MFC in open source (both mobile and > ExynosAuto would be supported by Samsung) > > We (Samsung) would like to propose a new driver for the latest generation of Samsung MFC (Multi-Format Codec) hardware. > Although the kernel already contains a Samsung MFC driver (drivers/media/platform/s5p-mfc/), the newer hardware > diverges significantly from the previous generations, in features supported, register interface and in system integration. > This has necessitated a new driver, rather than updating the existing one. I wont deny that sometimes a new driver is needed, and I encourage you to defend your point. It does just justify any form of copy paste, also understand that device descriptions should be independent from the driver implementation. This is also why this is reviewed indecently, and DT nack won't ever be ignored by us. From quick walk through, I'm not convince this new driver actually makes use of everything new in Linux and Linux Media since 2011. It will be important for you to research what other modern drivers do, and what could apply to your code base. I'm quite skeptical with all the custom memory handling code, which generally indicates the miss-use of dma APIs. Realistically, you will have to split your driver in smaller parts and submit in a way we can see your design principle, and not just randomly unused files being added. Considering the state of it, we are up to 20 or 30 revision, with 29 patches, you won't get to the end of that process. V4L2 wise, one of the common mistakes is that you are adding a lot of new controls, most of them just slammed as vendor control without even trying to generalize. It did make sense in 2011, since there was no decoder to compare against, but today there is a lot of example and overlap between various brand. Omitting documentation and not keeping the API addition separate is also a no go for me. Make it very clear whenever something that will live in our API forever is to be added. We also added rules since 2011 that enforce drivers submitter to show that proper testing have occurred. Its starts with the very basic v4l2-compliance report which you have omitted. Since its codec driver, we require a summary of your conformance decoding testing done with fluster[] with the supported framework of your choice (for v4l2 stateful, ffmpeg and gstreamer are supported, you can add more, as long as they are open source). We also expect that your firmware has been submitted to linux-firmware with a link to that submission. Without that, we can only consider your set as an RFC to show people what is coming. regards, Nicolas > > > Current driver vs targetted driver comparison > +++++++++++++++++++++++++++++++++++++++++++++ > > Target Feature > Current mainline : Simple V4L2/ VB2 interface based encoder/ decoder > New proposed driver: Dual core support, NAL-q support, LLC, Coredump, performance > measurement, plugin driver architecture, hardware manager(meerkat), DRM/OTF, > Resource manager, bandwidth compression, New Pixel formats (NV12N, YV12, P010, > SBWC, RGB family), 10 bit support, HDR support, Prio and RR Process Scheduler support, > > Register map > Current mainline : Fixed register layout, compatible across s5p variants > New proposed driver: Completely redesigned register set, incompatible with old layout > > Command model > Current mainline : Mailbox-style command queue > New proposed driver: Ring-buffer command queue with different signaling > > Memory management > Current mainline : CMA-backed contiguous buffers, ION legacy > New proposed driver: dma-heap / scatter-gather buffers with strict alignment rules > > Firmware > Current mainline : Supports up to Firmware v12, Legacy binary format, loaded via shared mechanism > New proposed driver: New firmware format, different protocol for control messages. Support Firmware v13 onwards > > DT bindings > Current mainline : Single clock + reset, simple PM > New proposed driver: Multiple clocks, reset domains, runtime PM dependencies > > Error handling > Current mainline : Simple IRQ error flags > New proposed driver: Detailed error codes, recovery sequences required > > Code impact > Current mainline :~8k LOC, minimal conditionals > New proposed driver: ~65KLOC with full features > > > Plan for supporting latest MFC (Best balance between code clarity and long-term kernel health, while still respecting ABI and legacy users.) > 1 We propose a new driver (exynos-mfc) for the latest generation of Samsung MFC (Multi-Format Codec) hardware. > 2 MFC FW V6 to V12 will be supported by existing mainline (s5p-mfc) and later versions by Exynos-mfc driver > 3 The existing MFC driver will remain available for older SoC’s and will not be broken. The new driver will only bind > to new compatible strings in DT, avoiding regressions for legacy hardware. Samsung will take responsibility for > maintaining both drivers until the old one can be formally marked as “legacy.” > 4 Keep it buildable for old SoCs but clearly say new SoCs should use the new driver. > 5 VIDEO_SAMSUNG_S5P_MFC and VIDEO_EXYNOS_MFC will both be supported for an agreed time > 6 Long term Support for new driver - commitment from Samsung > 7 The hardware has diverged to the point where conditionally supporting both in one codebase is worse for long-term kernel health > 8 Splitting keeps the code clean, testable, and reviewable, while ensuring legacy users aren’t broken due to user space ABI guarantees. > This seems more clean and easier approach Both can coexist without code spaghetti. > > Features and description supported > ++++++++++++++++++++++++++++++++++ > > 1 MFC driver registration Probe functionality and video nodes registration > 2 MFC driver open & close support MFC firmware loading, "ls" & "cat" on the video nodes and udev rules on the video nodes > 3 H264 decoding H264 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 4 HEVC decoding HEVC decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 5 VP8 decoding VP8 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 6 VP9 decoding VP9 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 7 AV1 decoding AV1 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 8 H264 encoding H264 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 9 HEVC encoding HEVC encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 10 VP8 encoding VP8 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 11 VP9 encoding VP9 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 12 Debug fs support Debug fs to control the MFC functionalities > 13 Debug log support Debug logs to get on the dmesg prompt for debug purpose > 14 Debug SFR dump support MFC SFR dumps during failures > 15 NAL Queue mode control NAL Queue mode support > 16 Batch mode control Batch mode support > 17 HW supported YUV formats YUV 420, 422, 444 (planar, semi-planar) formats support as per MFC HW specification > 18 HW supported RGB formats RGB format support as per MFC HW specification > 19 Multi instance decoding/encoding Multi instance decoding/encoding > 20 Suspend and resume Suspend and resume support > 21 Runtime suspend and resume Runtime suspend and resume support > 22 Priority decoding (decoders) Priority decoding support > 23 Frame delay configuration (decoders) Frame delay configuration support > 24 Error handling and conceal control (decoders) HW/Platform limitations should be gracefully exited and, > bit stream errors should be reported or concealed with warning indication > 25 Reference frame control (encoders) Reference frame control support > 26 SPS/PPS control (encoders) SPS/PPS control support > 27 Loop filter control (encoders) Loop filter control support > 28 B frame support (encoders) B frame support > 29 GOP control (encoders) GOP control support > 30 Frame rate control (encoders) Frame rate control support > > Features to be supported in 2026 > +++++++++++++++++++++++++++++++++ > > 31 Bit rate control (encoders) Bit rate control support > 32 QP control (encoders) QP control support > 33 I/IDR control (encoders) I/IDR control support > 34 Scalable control (encoders) Scalable control support > 35 ROI control (encoders) ROI control support > 36 Multi slice control (encoders) Multi slice control support > 37 Profile/Level control (encoders) Profile/Level control support > 38 Padding control (encoders) Padding control support > 39 Aspect ratio control (encoders) Aspect ratio control support > 40 Buffer full handling (encoders) Buffer full handling support > 41 SBWC SBWC bandwidth compression support > 42 10-bit support 10-bit support as per MFC HW specification > 43 Secure signed FW support Security signed FW support > 44 Secure playback DRM content playback for decoders > 45 HDR Support (decoders) HDR metadata support > 46 Dynamic resolution change Dynamic resolution change support > > Nagaraju Siddineni (29): > dt-bindings: media: mfc: Add Exynos MFC devicetree binding > arm64: dts: mfc: Add MFC device tree for Auto V920 SoC > media: mfc: Add MFC driver data structures and debugging macros > media: mfc: Add full register map and bit definitions for MFC hardware > media: mfc: Add MFC driver header files and core utilities > media: mfc: Add MFC core hardware register and debugfs APIs > media: mfc: Add MFC core command, hwlock, ISR and run functionalities > media: mfc: Add Exynos‑MFC driver probe support > media: mfc: Add bus‑devfreq, QoS, multi‑view and control > infrastructure > media: mfc: Add buffer‑queue and IOVMM support > media: mfc: Add rate‑calculation framework and memory utilities > media: mfc: Introduce QoS support and instance context handling > media: mfc: Add decoder core sync functions > media: mfc: Add buffer‑control framework > media: mfc: Add decoder resource‑management (RM) support and > load‑balancing > media: mfc: Enhance HW‑lock handling, scheduling and error recovery > media: mfc: Add VB2 decoder support > media: mfc: Add V4L2 decoder driver > media: mfc: Add QoS, Butler workqueue, and priority‑based scheduling > media: mfc: Add H264 decoder support > media: mfc: Add multi‑codec support & QoS improvements > media: mfc: Add H.264 encoder support with buffer and QoS improvements > media: mfc: Add encoder parameters, ROI & QoS support > media: mfc: Add encoder VB2 support to driver > media: mfc: Add encoder v4l2 driver interface > media: mfc: Add full encoder support > media: mfc: Add H.264 encoder support > media: mfc: Add AVC, VP8, VP9, and HEVC encoding support > media: mfc: Hardware‑accelerated encoding support > > .../bindings/media/samsung,exynos-mfc.yaml | 77 + > MAINTAINERS | 10 + > .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 630 +++ > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 + > drivers/media/platform/samsung/Kconfig | 7 + > drivers/media/platform/samsung/Makefile | 1 + > .../media/platform/samsung/exynos-mfc/Kconfig | 34 + > .../platform/samsung/exynos-mfc/Makefile | 26 + > .../samsung/exynos-mfc/base/mfc_buf.c | 765 +++ > .../samsung/exynos-mfc/base/mfc_buf.h | 43 + > .../samsung/exynos-mfc/base/mfc_common.h | 444 ++ > .../samsung/exynos-mfc/base/mfc_data_struct.h | 2014 +++++++ > .../samsung/exynos-mfc/base/mfc_debug.h | 247 + > .../samsung/exynos-mfc/base/mfc_format.h | 316 ++ > .../samsung/exynos-mfc/base/mfc_macros.h | 95 + > .../samsung/exynos-mfc/base/mfc_media.h | 554 ++ > .../samsung/exynos-mfc/base/mfc_mem.c | 995 ++++ > .../samsung/exynos-mfc/base/mfc_mem.h | 155 + > .../samsung/exynos-mfc/base/mfc_qos.c | 1070 ++++ > .../samsung/exynos-mfc/base/mfc_qos.h | 99 + > .../samsung/exynos-mfc/base/mfc_queue.c | 966 ++++ > .../samsung/exynos-mfc/base/mfc_queue.h | 158 + > .../exynos-mfc/base/mfc_rate_calculate.c | 640 +++ > .../exynos-mfc/base/mfc_rate_calculate.h | 106 + > .../samsung/exynos-mfc/base/mfc_regs.h | 58 + > .../samsung/exynos-mfc/base/mfc_regs_mfc.h | 1002 ++++ > .../samsung/exynos-mfc/base/mfc_sched.h | 30 + > .../samsung/exynos-mfc/base/mfc_utils.c | 401 ++ > .../samsung/exynos-mfc/base/mfc_utils.h | 481 ++ > .../media/platform/samsung/exynos-mfc/mfc.c | 1366 +++++ > .../platform/samsung/exynos-mfc/mfc_core.c | 703 +++ > .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 543 ++ > .../samsung/exynos-mfc/mfc_core_cmd.c | 576 ++ > .../samsung/exynos-mfc/mfc_core_cmd.h | 41 + > .../samsung/exynos-mfc/mfc_core_enc_param.c | 1463 ++++++ > .../samsung/exynos-mfc/mfc_core_enc_param.h | 23 + > .../samsung/exynos-mfc/mfc_core_hw_reg_api.c | 122 + > .../samsung/exynos-mfc/mfc_core_hw_reg_api.h | 144 + > .../samsung/exynos-mfc/mfc_core_hwlock.c | 761 +++ > .../samsung/exynos-mfc/mfc_core_hwlock.h | 80 + > .../samsung/exynos-mfc/mfc_core_intlock.c | 98 + > .../samsung/exynos-mfc/mfc_core_intlock.h | 20 + > .../samsung/exynos-mfc/mfc_core_isr.c | 2104 ++++++++ > .../samsung/exynos-mfc/mfc_core_isr.h | 25 + > .../samsung/exynos-mfc/mfc_core_ops.c | 813 +++ > .../samsung/exynos-mfc/mfc_core_ops.h | 16 + > .../platform/samsung/exynos-mfc/mfc_core_pm.c | 209 + > .../platform/samsung/exynos-mfc/mfc_core_pm.h | 33 + > .../samsung/exynos-mfc/mfc_core_reg_api.c | 597 +++ > .../samsung/exynos-mfc/mfc_core_reg_api.h | 380 ++ > .../samsung/exynos-mfc/mfc_core_run.c | 541 ++ > .../samsung/exynos-mfc/mfc_core_run.h | 35 + > .../samsung/exynos-mfc/mfc_core_sched_prio.c | 431 ++ > .../samsung/exynos-mfc/mfc_core_sync.c | 423 ++ > .../samsung/exynos-mfc/mfc_core_sync.h | 34 + > .../samsung/exynos-mfc/mfc_ctx_ctrl.c | 1469 ++++++ > .../platform/samsung/exynos-mfc/mfc_debugfs.c | 248 + > .../platform/samsung/exynos-mfc/mfc_debugfs.h | 20 + > .../samsung/exynos-mfc/mfc_dec_v4l2.c | 1739 +++++++ > .../samsung/exynos-mfc/mfc_dec_v4l2.h | 20 + > .../platform/samsung/exynos-mfc/mfc_dec_vb2.c | 394 ++ > .../platform/samsung/exynos-mfc/mfc_dec_vb2.h | 19 + > .../samsung/exynos-mfc/mfc_enc_v4l2.c | 4614 +++++++++++++++++ > .../samsung/exynos-mfc/mfc_enc_v4l2.h | 20 + > .../platform/samsung/exynos-mfc/mfc_enc_vb2.c | 443 ++ > .../platform/samsung/exynos-mfc/mfc_enc_vb2.h | 19 + > .../platform/samsung/exynos-mfc/mfc_rm.c | 2652 ++++++++++ > .../platform/samsung/exynos-mfc/mfc_rm.h | 110 + > 68 files changed, 34773 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi > create mode 100644 drivers/media/platform/samsung/exynos-mfc/Kconfig > create mode 100644 drivers/media/platform/samsung/exynos-mfc/Makefile > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.h [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver 2025-09-30 4:03 ` [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver Himanshu Dewangan ` (29 preceding siblings ...) 2025-09-30 18:00 ` [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver Nicolas Dufresne @ 2025-10-01 8:30 ` Hans Verkuil 30 siblings, 0 replies; 38+ messages in thread From: Hans Verkuil @ 2025-10-01 8:30 UTC (permalink / raw) To: Himanshu Dewangan, mchehab, robh, krzk+dt, conor+dt, sumit.semwal, christian.koenig, alim.akhtar, manjun, nagaraju.s, ih0206.lee, jehyung.lee, Nicolas Dufresne Cc: linux-arm-kernel, linux-media, devicetree, linux-samsung-soc, linux-kernel, dri-devel, linaro-mm-sig Hi Himanshu, On 30/09/2025 06:03, Himanshu Dewangan wrote: > Exynos MFC new driver upstream proposal > +++++++++++++++++++++++++++++++++++++++ > > The s5p-mfc driver in the kernel is quite outdated and has not kept up with the hardware advances of the MFC IP. > Going forward, we want to provide support for all the later versions of MFC in open source (both mobile and > ExynosAuto would be supported by Samsung) > > We (Samsung) would like to propose a new driver for the latest generation of Samsung MFC (Multi-Format Codec) hardware. > Although the kernel already contains a Samsung MFC driver (drivers/media/platform/s5p-mfc/), the newer hardware > diverges significantly from the previous generations, in features supported, register interface and in system integration. > This has necessitated a new driver, rather than updating the existing one. I did some (admittedly limited) comparison between the MFC hardware registers in patch 04/29 and what is in s5p-mfc and it did look like an incremental update, not a complete register redesign. So I am not convinced from that that a new driver is needed. In addition, a huge patch bomb like this is unreviewable and so I am just going to give a few high-level remarks based on a quick scan of the patches. 1) Clearly you never ran v4l2-compliance with this new driver as it would fail immediately on the VIDIOC_QUERYCAP ioctl. It's a M2M device, so it should use either V4L2_CAP_VIDEO_M2M or V4L2_CAP_VIDEO_M2M_MPLANE, not a mix of output and capture caps. I suspect that v4l2-compliance will fail on many issues. 2) I noticed that there is no VB2_MMAP support. No idea why not, and all drivers with streaming I/O support must support VB2_MMAP. 3) Lots of controls are added, none of them documented or even defined in a public header. It's part of the public API, so that must all be present in include/uapi/linux. Just 'git grep' for CID_MPEG_MFC51 to see how it should be done. I suspect that more than a few of these controls are either duplicated of already existing controls or should be promoted from MFC-specific controls to generic controls. But without documentation we can't tell. 4) Since this is a new M2M driver I would expect it to use the v4l2-mem2mem framework, instead it appears to be all homegrown. The only reason the existing s5p-mfc driver doesn't use that framework is because it predates it. 5) It clearly doesn't follow the stateful encoder/decoder interface spec as detailed in the V4L2 spec: https://linuxtv.org/downloads/v4l-dvb-apis-new/userspace-api/v4l/dev-mem2mem.html Even s5p-mfc does at least attempt to follow that (I'm not sure how complete support is, given that it's an old driver, but it tries). 6) Minor issue: don't set the .wait_prepare/finish vb2_ops callbacks: these callbacks are slated for removal. Instead set the vb2_queue lock field to the mutex &dev->mfc_mutex. There are probably many other things that need addressing, but I stopped there. I would need convincing (and based on his reply, Krzysztof as well) that a new driver is the right approach. If it is, then start small: just the decoder supporting just one codec. Exclude all the fancy features, just start with the basics. The recently merged Qualcomm iris driver can serve as inspiration: drivers/media/platform/qcom/iris/ I'll mark this series as Rejected in patchwork. It's always a very bad idea to try to upstream a huge driver with zillions of features. If, like this one, it has serious design issues, then you did a lot of work for nothing :-( Apologies for the bad news, Regards, Hans > > > Current driver vs targetted driver comparison > +++++++++++++++++++++++++++++++++++++++++++++ > > Target Feature > Current mainline : Simple V4L2/ VB2 interface based encoder/ decoder > New proposed driver: Dual core support, NAL-q support, LLC, Coredump, performance > measurement, plugin driver architecture, hardware manager(meerkat), DRM/OTF, > Resource manager, bandwidth compression, New Pixel formats (NV12N, YV12, P010, > SBWC, RGB family), 10 bit support, HDR support, Prio and RR Process Scheduler support, > > Register map > Current mainline : Fixed register layout, compatible across s5p variants > New proposed driver: Completely redesigned register set, incompatible with old layout > > Command model > Current mainline : Mailbox-style command queue > New proposed driver: Ring-buffer command queue with different signaling > > Memory management > Current mainline : CMA-backed contiguous buffers, ION legacy > New proposed driver: dma-heap / scatter-gather buffers with strict alignment rules > > Firmware > Current mainline : Supports up to Firmware v12, Legacy binary format, loaded via shared mechanism > New proposed driver: New firmware format, different protocol for control messages. Support Firmware v13 onwards > > DT bindings > Current mainline : Single clock + reset, simple PM > New proposed driver: Multiple clocks, reset domains, runtime PM dependencies > > Error handling > Current mainline : Simple IRQ error flags > New proposed driver: Detailed error codes, recovery sequences required > > Code impact > Current mainline :~8k LOC, minimal conditionals > New proposed driver: ~65KLOC with full features > > > Plan for supporting latest MFC (Best balance between code clarity and long-term kernel health, while still respecting ABI and legacy users.) > 1 We propose a new driver (exynos-mfc) for the latest generation of Samsung MFC (Multi-Format Codec) hardware. > 2 MFC FW V6 to V12 will be supported by existing mainline (s5p-mfc) and later versions by Exynos-mfc driver > 3 The existing MFC driver will remain available for older SoC’s and will not be broken. The new driver will only bind > to new compatible strings in DT, avoiding regressions for legacy hardware. Samsung will take responsibility for > maintaining both drivers until the old one can be formally marked as “legacy.” > 4 Keep it buildable for old SoCs but clearly say new SoCs should use the new driver. > 5 VIDEO_SAMSUNG_S5P_MFC and VIDEO_EXYNOS_MFC will both be supported for an agreed time > 6 Long term Support for new driver - commitment from Samsung > 7 The hardware has diverged to the point where conditionally supporting both in one codebase is worse for long-term kernel health > 8 Splitting keeps the code clean, testable, and reviewable, while ensuring legacy users aren’t broken due to user space ABI guarantees. > This seems more clean and easier approach Both can coexist without code spaghetti. > > Features and description supported > ++++++++++++++++++++++++++++++++++ > > 1 MFC driver registration Probe functionality and video nodes registration > 2 MFC driver open & close support MFC firmware loading, "ls" & "cat" on the video nodes and udev rules on the video nodes > 3 H264 decoding H264 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 4 HEVC decoding HEVC decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 5 VP8 decoding VP8 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 6 VP9 decoding VP9 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 7 AV1 decoding AV1 decoding support - HW supported profiles & levels (YUV420 Semi-Planar, 8-bit, min/max resolution) > 8 H264 encoding H264 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 9 HEVC encoding HEVC encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 10 VP8 encoding VP8 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 11 VP9 encoding VP9 encoding support - Basic encoding (YUV420 Semi-Planar, 8-bit, min/max resolution) > 12 Debug fs support Debug fs to control the MFC functionalities > 13 Debug log support Debug logs to get on the dmesg prompt for debug purpose > 14 Debug SFR dump support MFC SFR dumps during failures > 15 NAL Queue mode control NAL Queue mode support > 16 Batch mode control Batch mode support > 17 HW supported YUV formats YUV 420, 422, 444 (planar, semi-planar) formats support as per MFC HW specification > 18 HW supported RGB formats RGB format support as per MFC HW specification > 19 Multi instance decoding/encoding Multi instance decoding/encoding > 20 Suspend and resume Suspend and resume support > 21 Runtime suspend and resume Runtime suspend and resume support > 22 Priority decoding (decoders) Priority decoding support > 23 Frame delay configuration (decoders) Frame delay configuration support > 24 Error handling and conceal control (decoders) HW/Platform limitations should be gracefully exited and, > bit stream errors should be reported or concealed with warning indication > 25 Reference frame control (encoders) Reference frame control support > 26 SPS/PPS control (encoders) SPS/PPS control support > 27 Loop filter control (encoders) Loop filter control support > 28 B frame support (encoders) B frame support > 29 GOP control (encoders) GOP control support > 30 Frame rate control (encoders) Frame rate control support > > Features to be supported in 2026 > +++++++++++++++++++++++++++++++++ > > 31 Bit rate control (encoders) Bit rate control support > 32 QP control (encoders) QP control support > 33 I/IDR control (encoders) I/IDR control support > 34 Scalable control (encoders) Scalable control support > 35 ROI control (encoders) ROI control support > 36 Multi slice control (encoders) Multi slice control support > 37 Profile/Level control (encoders) Profile/Level control support > 38 Padding control (encoders) Padding control support > 39 Aspect ratio control (encoders) Aspect ratio control support > 40 Buffer full handling (encoders) Buffer full handling support > 41 SBWC SBWC bandwidth compression support > 42 10-bit support 10-bit support as per MFC HW specification > 43 Secure signed FW support Security signed FW support > 44 Secure playback DRM content playback for decoders > 45 HDR Support (decoders) HDR metadata support > 46 Dynamic resolution change Dynamic resolution change support > > Nagaraju Siddineni (29): > dt-bindings: media: mfc: Add Exynos MFC devicetree binding > arm64: dts: mfc: Add MFC device tree for Auto V920 SoC > media: mfc: Add MFC driver data structures and debugging macros > media: mfc: Add full register map and bit definitions for MFC hardware > media: mfc: Add MFC driver header files and core utilities > media: mfc: Add MFC core hardware register and debugfs APIs > media: mfc: Add MFC core command, hwlock, ISR and run functionalities > media: mfc: Add Exynos‑MFC driver probe support > media: mfc: Add bus‑devfreq, QoS, multi‑view and control > infrastructure > media: mfc: Add buffer‑queue and IOVMM support > media: mfc: Add rate‑calculation framework and memory utilities > media: mfc: Introduce QoS support and instance context handling > media: mfc: Add decoder core sync functions > media: mfc: Add buffer‑control framework > media: mfc: Add decoder resource‑management (RM) support and > load‑balancing > media: mfc: Enhance HW‑lock handling, scheduling and error recovery > media: mfc: Add VB2 decoder support > media: mfc: Add V4L2 decoder driver > media: mfc: Add QoS, Butler workqueue, and priority‑based scheduling > media: mfc: Add H264 decoder support > media: mfc: Add multi‑codec support & QoS improvements > media: mfc: Add H.264 encoder support with buffer and QoS improvements > media: mfc: Add encoder parameters, ROI & QoS support > media: mfc: Add encoder VB2 support to driver > media: mfc: Add encoder v4l2 driver interface > media: mfc: Add full encoder support > media: mfc: Add H.264 encoder support > media: mfc: Add AVC, VP8, VP9, and HEVC encoding support > media: mfc: Hardware‑accelerated encoding support > > .../bindings/media/samsung,exynos-mfc.yaml | 77 + > MAINTAINERS | 10 + > .../dts/exynos/exynosautov920-evt2-mfc.dtsi | 630 +++ > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 1 + > drivers/media/platform/samsung/Kconfig | 7 + > drivers/media/platform/samsung/Makefile | 1 + > .../media/platform/samsung/exynos-mfc/Kconfig | 34 + > .../platform/samsung/exynos-mfc/Makefile | 26 + > .../samsung/exynos-mfc/base/mfc_buf.c | 765 +++ > .../samsung/exynos-mfc/base/mfc_buf.h | 43 + > .../samsung/exynos-mfc/base/mfc_common.h | 444 ++ > .../samsung/exynos-mfc/base/mfc_data_struct.h | 2014 +++++++ > .../samsung/exynos-mfc/base/mfc_debug.h | 247 + > .../samsung/exynos-mfc/base/mfc_format.h | 316 ++ > .../samsung/exynos-mfc/base/mfc_macros.h | 95 + > .../samsung/exynos-mfc/base/mfc_media.h | 554 ++ > .../samsung/exynos-mfc/base/mfc_mem.c | 995 ++++ > .../samsung/exynos-mfc/base/mfc_mem.h | 155 + > .../samsung/exynos-mfc/base/mfc_qos.c | 1070 ++++ > .../samsung/exynos-mfc/base/mfc_qos.h | 99 + > .../samsung/exynos-mfc/base/mfc_queue.c | 966 ++++ > .../samsung/exynos-mfc/base/mfc_queue.h | 158 + > .../exynos-mfc/base/mfc_rate_calculate.c | 640 +++ > .../exynos-mfc/base/mfc_rate_calculate.h | 106 + > .../samsung/exynos-mfc/base/mfc_regs.h | 58 + > .../samsung/exynos-mfc/base/mfc_regs_mfc.h | 1002 ++++ > .../samsung/exynos-mfc/base/mfc_sched.h | 30 + > .../samsung/exynos-mfc/base/mfc_utils.c | 401 ++ > .../samsung/exynos-mfc/base/mfc_utils.h | 481 ++ > .../media/platform/samsung/exynos-mfc/mfc.c | 1366 +++++ > .../platform/samsung/exynos-mfc/mfc_core.c | 703 +++ > .../samsung/exynos-mfc/mfc_core_buf_ctrl.c | 543 ++ > .../samsung/exynos-mfc/mfc_core_cmd.c | 576 ++ > .../samsung/exynos-mfc/mfc_core_cmd.h | 41 + > .../samsung/exynos-mfc/mfc_core_enc_param.c | 1463 ++++++ > .../samsung/exynos-mfc/mfc_core_enc_param.h | 23 + > .../samsung/exynos-mfc/mfc_core_hw_reg_api.c | 122 + > .../samsung/exynos-mfc/mfc_core_hw_reg_api.h | 144 + > .../samsung/exynos-mfc/mfc_core_hwlock.c | 761 +++ > .../samsung/exynos-mfc/mfc_core_hwlock.h | 80 + > .../samsung/exynos-mfc/mfc_core_intlock.c | 98 + > .../samsung/exynos-mfc/mfc_core_intlock.h | 20 + > .../samsung/exynos-mfc/mfc_core_isr.c | 2104 ++++++++ > .../samsung/exynos-mfc/mfc_core_isr.h | 25 + > .../samsung/exynos-mfc/mfc_core_ops.c | 813 +++ > .../samsung/exynos-mfc/mfc_core_ops.h | 16 + > .../platform/samsung/exynos-mfc/mfc_core_pm.c | 209 + > .../platform/samsung/exynos-mfc/mfc_core_pm.h | 33 + > .../samsung/exynos-mfc/mfc_core_reg_api.c | 597 +++ > .../samsung/exynos-mfc/mfc_core_reg_api.h | 380 ++ > .../samsung/exynos-mfc/mfc_core_run.c | 541 ++ > .../samsung/exynos-mfc/mfc_core_run.h | 35 + > .../samsung/exynos-mfc/mfc_core_sched_prio.c | 431 ++ > .../samsung/exynos-mfc/mfc_core_sync.c | 423 ++ > .../samsung/exynos-mfc/mfc_core_sync.h | 34 + > .../samsung/exynos-mfc/mfc_ctx_ctrl.c | 1469 ++++++ > .../platform/samsung/exynos-mfc/mfc_debugfs.c | 248 + > .../platform/samsung/exynos-mfc/mfc_debugfs.h | 20 + > .../samsung/exynos-mfc/mfc_dec_v4l2.c | 1739 +++++++ > .../samsung/exynos-mfc/mfc_dec_v4l2.h | 20 + > .../platform/samsung/exynos-mfc/mfc_dec_vb2.c | 394 ++ > .../platform/samsung/exynos-mfc/mfc_dec_vb2.h | 19 + > .../samsung/exynos-mfc/mfc_enc_v4l2.c | 4614 +++++++++++++++++ > .../samsung/exynos-mfc/mfc_enc_v4l2.h | 20 + > .../platform/samsung/exynos-mfc/mfc_enc_vb2.c | 443 ++ > .../platform/samsung/exynos-mfc/mfc_enc_vb2.h | 19 + > .../platform/samsung/exynos-mfc/mfc_rm.c | 2652 ++++++++++ > .../platform/samsung/exynos-mfc/mfc_rm.h | 110 + > 68 files changed, 34773 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/samsung,exynos-mfc.yaml > create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-evt2-mfc.dtsi > create mode 100644 drivers/media/platform/samsung/exynos-mfc/Kconfig > create mode 100644 drivers/media/platform/samsung/exynos-mfc/Makefile > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_buf.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_common.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_data_struct.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_debug.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_format.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_macros.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_media.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_mem.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_qos.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_queue.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_rate_calculate.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_regs_mfc.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_sched.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/base/mfc_utils.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_buf_ctrl.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_cmd.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_enc_param.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hw_reg_api.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_hwlock.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_intlock.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_isr.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_ops.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_pm.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_reg_api.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_run.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sched_prio.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_core_sync.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_ctx_ctrl.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_debugfs.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_v4l2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_dec_vb2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_v4l2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_enc_vb2.h > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.c > create mode 100644 drivers/media/platform/samsung/exynos-mfc/mfc_rm.h > ^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2025-10-01 8:30 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20250930035518epcas5p2395afdb6f22d2a6b42f9daaec6bc3c1f@epcas5p2.samsung.com>
2025-09-30 4:03 ` [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver Himanshu Dewangan
[not found] ` <CGME20250930035521epcas5p428367b20b9498eb8862d17f4bb75f663@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 01/29] dt-bindings: media: mfc: Add Exynos MFC devicetree binding Himanshu Dewangan
2025-09-30 6:01 ` Krzysztof Kozlowski
[not found] ` <CGME20250930035525epcas5p3a1238a3a7bc6e52113838397187e36ba@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 02/29] arm64: dts: mfc: Add MFC device tree for Auto V920 SoC Himanshu Dewangan
2025-09-30 6:40 ` Krzysztof Kozlowski
[not found] ` <CGME20250930035527epcas5p3e6b8c8040341cd99e6e73c9db7a4d74e@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 03/29] media: mfc: Add MFC driver data structures and debugging macros Himanshu Dewangan
[not found] ` <CGME20250930035531epcas5p22f3bc84d7e1f3bce78459f4f159e3d1a@epcas5p2.samsung.com>
2025-09-30 4:03 ` [PATCH 04/29] media: mfc: Add full register map and bit definitions for MFC hardware Himanshu Dewangan
[not found] ` <CGME20250930035535epcas5p3def6efaf88b04542ab6c27ecaa8e86fd@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 05/29] media: mfc: Add MFC driver header files and core utilities Himanshu Dewangan
[not found] ` <CGME20250930035540epcas5p356f8403ee4d973701a74cf96f6e9c19b@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 06/29] media: mfc: Add MFC core hardware register and debugfs APIs Himanshu Dewangan
[not found] ` <CGME20250930035547epcas5p11f579ca8f8a83767cbb2b632fa9cd6f7@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 07/29] media: mfc: Add MFC core command, hwlock, ISR and run functionalities Himanshu Dewangan
[not found] ` <CGME20250930035551epcas5p4ee7cb5af08eadb2f5ed6e5eaa06a60a9@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 08/29] media: mfc: Add Exynos‑MFC driver probe support Himanshu Dewangan
2025-09-30 5:54 ` Krzysztof Kozlowski
2025-09-30 15:46 ` Marek Szyprowski
2025-09-30 22:59 ` Krzysztof Kozlowski
2025-09-30 23:06 ` Krzysztof Kozlowski
[not found] ` <CGME20250930035557epcas5p2efa9fa41298b8a9aabb46e5fac70d49e@epcas5p2.samsung.com>
2025-09-30 4:03 ` [PATCH 09/29] media: mfc: Add bus‑devfreq, QoS, multi‑view and control infrastructure Himanshu Dewangan
[not found] ` <CGME20250930035600epcas5p13782313e204588986f44514d005ccf70@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 10/29] media: mfc: Add buffer‑queue and IOVMM support Himanshu Dewangan
[not found] ` <CGME20250930035606epcas5p3c38c2ba8148bd90a56415f544c5072f1@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 11/29] media: mfc: Add rate‑calculation framework and memory utilities Himanshu Dewangan
[not found] ` <CGME20250930035610epcas5p3c64bccc78b92b0bb907a73615103ebd3@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 12/29] media: mfc: Introduce QoS support and instance context handling Himanshu Dewangan
[not found] ` <CGME20250930035616epcas5p3696fbcd8fbe66221433651290859e198@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 13/29] media: mfc: Add decoder core sync functions Himanshu Dewangan
[not found] ` <CGME20250930035619epcas5p1a3a8cd3e71442235e571c840a78286d8@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 14/29] media: mfc: Add buffer‑control framework Himanshu Dewangan
[not found] ` <CGME20250930035623epcas5p3447703a70d34c96a719a3e92d0ff6d39@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 15/29] media: mfc: Add decoder resource‑management (RM) support and load‑balancing Himanshu Dewangan
[not found] ` <CGME20250930035628epcas5p1c0ebecf84b6b9c17aa291b097e411df0@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 16/29] media: mfc: Enhance HW‑lock handling, scheduling and error recovery Himanshu Dewangan
[not found] ` <CGME20250930035633epcas5p3d859613b1d1d3319ded26da626c959bc@epcas5p3.samsung.com>
2025-09-30 4:03 ` [PATCH 17/29] media: mfc: Add VB2 decoder support Himanshu Dewangan
[not found] ` <CGME20250930035637epcas5p4d52ed2f59e17862cd7d7a650fa01bf44@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 18/29] media: mfc: Add V4L2 decoder driver Himanshu Dewangan
[not found] ` <CGME20250930035641epcas5p4a5011f149b293c1b5aee60df0447666c@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 19/29] media: mfc: Add QoS, Butler workqueue, and priority‑based scheduling Himanshu Dewangan
[not found] ` <CGME20250930035644epcas5p178155478c949c231c14a131b00f23bc1@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 20/29] media: mfc: Add H264 decoder support Himanshu Dewangan
[not found] ` <CGME20250930035646epcas5p2f4a9694c7f89ffe27384f8b7b8227802@epcas5p2.samsung.com>
2025-09-30 4:03 ` [PATCH 21/29] media: mfc: Add multi‑codec support & QoS improvements Himanshu Dewangan
[not found] ` <CGME20250930035651epcas5p2a45576829011bbf653c725b352c65140@epcas5p2.samsung.com>
2025-09-30 4:03 ` [PATCH 22/29] media: mfc: Add H.264 encoder support with buffer and " Himanshu Dewangan
[not found] ` <CGME20250930035654epcas5p1cbb6f3d0fe0dd25758085d041f020846@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 23/29] media: mfc: Add encoder parameters, ROI & QoS support Himanshu Dewangan
[not found] ` <CGME20250930035657epcas5p17d3e94c7c1ba5eeace97b0ff81053653@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 24/29] media: mfc: Add encoder VB2 support to driver Himanshu Dewangan
[not found] ` <CGME20250930035700epcas5p1860af28e8a9e99d32b94fa1e97ab5456@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 25/29] media: mfc: Add encoder v4l2 driver interface Himanshu Dewangan
[not found] ` <CGME20250930035703epcas5p18e09c3e9e07401f4b268ea77bc831987@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 26/29] media: mfc: Add full encoder support Himanshu Dewangan
[not found] ` <CGME20250930035706epcas5p4530de9edacfc86c0ae1ab9de2d2b0695@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 27/29] media: mfc: Add H.264 " Himanshu Dewangan
[not found] ` <CGME20250930035711epcas5p437e54e8c277ee98149fccb2d984a0e55@epcas5p4.samsung.com>
2025-09-30 4:03 ` [PATCH 28/29] media: mfc: Add AVC, VP8, VP9, and HEVC encoding support Himanshu Dewangan
[not found] ` <CGME20250930035717epcas5p1dd561ae382ab7cbab428c528a046e989@epcas5p1.samsung.com>
2025-09-30 4:03 ` [PATCH 29/29] media: mfc: Hardware‑accelerated " Himanshu Dewangan
2025-09-30 18:00 ` [PATCH 00/29] media: codec: add new Samsung Exynos-MFC driver Nicolas Dufresne
2025-10-01 8:30 ` Hans Verkuil
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